SGS Thomson Microelectronics TDA7427AD, TDA7427AD1 Datasheet

TDA7427A

AM-FM RADIO FREQUENCY SYNTHESIZER

AND IF COUNTER

ON-CHIP REFERENCE OSCILLATOR AND
PROGRAMMABLEIF COUNTER

VHF INPUT AND PRECOUNTER FOR FRE­QUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)

HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORTWAVE BAND)

IN-LOCK DETECTOR FOR SEARCH/STOP
STATIONFUNCTION

STAND-BY MODE FOR LOW POWER CON­SUMPTION

HIGH CURRENT SOURCE FOR 0.5ms
LOCK-INTIME

DIGITAL PORT EXTENSION WITH SIX OUT­PUTS FOR FLEXIBILITYIN APPLICATION

FULLY PROGRAMMABLEBYI

2

C BUS

DESCRIPTION

The TDA7427A is a PLL frequency synthesizer

with an additional IF counting system that per­forms all the functionsneeded in a complete PLL
radio tuning system for conventional and high
speedRDS tuners. The devicehas dedicatedout­puts for IN-LOCK detectionand Search/Stopsta­tion.

July 1998



SWITCH

AM/FM

PRECOUNTER

:32/33

5 BIT

PROG.

COUNTER

11-21 BITPROG COUNTER

SWITCH

SWM/DIR

11 BIT

PROG

COUNTER

INLOCK

DETECTOR

PHASE

COMP

REF

OSCILLATOR

CHARGE

PUMP

-

+

SWITCH
LP1/LP2

14 BIT

PROG

COUNTER

TIMER CONTROL

I2C BUS

INTERFACE

TEST

LOGIC

PORT EXTENSION

FM_IN

AM_IN

OSCIN

ADDR

SCL

SDA

IF_AM

IF_FM

DOUT2 DOUT3 DOUT4 DOUT5 DOUT6

VDD2

GNDAN

VREF

LP_OUT

VDD1

LP_FM

LP_AM

D95AU372D

SWITCH

SWM/DIR

16 BIT

PROG

COUNTER

VDD1

OSCOUT

SSTOP

GNDDIG

LP_HC

DOUT1/INLOCK

24

25

9
10

20
12
13

27

21

22

14

15

16 185678

26

4

28

1

3

2

17

HFREF

19

SUPPLY

&

POWER-ON

RESET

SWITCH

AM/FM

SWITCH

OUT

BLOCK DIAGRAM

ORDERING NUMBERS:

TDA7427AAD (TSSOP28)
TDA7427AAD1 (SO28)

TSSOP28

SO28

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ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD1

Supply Voltage - 0.3 to + 7 V

V

DD2

Supply Voltage - 0.3 to+ 11 V

P

tot

Total PowerDissipation 300 mW

T

stg

Storage Temperature - 55 to + 150

o

C

T

amb

Ambient Temperature -40 to + 85

o

C

THERMAL DATA

Symbol Parameter TSSOP28 SO 28 Unit

R

th j-amb

Thermal ResistanceJunction-Ambient 160 65

o

C/W

LP_FM
LP_HC

LP_AM

VREF

DOUT3

DOUT5

DOUT4

DOUT6

OSCIN ADDR

VDD1

GND-DIG

FM_IN
N.C.

AM_IN

GND-AN

VDD2

LPOUT1

3

2

4
5
6
7
8
9

26
25
24
23
22

20

21

19

27

10

28

OSCOUT HFREF

D95AU374C

N.C.
SCL
SDA SSTOP

DOUT1/INLOCK

DOUT211
12
13

18

16

17

1514IF_AM IF_FM

PIN CONNECTION

TDA7427A

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PIN DESCRIPTION

PIN SYMBOL DESCRIPTION

1

LP_FM FilterOPAMP input,charge pump output(FM mode)

2

LP_HC FilterOPAMP input,charge pump output(high current mode)

3

LP_AM FilterOPAMP input, charge pump output(AM mode)

4

VREF OPAMPreference voltage

5

DOUT3 Digital Output 3 (open collector)

6

DOUT4 Digital Output 4 (open collector)

7

DOUT5 Digital Output 5 (open collector)

8

DOUT6 Digital Output 6 (open collector)

9

OSCIN Reference Oscillator Input

10

OSCOUT ReferenceOscillator Output

11

N.C. Not connected

12

SCL I2C bus clock input

13

SDA I2C bus data I/O

14

IF_AM IF counterHF input

15

IF_FM IF counterVHF input

16

SSTOP IF counterresult output

17*

DOUT1 Digital output 1 (push-pull)

17*

INLOCK Inlockdetectoroutput

18

DOUT2 Digital Output 2 (open collector)

19

HF-REF HF reference pin

20

ADDR I2C bus address pin

21

VDD1 Supply Voltage

22

GND-DIG Digitalground

23

N.C. Not connected

24

FM_IN High frequency input FM

25

AM_IN Highfrequencyinput AM

26

GND-AN Analog ground

27

VDD2 Supply Voltage

28

LP_OUT FilterOPAMP output

* Pin function is selectable by software (see softwarespecification)

TDA7427A

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ELECTRICAL CHARACTERISTICS

(T

amb

=25°C; V

DD1

= 5V; V

DD2

= 10V; f

OSC

= 4MHz; unless other-

wise specified).

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

DD1

Supply Voltage 4.5 5.0 5.5 V

V

DD2

Supply Voltage 9.0 11.0 V

I

DD1 Supply Current no output load 2 4 6 mA

I

DD2

Supply Current PLL locked 1 2 3 mA

I

DD1 STB

Supply Current Standby mode 1

µ

A

RF INPUT (AM_IN, FM_IN)

f

iAM

Input Frequency AM Vi = 100mV

rms

sinusoidal 0.5 64 MHz

f

iFM Input Frequency FM Vi = 100mV

rms

sinusoidal 30 200 MHz

V

iMIN

Min Input Voltage AM 0.5 to 16MHz range sinusoidal 30 mVrms

V

iMAX

Max Input Voltage AM 0.6 to 16MHz range sinusoidal 600 mVrms

V

iMIN Min Input Voltage FM 70 to 120MHz range sinusoidal 30 mVrms

V

iMAX

Max Input Voltage FM 70 to 120MHz range sinusoidal 600 mVrms

Z

in Input Impedance FM input 3 4 5 KΩ

Z

in

Input Impedance AM input 3 4 5 KΩ

IF COUNTER (IF_AM, IF_FM)

f

iAM Input Frequency range AM Vi = 100mV

rms

0.400 11 MHz

f

iAM

Input Frequency range FM Vi = 100mV

rms

10 11 MHz

V

iMIN Min Input Voltage AM IF pin f

in

= 455kHz 30 mVrms

V

iMIN

Min Input Voltage FM IF pin fin= 10.7MHz 30 mVrms

V

iMAX

Max Input Voltage AM IF pin fin= 455kHz 600 mVrms

V

iMAX Max Input Voltage FM IF pin f

in

= 10.7MHz 600 mVrms

Z

in

Input Inpedance FM IF pin 3 4 5 KΩ

Z

in Input Inpedance AM IF pin 3 4 5 KΩ

BUS INTERFACE

T

j

Noise Suppression Time
Constant on SCL, SDA Input

50 ns

f

SCL

SCL Clock Frequency 400 kHz

t

AA SCL Low to SDA Data Valid 300 ns

t

buf

Time the bus must be free for
the new transmission

4.7 µs

t

HD-START

START Condition hold time 4.0

µ

s

t

LOW

Clock Low Period 4.7 µs

t

HIGH

Clock High Period 4.0 µs

t

SU-SDA

Start Condition Setup Time 4.7

µ

s

t

HD-DATA Data Input Hold Time 1 µs

t

SU-DATA

Data Input Setup Time 250 ns

t

R SDA & SCL Rise Time 1 µs

t

F

SDA & SCL Full Time 0.3 µs

t

SU-STOP

Stop Condition Setup Time 4.7

µ

s

t

DH DATA OUT Time 300 ns

TDA7427A

4/21

ELECTRICALCHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

IL

Input Low Voltage 1V

V

IH Input High Voltage 3 V

I

IN

Input Current -5 +5 µA

V

OUT

Output Voltage SDA
acknowledge

IO= 1.6mA 0.15 0.4 V

OSCILLATOR

t

bu

Build Up Time f

out

= 4MHz 100 ms

C

in

Internal Capacitance 20 pF

C

OUT Internal Capacitance f

osc

= 4MHz 20 pF

Z

in

Input Impedance f

osc

= 4MHz 100 KΩ

V

in Input Voltage (for Slave Mode) f

IN

= 4 to 13MHz (Sinus)

capacitance coupling

300 V

DD

mV

pp

fin Max Input frequency (for Slave

Mode)

VIN= 600mVPP(Sinus) 30 MHz

LOOP FILTER

(LP_FM, LP_AM, LP_HC, LP_OUT)

I

IN

Input Leakage Current (*) VIN= GND; PD

out

= Tristate (1) -1 0.1 1 µA

I

IN

Input Leakage Current (*) VIN=V

DD1

;PD

out

= Tristate (1) -1 0.1 1

µ

A

V

OL

Output Voltage Low IIN= -0.2mA 0 0.5 V

V

OH

Output Voltage High I

OUT

= 0.2mA 9.5 10 V

I

OUT Output Current Sink 10 30 mA

I

OUT

Output Current Source Vout = 0.5 to 9.5V 10 30 mA

DOUT1/SSTOP (push-pull outputs)

V

OL Output Voltage Low I

OUT

= -0.1mA 0.1 0.2 V

V

OH

Output Voltage High I

OUT

= 0.1mA V

DD1

*0.2 4.9 V

DOUT2 to 6

(opencollector outputs)

I

OUT

Output leakage Current V

OUT

= 10V -1 0.1 1 mA

V

OL

Output Voltage Low I

OUT

= -1mA 0.2 0.5 V

I

OUT Output Current Sink Vout = 0.5 to 9.5V 3 5 mA

1) PD = Phase Detector
(*) LP_FM and LP_HC pins only

TDA7427A

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GENERAL DESCRIPTION

This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning sys­tems. Only a VCO is required to build a complete
PLL system. For auto search/stopoperationan IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stageconfiguration. The first stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit pro­grammable counter.
For LW and MW application,a 16-bit programma­ble counteris available.
The circuit receivesthe scaling factors for the pro­grammable counters and the values of the refer­ence frequenciesvia a I

2

C bus interface.
The reference frequency is generated by an inter­nal XTAL oscillator followed by the reference di­vider. The device can operate with XTAL oscilla­tor between 4 and 13MHz either in master mode
and in slave mode.

The reference and step frequencies are free se­lectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.

Values of the current sources are programmable
by 6 bitsalso received via the I

2

C bus.

To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the cur­rent valuesof thecharge/pumpgenerator.

IF COUNTER SYSTEM

Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuringcycle times.
The tolerance of the accepted count value is ad­justable, to reach an optimum compromise for
searchspeed and precisionof the evaluation.

For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter toler­ance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-con­version)with 1KHz steps is available.

PLL FREQUENCYSYNTHESIZER
InputAmplifiers

The signals applied on AM and FM inputs are am­plified to get a logic level in order to drive the fre­quencydividers.
The typical input impedance for FM and AM in­puts is 4kΩ.

MSB LSB

FUNCTION SUBAD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PLL CHARGE PUMP

00H LPIN1/2 CURRH B1 B0 A3 A2 A1 A0

PLL COUNTER

01H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PLL COUNTER

02H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

PLL REF COUNTER

03H RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

PLL REF COUNTER

04H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8

PLL LOCK DETECT

05H LDENA INLOCK D3 D2 D1 D0 PM1 PM0

IFC REF COUNTER

06H IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0

IFC REF COUNTER

07H IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8

IFC CONTROL

08H IFENA - - - - EW2 EW1 EW0

IFC CONTROL

09H IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0

OSC ADJUST

0AH - - - OSC4 OSC3 OSC2 OSC1 OSC0

PORT EXTENSION

0BH - - DOUT3 DOUT4 DOUT5 DOUT6 DOUT2 DOUT1

Table 1. Address Organization

TDA7427A

6/21

REGISTER NAME FUNCTION

PC

Programmable counter for VCO frequency

RC

Reference counter PLL

IRC

Reference counter IF

IFCM

IF counter mode selector

EW

Frequency error window IF counter

IFENA

Enable IFRC

CF

Center frequency IF counter

IFS

Sampling time IF counter

PM

Stby, FM, AM, AM swallow mode selector

D

Programmable delay and phase error for lock detector

LPIN1/2

Loop filter input select

PLLSTOP

PLL stop

A

Charge pump high current

B

Charge pump low current

LDENA

Lock detector enable

CURRH

Set current high

OSC

Oscillator adjust

DOUT1

Push pull output 5V

DOUT2....6

Open collector output

INLOCK

Lock detector output

Table 2. Control Register Functions.

OSC IN

REGISTER

R0 ...R15

PREDIVIDER

:R

PD

AM IN

FM IN

REGISTER

PC0 ...PC4
COUNTER

A

PRESCALER

M/M+1

REGISTER
PC5 ... P15

COUNTER

:B

fref

fsyn

D95AU375A

∆ϕ

TO CHARGE

PUMP

Figure 1. FM and AM (SW) operation (swallowmode)

TDA7427A

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