SGS Thomson Microelectronics TDA7427, TDA7427D Datasheet
AM-FM RADIO FREQUENCY SYNTHESIZER
ON-CHIP REFERENCE OSCILLATOR AND
PROGRAMMABLEIF COUNTER
VHF INPUT AND PRECOUNTER FOR FREQUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)
HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORTWAVE BAND)
IN-LOCK DETECTOR FOR SEARCH/STOP
STATIONFUNCTION
STAND-BY MODE FOR LOW POWER CONSUMPTION
HIGH CURRENT SOURCE FOR 0.5ms
LOCK-INTIME
DIGITAL PORT EXTENSION WITH TWO
OUTPUTS FOR FLEXIBILITY IN APPLICATION
FULLY PROGRAMMABLEBYI
DESCRIPTION
The TDA7427 is a PLL frequency synthesizer
2
C BUS
TDA7427
AND IF COUNTER
DIP20
ORDERING NUMBERS:
with an additional IF counting system that performs all the functionsneeded in a complete PLL
radio tuning system for conventional and high
speedRDS tuners. The devicehas dedicatedoutputs for IN-LOCK detectionand Search/Stopstation.
SO20
TDA7427(DIP20)
TDA7427D (SO20)
BLOCK DIAGRAM
16
FM_IN
14
HFREF
17
AM_IN
5
OSCIN
OSCOUT
SCL
SDA
VDD2
VDD1
IF_AM
IF_FM
6
8
9
19
15
10
11
I2C BUS
INTERFACE
OSCILLATOR
SWITCH
AM/FM
REF
14 BIT
PROG
CNT
D95AU418B
PRECOUNTER
:32/33
SWITCH
SWM/DIR
PROG
16 BIT
CNT
TIMER CONTROL
11-21 BIT PROG CNT
5 BIT
SWITCH
SWM/DIR
11 BIT
PROG.
CNT
PROG
CNT
SSTOP
DETECTOR
PHASE
COMP
INLOCK
CHARGE
PUMP
TEST
LOGIC
PORT EXTENSION
712
DOUT3
SWITCH
LP1/LP2
+
POWER
RESET
13
DOUT1/INLOCK
2
LP_HC
3
LP_AM
1
LP_FM
-
ON
VDD1
20
4
18
LPOUT
VREF
GNDan/GNDdig
November 1999
1/21
TDA7427
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD1
V
DD2
P
tot
T
stg
T
amb
PIN CONNECTION
Supply Voltage - 0.3 to + 7 V
Supply Voltage - 0.3 to+ 11 V
Total PowerDissipation 300 mW
Storage Temperature - 55 to + 150
Ambient Temperature -40 to + 85
o
C
o
C
LP_FM
LP_HC
LP_AM
VREF
OSCIN
OSCOUT
DOUT3
SCL
SDA
1
2
3
4
5
6
7
8
9 SSTOP
19
18
17
16
15
14
13
12
LPOUT20
VDD2
GND
AM_IN
FM_IN
VDD1
HFREF
DOUT1/INLOCK
IF_AM 10 IF_FM11
D95AU373B
THERMAL DATA
Symbol Parameter DIP20 SO20 Unit
R
th j-amb
Thermal ResistanceJunction-Ambient max 100 150
o
C/W
2/21
TDA7427
PIN DESCRIPTION
PIN SYMBOL DESCRIPTION INPUT/OUTPUT
1
2
3
4
5
6
7
8
9
10
11
12
13*
13*
14
15
16
17
18
19
20
* Pin function is userdefined bysoftware
LP_FM FilterOPAMPinput, charge pump output (FM mode)
LP_HC
LP_AM FilterOPAMPinput, charge pump output (AM mode)
VREF OPAMPreferencevoltage
OSCIN Oscillator reference clock input
OSCOUT Oscillatoroutput
DOUT3 Opencollectoroutput
SCL I2C busclock input Input
SDA I2C busdata I/O Input/output
IF_AM IF counterinput (AMmode) Analoginput
IF_FM IF counter input (FM mode) Analog input
SSTOP IF counterresultoutput Output
DOUT1 Digital output Push-pulloutput
INLOCK Inlockdetectoroutput Output
HFREF HF reference
VDD1 Positivepowersupply 5V Supply
FM_IN HighfrequencyinputFM Analoginput
AM_IN High frequency input AM Analoginput
GND Analogdigitalground Supply
VDD2 Positivepowersupply 10V Supply
LPOUT Filter input, change pump output
(TDA7427/D)
FilterOPAMPinput, charge pump output (high current
mode)
3/21
TDA7427
ELECTRICAL CHARACTERISTICS
(T
amb
=25°C; V
DD1
= 5V; V
DD2
= 10V; f
OSC
= 4MHz; unless other-
wise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
DD1
V
DD2
I
DD1 Supply Current no output load 2 4 6 mA
I
DD2
I
DD1 STB
RF INPUT (AM_IN, FM_IN)
f
iAM
f
iFM Input Frequency FM Vi = 100mV
V
iMIN
V
iMAX
V
iMIN Min Input Voltage FM 70 to 120MHz range sinusoidal 30 mVrms
V
iMAX
Z
in Input Impedance FM input 3 4 5 KΩ
Z
in
IF COUNTER (IF_AM, IF_FM)
f
iAM Input Frequency range AM Vi = 100mV
f
iAM
V
iMIN Min Input Voltage AM IF pin f
V
iMIN
V
iMAX
V
iMAX Max Input Voltage FM IF pin f
Z
in
Z
in Input Inpedance AM IF pin 3 4 5 KΩ
BUS INTERFACE
T
f
SCL
t
AA SCL Low to SDA Data Valid 300 ns
t
buf
t
HD-START
t
LOW
t
HIGH
t
SU-SDA
t
HD-DATA Data Input Hold Time 1 µs
t
SU-DATA
t
R SDA & SCL Rise Time 1 µs
t
F
t
SU-STOP
t
DH DATA OUT Time 300 ns
Supply Voltage 4.5 5.0 5.5 V
Supply Voltage 9.0 11.0 V
Supply Current PLL locked 1 2 3 mA
Supply Current Standby mode 1
Input Frequency AM Vi = 100mV
sinusoidal 0.5 64 MHz
rms
sinusoidal 30 200 MHz
rms
Min Input Voltage AM 0.5 to 16MHz range sinusoidal 30 mVrms
Max Input Voltage AM 0.6 to 16MHz range sinusoidal 600 mVrms
Max Input Voltage FM 70 to 120MHz range sinusoidal 600 mVrms
Input Impedance AM input 3 4 5 KΩ
0.400 11 MHz
10 11 MHz
Input Frequency range FM Vi = 100mV
= 455kHz 30 mVrms
in
rms
rms
Min Input Voltage FM IF pin fin= 10.7MHz 30 mVrms
Max Input Voltage AM IF pin fin= 455kHz 600 mVrms
= 10.7MHz 600 mVrms
in
Input Inpedance FM IF pin 3 4 5 KΩ
Noise Suppression Time
j
50 ns
Constant on SCL, SDA Input
SCL Clock Frequency 400 kHz
Time the bus must be free for
4.7 µs
the new transmission
START Condition hold time 4.0
Clock Low Period 4.7 µs
Clock High Period 4.0 µs
Start Condition Setup Time 4.7
Data Input Setup Time 250 ns
SDA & SCL Full Time 0.3 µs
Stop Condition Setup Time 4.7
A
µ
s
µ
s
µ
s
µ
4/21
TDA7427
ELECTRICALCHARACTERISTICS
(continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
IL
V
IH Input High Voltage 3 V
I
IN
V
OUT
Input Low Voltage 1V
Input Current -5 +5 µA
Output Voltage SDA
IO= 1.6mA 0.15 0.4 V
acknowledge
OSCILLATOR
t
bu
C
in
C
OUT Internal Capacitance f
Z
in
V
in Input Voltage (for Slave Mode) f
Build Up Time f
Internal Capacitance 20 pF
Input Impedance f
= 4MHz 100 ms
out
= 4MHz 20 pF
osc
= 4MHz 100 KΩ
osc
= 4 to 13MHz (Sinus)
IN
300 V
DD
capacitance coupling
fin Max Input frequency (for Slave
VIN= 600mVPP(Sinus) 30 MHz
Mode)
LOOP FILTER
I
IN
I
IN
V
OL
V
OH
I
OUT Output Current Sink 10 30 mA
I
OUT
(LP_FM, LP_AM, LP_HC, LP_OUT)
Input Leakage Current (*) VIN= GND; PD
Input Leakage Current (*) VIN=V
Output Voltage Low I
Output Voltage High I
Output Current Source V
OUT
OUT
OUT
;PD
DD1
= -0.2mA 0 0.5 V
= 0.2mA 9.5 10 V
= 0.5to 9.5V 10 30 mA
= Tristate (1) -1 0.1 1 µA
out
= Tristate (1) -1 0.1 1
out
DOUT1/SSTOP (push-pull outputs)
V
OL Output Voltage Low I
V
OH
DOUT3
I
OUT
V
OL
I
OUT Output Current Sink V
1) PD = Phase Detector
(*) LP_FM and LP_HC pins only
Output Voltage High I
(open collector output)
Output leakage Current V
Output Voltage Low I
= -0.1mA 0.1 0.2 V
OUT
= 0.1mA V
OUT
= 10V -1 0.1 1 mA
OUT
= -1mA 0.2 0.5 V
OUT
= 0.5to 9.5V 3 5 mA
OUT
*0.2 4.9 V
DD1
mV
µ
pp
A
5/21
TDA7427
GENERAL DESCRIPTION
This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning systems. Only a VCO is required to build a complete
PLL system. For auto search/stopoperationan IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stageconfiguration.Thefirst stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit programmable counter.
For LW and MW application,a 16-bit programmable counteris available.
The circuit receivesthe scaling factors for the programmable counters and the values of the reference frequenciesviaa I
2
C bus interface.
The reference frequency is generated by an internal XTAL oscillator followed by the reference divider. The device can operate with XTAL oscillator between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free selectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bitsalso received via the I
2
C bus.
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the current valuesof thecharge/pumpgenerator.
IF COUNTER SYSTEM
Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuringcycletimes.
The tolerance of the accepted count value is adjustable, to reach an optimum compromise for
searchspeed and precisionof the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter tolerance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-conversion)with 1KHz steps is available.
PLL FREQUENCYSYNTHESIZER
InputAmplifiers
The signals applied on AM and FM inputs are amplified to get a logic level in order to drive the frequencydividers.
The typical input impedance for FM and AM inputs is 4kΩ.
Table 1. Address Organization
MSB LSB
FUNCTION SUBAD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PLL CHARGE PUMP
PLL COUNTER
PLL COUNTER
PLL REF COUNTER
PLL REF COUNTER
PLL LOCK DETECT
IFC REF COUNTER
IFC REF COUNTER
IFC CONTROL
IFC CONTROL
OSC ADJUST
PORT EXTENSION
00H LPIN1/2 CURRH B1 B0 A3 A2 A1 A0
01H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
02H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
03H RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
04H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8
05H LDENA INLOCK D3 D2 D1 D0 PM1 PM0
06H IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0
07H IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8
08H IFENA - - - - EW2 EW1 EW0
09H IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0
0AH - - - OSC4 OSC3 OSC2 OSC1 OSC0
0BH - - - - - DOUT3 - DOUT1
6/21
Figure 1. FM and AM (SW) operation (swallowmode)
REGISTER
OSC IN
AM IN
R0 ...R15
PREDIVIDER
:R
REGISTER
PC0 ...PC4
COUNTER
A
fref
fsyn
REGISTER
PC5 ... P15
PD
TDA7427
∆ϕ
TO CHARGE
PUMP
PRESCALER
M/M+1
FM IN
Table 2. Control Register Functions.
REGISTER NAME FUNCTION
PC
RC
IRC
IFCM
EW
IFENA
CF
IFS
PM
D
LPIN1/2
PLLSTOP
A
B
LDENA
CURRH
OSC
DOUT1
DOUT3
INLOCK
Programmable counter for VCO frequency
Reference counter PLL
Reference counter IF
IF counter mode selector
Frequency error window IF counter
Enable IFRC
Center frequency IF counter
Sampling time IF counter
Stby, FM, AM, AM swallow mode selector
Programmable delay and phase error for lock detector
Loop filter input select
PLL stop
Charge pump high current
Charge pump low current
Lock detector enable
Set current high
Oscillator adjust
Push pull output 5V
Open collector output
Lock detector output
COUNTER
:B
D95AU375A
7/21
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