TWO INDEPENDENT INPUT ATTENUATORS
IN 0.31dB FORBALANCEFACILITY
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
SO20
TDA7346
DIP20
DESCRIPTION
The TDA7346 reproduces surround sound by using phase shifters and a signal matrix. Control of
all the functionsis accomplishedby serial bus.
The AC signal setting is obtained by resistor net-
BLOCK DIAGRAM
5.6nF680nF
LP1
HP1HP2
100nF
100nF
L
-in
100K
R
-in
100K
RLP1 RHP1
+
R5
-
+
R6
SUPPLY
+
+
L-R
SIM
MOVIE/
MUSIC
ORDERING NUMBER: TDA7346 (DIP20)
TDA7346D (SO20)
works and switches combined with operational
amplifiers.
100nF
PS1
RPS1
PS1
90Hz
LPF
9KHz
4.7nF
PS2
RPS2RPS3RPS4
PS2
4KHz
MUSIC
OFF
EFFECT
CONTROL
22nF
PS3
PS3
400Hz
PHASESHIFTER
MOVIE/SIM
22nF
PS4
PS4
400Hz
MIXING
AMP
MIXING
AMP
I2C
BUS
DECODER
LATCHES
L
out
SCL
SDA
DIG GND
ADDR
REAR
R
out
February 1997
VSAGND CREFLP
C5
22µF
1.2nF
D94AU122A
1/14
TDA7346
ABSOLUTE MAXIMUMRATINGS
SymbolParameterValueUnit
V
T
T
PIN CONNECTION
Operating Supply Voltage10.5V
S
Operating Ambient Temperature-40 to 85°C
amb
Storage Temperature Range-55 to +150°C
stg
PS1
V
CREF
L
-in
LP
REAR
L
out
SDA
SCL
1
2
S
3
4
5
6
7
8
9ADDR
19
18
17
16
15
14
13
12
PS220
LP1
HP1
HP2
R
-in
PS3
PS4
R
out
DIG GND10AGND11
D94AU128
THERMAL DATA
SymbolDescriptionValueUnit
R
thj-pins
Thermal Resistance Junction-pinsMax.85°C/W
QUICK REFERENCEDATA
SymbolParameterMin.Typ.Max.Unit
V
V
CL
THDTotal Harmonic Distortion V = 1Vrms f = 1KHz0.020.1%
S/NSignal to Noise Ratio V
S
2/14
Supply Voltage7910.2V
S
Max. input signal handling2Vrms
out = 1Vrms (mode = OFF)106dB
Channel Separation f= 1KHz70dB
C
TEST CIRCUIT
TDA7346
L
out
SCL
SDA
680nF
HP1
18
REAR
6798
C16
17
L
-in
4
0.1µF
C17
V
HP2
S
10µFC1
2
TDA7346
100nF
C2
PS3
22nF
15
C4
PS4
22nF
C5
ELECTRICALCHARACTERISTICS
R
= 600Ω, all controls flat (G = 0),EffectCtrl = -6dB, MODE = OFF; f = 1KHz
G
14
R
out
AGNDDIG GND
(refer to the test circuitT
12101113
ADDR
=25°C, VS= 9V, RL= 10KΩ,
amb
unless otherwisespecified)
LP
5
R
16
LP1
19
PS1
1
PS2
20
CREF
3
D93AU040C
1.2nF
C6
0.1µF
-in
C7
5.6nF
C15
100nF
C14
4.7nF
C13
22µF
C3
SymbolParameterTest ConditionMin.Typ.Max.Unit
SUPPLY
V
S
I
S
SVRRipple RejectionL
Supply Voltage7910.2V
Supply Current10mA
CH/RCH out
, Mode = OFF6080dB
INPUT STAGE
C
RANGE
A
A
A
V
R
II
V
CL
VMIN
VMAX
STEP
DC
Input Resistance100K
Clipping LevelTHD = 0.3%; Lin orRin22.5Vrms
THD = 0.3%; Rin + Lin (2)3.0Vrms
Control Range20dB
Min. Attenuation-101dB
Max. Attenuation20dB
Step Resolution0.31dB
DC Stepsadjacent att.step0mV
EFFECT CONTROL
C
RANGE
S
STEP
Control Range- 21- 6dB
Step Resolution1dB
Ω
3/14
TDA7346
ELECTRICAL CHARACTERISTICS
(continued)
SURROUNDSOUND MATRIX
SymbolParameterTest ConditionMin.Typ.Max.Unit
G
D
OFF
GOFF
In-phase Gain (OFF)Mode OFF, Input signal of
LR In-phase Gain Difference
(OFF)
G
MOV1
In-phase Gain (Movie 1)
RPS1, RPS2, RPS3, RPS4 =
POR Preset
G
MOV2
In-phase Gain (Movie 2)
RPS1, RPS2, RPS3, RPS4 =
POR Preset
D
GMOV
LR In-phase Gain Difference
(Movie)
G
MUS1
In-phase Gain (Music 1)
RPS1 = POR PRESET
G
MUS2
In-phase Gain (Music 2)
RPS1 = POR PRESET
D
GMUS
LR In-phase Gain Difference
(Music)
L
MON1
Simulated L Output 1
RPS1, RPS2, RPS3, RPS4 =
POR Preset
L
MON2
Simulated L Output 2
RPS1, RPS2, RPS3, RPS4 =
POR Preset
L
MON3
Simulated L Output 3
RPS1, RPS2, RPS3, RPS4 =
POR Preset
R
MON1
Simulated R Output 1
RPS1, RPS2, RPS3, RPS4 =
POR Preset
R
MON2
Simulated R Output 2
RPS1, RPS2, RPS3, RPS4 =
POR Preset
R
MON3
Simulated R Output 3
RPS1, RPS2, RPS3, RPS4 =
POR Preset
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
Rin→ R
out,Lin
→ L
p-p
out
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
Rin→ R
out,Lin
→ L
p-p
out
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
R
(R
in
→
out
)–(L
→
in
p-p
L
)
out
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
R
(R
in
→
out
)–(L
→
in
p-p
L
)
out
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
Rin→ R
out,Lin
→ L
p-p
out
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
(Rin→ R
)–(Lin→ L
out
out
p-p
)
SimulatedMode,EffectCtrl=-6dB
Input signal of 250Hz,
1.4 V
p-p,Rin
and Lin→ L
out
SimulatedMode,EffectCtrl=-6dB
Input signal of 1kHz,
1.4 V
p-p,Rin
and L
L
→
in
out
SimulatedMode, EffectCtrl= 6dB
Input signal of 3.6kHz,
1.4 V
p-p,Rin
and L
L
→
in
out
SimulatedMode,EffectCtrl=-6dB
Input signal of 250Hz,
1.4 V
p-p,Rin
and L
R
→
in
out
SimulatedMode,EffectCtrl=-6dB
Input signal of 1kHz,
1.4 V
p-p,Rin
and Lin→R
out
SimulatedMode,EffectCtrl=-6dB
Input signal of 3.6kHz,
1.4 V
p-p,Rin
and Lin→ R
out
-1.501.5dB
-1.501.5dB
7dB
8dB
0dB
6dB
7.5dB
0dB
4.5dB
– 4.0dB
7.0dB
– 4.5dB
3.8dB
–20dB
Ω
Ω
4/14
TDA7346
ELECTRICAL CHARACTERISTICS
(continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
AUDIO OUTPUTS
V
OCL
R
OUT
V
OUT
Clipping Leveld = 0.3%22.5Vrms
Output resistance100200300Ω
DC Voltage Level3.53.84.1V
GENERAL
N
O(OFF)
N
O(MOV)
N
O(MUS)
N
O(MON)
dDistorsionAv = 0 ; V
S
C
Output Noise (OFF)BW= 20Hz to 20KHz
R
out
and L
measurement
out
Output Noise (Movie)Mode =Movie ,
B
= 20Hz to 20KHz
W
R
out
andL
measurement
out
Output Noise (Music)Mode = Music ,
B
= 20Hz to 20KHz,
W
R
out
andL
measurement
out
Output Noise (Simulated)Mode = Simulated,
B
= 20Hz to 20KHz
W
R
out
andL
measurement
out
= 1Vrms0.020.1%
in
8µVrms
30
30µVrms
30µVrms
Channel Separation70dB
BUS INPUTS
V
IL
V
IH
I
IN
V
O
Note:
(1) Bassand Treble response: The center frequency and the resonance quality can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network.
(2) Thepeak voltage of thetwo input signals must be less then
(Lin + Rin)
Input Low Voltage1V
Input High Voltage3V
Input Current-5+5
Output Voltage SDA
IO= 1.6mA0.40.8V
Acknowledge
V
S
:
2
peak
• A
V
S
<
Vin
2
Vrms
µ
µ
A
5/14
TDA7346
2
C BUS INTERFACE
I
Data transmission from microprocessor to the
TDA7346 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supplyvoltage mustbe connected).
Data Validity
As shown in fig. 3, the data on the SDAline must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDAline while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an ac-
Figure 3:
Data Validityon theI
2
CBUS
knowledgebit. The MSBis transferredfirst.
Acknowledge
The master (µP) putsa resistiveHIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineis stableLOWduringthisclockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwisethe SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
TransmissionwithoutAcknowledge
Avoiding to detect the acknowledge of the audioprocessor,the µP can usea simplertransmission:
simply it waits one clock without checking the
slave acknowledging,and sends the new data.
This approach of course is less protected from
misworking and decreasesthe noise immunity.
Figure 4:
TimingDiagram of I
2
Figure 5: Acknowledgeon theI
6/14
CBUS
2
CBUS
TDA7346
SOFTWARESPECIFICATION
InterfaceProtocol
The interfaceprotocol comprises:
A startcondition (s)
A chip address byte, containing the TDA7346
TDA7346 ADDRESS
MSB
S110111A0
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
first byte
LSBMSBLSBMSBLSB
ACK
SOFTWARESPECIFICATION
Chip address
1
MSB
10111A0
address(the 8th bit of the byte must be 0). The
TDA7346must always acknowledgeat the end
of each transmitted byte.
A sequenceof data (N bytes + achnowledge).
A stopcondition (P)
DATA
Data Transferred (N-bytes + Acknowledge)
LSB
ACK
ACHIP ADDRESS
0DC (HEX)
1DE (HEX)
DATA
ACK
P
A = Logic level on pin ADDR
A = 1 if ADDR pin = open
A = 0 if ADDR pin = connected to ground
SoftwareSpecification
MSBLSBSUBADDRESS
00A5A4A3A2A1A0INPUT ATTENUATION R
01A5A4A3A2A1A0INPUT ATTENUATION L
1M1M0SURROUND MODES
100SIMULATED MODE
101MUSIC MODE
110MOVIE MODE
11111111OFFMODE
1M1M01B3B2B1B0EFFECT CONTROL
1M1M0000C1C0PHASE SHIFTER 4 CONTROL
1M1M0001C1C0PHASE SHIFTER 3 CONTROL
1M1M0010D1D0PHASE SHIFTER 2 CONTROL
1M1M0011E1E0PHASE SHIFTER 1 CONTROL
7/14
TDA7346
INPUT ATTENUATION
MSBLSB0.3125 dB STEPS
I A5A4A3A2A1A0
00000
0001-0.3125
0010-0.625
0011-0.9375
0100-1.25
0101-1.5625
0110-1.875
0111-2.1875
INPUT ATTENUATION-19.375dB
EFFECT CONTROL-20dB
SURROUND MODEOFF MODE
PHASE SHIFTER 1 RESISTOR VALUE17.950 K
PHASE SHIFTER 2 RESISTOR VALUE8.465 K
PHASE SHIFTER 3, 4 RESISTOR VALUE18.050 K
Ω
Ω
Ω
9/14
TDA7346
PIN:
HP1
LP1
HP2
PIN: Lin,R
PIN:
HP2
V
, R
V
S
20µA
5.5K
60K
D94AU199
, REAR
OUT
S
5.5K
20µA
V
S
10K
60K
GND
D94AU198
in
V
S
HP1
PIN: L
OUT
20µA
PIN:
SCL, SDA
Vref
100K
D94AU123
20µA
D94AU205
PIN:
ADDR
100Ω
V
S
100K
D94AU204
20µA
D94AU212
10/14
TDA7346
PIN:
PIN: C
LP
REF
V
S
D94AU206
V
S
10K
20µA
PIN:
PS3, PS2
PIN: PS2
PS3A
PS4A
V
S
20µA
18.050K
D94AU124
V
S
20µA
PIN:
PS1
PS1A
20K
20K
V
S
20µA
D94AU208
20µA
PIN:
LP1
PS2A
8.465K
D94AU125
V
S
20µA
17.95K
10K
HP1
D94AU126
D94AU211
11/14
TDA7346
SO20 PACKAGEMECHANICAL DATA
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
A2.650.104
a10.10.30.0040.012
a22.450.096
b0.350.490.0140.019
b10.230.320.0090.013
C0.50.020
c145°(typ.)
D12.613.00.4960.512
E1010.650.3940.419
e1.270.050
e311.430.450
F7.47.60.2910.299
L0.51.270.0200.050
M0.750.030
mminch
S8
(max.)
°
12/14
DIP20 PACKAGE MECHANICAL DATA
TDA7346
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
I3.930.155
L3.30.130
mminch
Z1.340.053
13/14
TDA7346
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patentrights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.