SGS Thomson Microelectronics TDA7330B, TDA7330BD Datasheet
SINGLE CHIP RDS DEMODULATOR+ FILTER
HIGH PERFORMANCE, 57KHz BANDPASS
FILTER (8th ORDER)
FILTER ADJUSTMENTFREE AND WITHOUT
EXTERNALCOMPONENTS
PURELY DIGITAL RDS DEMODULATION
WITHOUTEXTERNALCOMPONENTS
ARI (SK INDICATION) AND RDS SIGNAL
QUALITYOUTPUT
4.332MHzCRYSTAL OSCILLATOR
(8.664MHzOPTIONAL)
LOW NOISE MIXED BIPOLAR/CMOS TECHNOLOGY
DESCRIPTION
The TDA7330B is a RDS demodulator. It recovers the additional inaudible RDS information
which is transmitted by FM radio broadcasting
stations.
The output data signal (RDDA) and clock signal
(RDCL) can be further processed by a suitable
RDS decoder (microprocessor).
The device operates in accordancewith the EBU
(European BroadcastingUnion) specifications.
The IC includes a 2nd order antialiasing input fil-
TDA7330B
DIP20 SO20
ORDERING NUMBERS:
TDA7330B TDA7330BD
ter, a 57KHz switched capacitor band pass filter,
a smoothing filter and cross detector, a bit rate
clock recovery circuit, a 57KHz PLL, BI-PHASE
PSK decoder, differential decoding circuit, ARI indication and RDS signalquality output.
BLOCK DIAGRAM
November 1999
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TDA7330B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
T
op
T
stg
THERMAL DATA
Symbol Description DIP20 SO20 Unit
R
th j-case
PIN CONNECTION(Topview)
Supply Voltage 7 V
Operating Temperature Range -40 to 85
Storage Temperature -40 to 150 °C
Thermal Resistance Junction-case Typ. 100 200 °C/W
C
°
PIN FUNCTION
Nr. Name Description
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10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
MUXIN
V
ref
COMP
FIL OUT
GND
T1
T3
T4
OSC OUT
OSC IN
T57
RDCL
RDDA
QUAL
ARI
V
CC
T2
FSEL
TM
POR
RDS input signal.
Reference voltage
Not inverting comparator input (smoothing filter)
Filter Output
Ground
Testing output pin (not to be used)
Testing output pin (not to be used)
Testing output pin (not to be used)
Oscillator output
Oscillator Input
Testing output pin: 57KHz clock output
RDS clock output (1187.5Hz)
RDS data output
Output for signal quality indication (High = good)
Output for ARI indication (High when RDS + ARIsignals are present)
(High when onlyARI is present)
(Low when only RDS is present)
(indefined when no signal is present)
Supply Voltage
Testing output pin (not to be used)
Frequency selector pin: open = 4.332MHz, closed to V
Test mode pin (open = normal RUN)
(closedto V
= Test mode)
CC
Reset Input for testing (active high)
= 8.664MHz
CC
TDA7330B
ELECTRICALCHARACTERISTICS (VCC= 5V, Tamb = 25°C; Rg = 600Ω; fosc = 4.332MHz;
V
= 20mVrmsunless otherwisespecified)
IN
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
V
I
R
POR
POR
CC
S
Supply Voltage 4.5 5 5.5 V
Supply Current 9 mA
POR Pull Down Resistor pin 20 40 KΩ
POR Threshold 2.5 V
ON
FILTER(measuredan pin 4 FILOUT)
F
BW 3dB Bandwidth 2.5 3 3.5 KHz
G Gain f = 57KHz 18 20 22 dB
A Attenuation ∆f = +4KHz
Ph Phase nonlinearity A (see note1)
∆
R
S/N Signal to Noise Ratio V
V
R
Center Frequency 56.5 57 57.5 KHz
C
f = 38KHz; V
f = 67KHz; V
= 500mVrms
i
= 250mVrms
i
18
50
35
22
80
50
0.5
B (see note1)
C (see note1)
Input Impedance 100 160 200 KΩ
i
= 3mVrms 30 40 dB
i
Maximum Input Signal Capability f= 19KHz;T3 < –40dB(seenote2)
i
1
2
f = 57KHz (RDS + ARI)
Load Impedance Pin 4 100 KΩ
L
5
7.5
10
1
50
CROSSDETECTOR
RA Resistance pin 3-4 15 21 28 KΩ
OSCILLATOR
dB
dB
dB
DEG
DEG
DEG
Vrms
mVrms
F
OSC
Oscillator Frequency F
= Open (*)
SEL
F
= Closed to VCC(**)
SEL
4.332
8.664
VCLL Clock Input level LOW (pin10) 1 V
VCLH Clock Input Level HIGH (pin 10) 4 V
Output Amplitude (pin 9) 4.5 V
(*) FSEL pin has an internal 40KΩ pull down resistor A 4.332MHz QUARTZ must be used (**)A 8.664MHz QUARTZ must be used.
DEMODULATOR
f
∆
S
RDS
S
ARI
T
lock
V
OH
V
OL
f
RDS
t
D
Note(1):
The phase non linearity isdefined as: ∆Ph = | -2φf2 + φf1 + φf3 |
where φfx is the input-output phase difference at the frequency fx (x = 1,2,3)
Max Oscillator Deviation F
O
= Open + 1.2 KHz
SEL
RDS Detection Sensitivity 1 mVrms
ARI Detection Sensitivity 3 mVrms
RDS Lockup Time 100 ms
Output HIGH Voltage IL= 0.5mA; pins 12,13, 14, 15 4 V
Output LOW Voltage IL= 0.5mA; pins 12, 13, 14, 15 1 V
Data Rate for RDS RDCL pin 1187.5 Hz
RDDA Transition versus RDCL (see figure 2) 4.3 µsec
MHz
MHz
PP
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