AM-FM RADIO FREQUENCY SYNTHESIZER
FM INPUT AND PRECOUNTER FOR UP TO
140MHz
AM INPUTFOR UP TO 40MHz
6-BIT SWALLOW COUNTER, 8-BIT PRO-
GRAMMABLE COUNTER FOR FM ANDSW
14-BIT PROGRAMMABLE COUNTER FOR
LWAND MW
THREEWIRES 8-BITSERIALINTERFACE
ON-CHIP REFERENCE OSCILLATOR AND
COUNTER
PROGRAMMABLE SCANNING STEPS FOR
AM ANDFM
DIGITALPHASEDETECTOR AND LOOP FIL-
TER
TWO SEPARATE FREE PROGRAMMABLE
FILTERAPPLICATIONS AVAILABLE
TUNINGVOLTAGE OUTPUT0.5 TO 9.5V
PROGRAMMABLE CURRENT SOURCES TO
SET THE LOOP GAIN
ON-CHIPPOWER ON RESET
STANDBYMODE
TDA7326
DIP16
SO16W
ORDERING NUMBERS: TDA7326 (DIP16)
TDA7326D (SO16W)
DESCRIPTION
The TDA7326 is a PLL frequency synthesizer in
CMOStechnology that performs all the functionof
a PLL radio tuning system for FM and AM (LW,
MW, SW)
BLOCKDIAGRAM
July 1994
1/16
TDA7326
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD1-VSS
V
DD2-VSS
V
IN
V
OUT
I
IN
I
OUT
T
stg
T
A
PIN CONNECTION
Supply Voltage - 0.3 to + 7 V
Supply Voltage - 0.3 to + 12 V
Input Voltage VSS - 0.3 to VDD+ 0.3 V
Output Voltage VSS - 0.3 to VDD+ 0.3 V
Input Current - 10 to + 10 mA
Output Current - 10 to + 10 mA
Storage Temperature - 55 to + 125
Ambient Temperature -40 to + 85
o
C
o
C
THERMALDATA
Symbol Parameter DIP 16 SO 16L Unit
th j-amb Thermal Resistance Junction-ambient 100 200 °C/W
R
Figure 1:Input Sensitivity
2/16
TDA7326
ELECTRICAL CHARACTERISTICS (Tamb =25°C;VDD1 = 5V; VDD2 =9VfOSC = 4MHz; RISET =68KΩ;
unlessotherwisespecified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
DD1 Supply Voltage 4.5 5.0 5.5 V
V
DD2 Supply Voltage 9.0 10.0 V
V
DD1 FM Supply Current no output load, FM mode,
I
f
in = 100MHz
DD1 AM Supply Current no output load, AM mode,
I
fin= 1MHz
I
DD1 STB Supply Current Standby mode 3 20 µA
DD2 Supply Current 0.5 2 3 mA
I
REF Voltage at pin 3 3.0 3.5 4.0 V
V
iSET Voltage at pin 2 RiSET = 68KΩ 7.0 8.0 9.0 V
V
RF INPUT (AMIN FMIN)
fiAM Input Frequency AM DirectMode, Vin= 50mV 0.5 20 MHz
Swallow Mode, V
iFM InputFrequency FM Sinus, V
f
iAM Input Voltage AM Direct Mode
V
= 50mV 30 140 MHz
in
= 50mV 16 40 MHz
in
0.6 to 16MHz (Sinus)
Swallow Mode
16 to 40MHz (Sinus)
V
iFM Input Voltage FM 70 to 120MHz (Sinus) 30 600 mVrms
in Input Impedance FM fin= 120MHz 200 Ω
Z
in Input Impedance AM fin= 12MHz 1400 Ω
Z
OSCILLATOR
10 18 25 mA
3 5 10 mA
40 600 mVrms
40 600 mVrms
fOSC Oscillator Frequency 4 MHz
bu Built Up Time Euro-Quartz ITT 100 ms
t
in Internal Capacitance 9 pF
C
OUT Internal Capacitance 9 pF
C
in Input Impedance 4 15 KΩ
Z
in Input Voltage 0.5 V
V
DD1
PLL CHARACTERISTICS
fstep Step Width AM 1/2.5 KHz
step Step Width FM 12.5/25 KHz
f
ref Ref Frequency AM 1/2.5 KHz
f
ref Ref Frequency FM 12.5/25 KHz
f
LOOP FILTER INPUT (LPIN1,LPIN2 =PIN 15,16)
-Iin Input Leakage Current VIN= VSS; Phase Detector
Output = Tristate
I
in Input Leakage Current VIN = VDD; Phase Detector
Output = Tristate
-1 -0.1 µA
0.1 +1 µA
Vpp
3/16
TDA7326
ELECTRICALCHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LP
Symbol Parameter Test Condition Min. Typ. Max. Unit
OL Output Voltage Low ILOAD = 0.2mA VDD2;= 10V 0.5 0.8 V
v
OH Output Voltage High -ILOAD = 0.2mA VDD2; = 10V 9 9.5 V
V
CHARGE PUMP CURRENT GENERATION (LPIN1,LPIN2 = PIN 15,16)
Isi Sink Current LPIN1,2 CURR1 = 0, CURR2 = 0 2 5 7 µA
so Source CurrentLPIN1,2 CURR1 = 0, CURR2 = 0 2 5 7 µA
-I
DOUT1 OPENDRAIN OUTPUT(PIN9)
vOL Output Voltage Low ILOAD = 1mA 0.2 0.5 V
BUS INTERFACE
-IIL Input Leakage Current VIN = VSS -1 0.1 1 µA
IH Input Leakage Current VIN = VSS -1 0.1 1 µA
I
IH Input Voltage High Leading edge 3.4 4.0 V
v
IL Input Voltage Low Leadingedge 1.0 1.6 V
V
BUS INTERFACE, WAITINGTIME (see fig.5) The Data is Acquiredat the High → Low ClockTransition
OUT = PIN 14)
CURR1 = 0, CURR2 = 1 120 200 280 µA
CURR1 = 1, CURR2 = 1 180 300 420 µA
CURR1 = 1, CURR2 = 0 370 500 630 µA
CURR1 = 0, CURR2 = 1 120 200 280 µA
CURR1 = 1, CURR2 = 1 180 300 420 µA
CURR1 = 1, CURR2 = 0 370 500 630 µA
t1 CLK Low to DLEN L → H 0.2 µs
3 DATA Transition to CLK H → L 0.1 µs
t
5 CLK H → L to DATA Transition 0.4 µs
t
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
tr1 Release Time Between 2 bytes,
except byte 4
t
r2 Release Time after the
transmission of byte 4
FM mode 180 µs
AM mode 2 ms
5 µs
BUS INTERFACE, SETUPTIME (see fig.5)
t2 DLEN High to CLK L → H 0.1 µs
BUS INTERFACE, HOLD TIME (see fig.5)
t4 DATA Transition to CKL L → H0µs
6CLK H → L toDLEN H → L 0.4 µs
t
CLK CLK Frequency 500 KHz
f
Duty Cycle 50 %
pl Clock Pulse Low 1 µs
t
ph Clock Pulse High 1 µs
t
4/16
TDA7326
2.0 GENERAL DESCRIPTION
This circuit contains a frequency synthesizer and
a loop filter for an FM and AM radio tuning system. Only a V
is required to build a complete
CO
PLLsystem.
For FM and SW application, the counter works in
a twostages configuration.
The first stage is a swallow counter with a four
modulus(:32/33/64/65)precounter.
The loopgain can be set for different conditions.
After a power on reset, all registers are reset to
zero andthe standbymode is activated.
In standby mode, oscillator, reference counter,
AM input and FM input are stopped. The power
consumption is reducedto a minimum.
3.0 DETAILED DESCRIPTION OF THE PLL
FREQUENCYSYNTHESIZER
The second stage is an 8-bit programmable
counter.
For LW and MWapplication, a 14-bit programmable counteris available.
Thecircuit receives the scaling factors for the pro-
3.1 INPUT AMPLIFIERS
The signals applied on AM and FM input are amplified to get a logic level in order to drive the fre-
quency dividers.
grammable counters and the values of the reference frequencies via a three line serial bus interface.
The reference frequencyis generatedby a 4MHz
XTALoscillatorfollowed bythe reference divider.
An external oscillator (f = 4MHz) can be used instead of the internal one; it must be connectedto
OSCIN (pin 7).
3.1.1 Input Impedance
The typical input impedance: for the FM input
is 200Ω and forAM input is 1.4kΩ.
3.1.2 Input sensitivity
(seeFigures 1a and 1b).
The reference step-frequency is 1 or 2.5kHz for
AM. For FM mode a step frequency of 12.5 and
25kHzcan be selected.
The circuit checks the format of the received data
words.
Valid data in the interface shift register are stored
automatically in buffer registers at the end of
transmission.
The output signals of the phase detector are
switching the programmablecurrent sources.
Their currents are integrated in the loop filter to a
DC voltage.The values of the current sources are
programmable by two bits also received via the
serialbus.
The loop filter amplifier is supplied by a separate
positive power supply, to minimize the noise in-
3.2 DATAAND CONTROLREGISTER
3.2.1 Register Location
The data registers (bit2...bit7) for the control
register and the data registers PC7...PC0,
SC5...SC0 for the counters are organized in
fourwords, identified by two addressbits (bit 7
and bit 6), bit 7 is the first bit to be sentby the
controller, bit0 is the last one. The order and
the number of the bytes to be transmitted is
free of choice. The modification of the
PC7...PC0 registers is valid for the internal
counters only after transmission of byte 4
(SC5...SC0).
duced by the digitalpart of thesystem.
3.2.2 CONTROL ANDSTATUS REGISTERS
RegisterConfiguration
ADDRESS BITS DATA BITS
BYTE MSB-BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0
Function adr 0 adr 1 data 0 data 1 data 2 data 3 data 4 data 5
byte1 0 0 test 0 test 1 test 2 SOUT CURR2 f
byte2 0 1 PC7 PC6 LPF1/2 CURR 1 SWM/DIR AM/FM
byte3 1 0 PC5 PC4 PC3 PC2 PC1 PC0
byte4 1 1 SC5 SC4 SC3 SC2 SC1 SC0
REF
REGISTER NAME FUNCTION
SWM/DIR Swallow direct-mode switch 1 = SWM, 0 = DIR
AM/FM AM - FM band switch 1=AM, 0 = FM
REF Selection of reference frequency (see table 3.4)
f
CURR1 Current select of change pump
CURR2 Current select of change pump
LPF1/LPF2 Loop filter input select1= I
SOUT Switch output condition 1=output high,0 = output low
PF1,0=IPF2
5/16
TDA7326
3.3 DIVIDER FROM VCOFREQUENCYTO
REFERENCEFREQUENCY
This divider provides a low frequency f
SYN
which
is phase compared with the reference frequency
f
.
REF
3.4 OPERATINGMODE
Four operating modes are available:
- FM mode,
- AMswallow mode,
- AMdirect mode,
- Standbymode
They are user programmable with the SWR/DIR
and AM/FM bits in the byte 2.
Standby mode: all functions are stopped. This allowslow current consumptionwithout lost of informationin all register, it is activatedby forcing bit 0
(AM/FM)and bit 1 (SWM/DIR)both at zero value.
MODE SECTION SWM/DIR AM/FM
STAND-BY 0 0
FM 1 0
AM SWALLOW 0 1
AM DIRECT 1 1
3.4.1 FM and AM (SW) Operation (Swallow
Mode)
The FM or AM signal is applied to a four
modulus: 32/33/64/65 high speed prescaler,
which is controlled by a 6 bit divider ’A’.This
divider is controlled by the 6 bit SC register.
In parallel the output of the prescaler is connected to a 8 bit divider ’B’. This divider is
controlled by the 8 bit PC register. For FM
mode with 25kHz reference frequency operation, the divider A is a 5 bit divider. The high
speed prescaler is working in : 32/33 dividing
mode. Bit 6 of the SC register has to be kept
to ”0”.
Dividing range calculation :
For FM mode with 12.5kHz reference frequencyand SWswallow modeoperation :
=[65⋅A1+(B1+1 -A1)⋅64 ]. f
f
VCO
f
= (64⋅ B1+A1+64) ⋅ f
VCO
REF
REF
or
Important : For correctoperation B ≥ 64 and B
≥ A.
At FM mode with25kHz referencefrequency :
=[33⋅A2+(B2+1-A2)⋅32 ]⋅ f
f
VCO
f
= (32 ⋅ B2+A2+ 32) ⋅ f
VCO
REF
REF
Important:For correct operation B ≥ 32 and B
≥ A.
A and B are variable values of the dividers.
To keep the actual tuning frequency after a
modification of the reference frequency, the
values of the dividers have to be modified in
the followingway.
Switching from 25kHz to 12.5kHz reference
frequency: B
1=B2,A1=A2
⋅2
Switching from 12.5kHz to 25kHz reference
frequency:
2=B1
,A2=
2
B
A
for odd values A
1
and A
.
1
(A
+ 1)
1
=
2
2
The AM signal is directly applied to the 14 bit
static divider ’C’. This divider is controlled by
both SC and PC registers.
Dividing range:
f
=(C+1)⋅f
VCO
REF
Figure2: FM and AM (SW) operation(swallow mode)
OSC IN
AM IN
FM IN
6/16
PREDIVIDER
R
REGISTER
SC5 .. SC0
COUNTER
A
PREDIVIDER
M/M+1
fref
fsyn
PD
REGISTER
PC7 .. PC0
COUNTER
B
D94AU101
Figure3: AM directmode operationfor SW, MWand LW
TDA7326
OSC IN
AM IN
FM IN
3.4 REFERENCEFREQUENCY GENERATOR
The crystal oscillator clock is divided by the
referencefrequency divider to provide the reference frequency to the phase comparator.
Reference frequency divider range is selectable by theprogrammingbit ’f
REF
’.
Available reference frequency are shown in
followingtable.
Figure4: Phase comparator
PREDIVIDER
R
MSB
REGISTER
PC7 .. PC0
COUNTER : C
TABLE3.4
fref
PD
fsyn
REGISTER
SC5 .. SC0
D94AU102
AM/FM f
REF
f
REF
(kHz)
0 0 12.5
0125
101
1 1 2.5
7/16
TDA7326
Figure5
D94AU103
8/16
byte 1 - 3 byte 4byte 1 - 3 byte 1 - 4
DLEN
R1
t
tpl
t5
t4
tph
t2
t1
CLK
t3
DATA
TDA7326
3.5 THREE STATEPHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
f
SYN
and f
. This phase error signal drives the
REF
chargepump current generator
3.6 CHARGE PUMP CURRENT GENERATOR
This system generates signed pulses of current.
Duration and polarity of those pulses are determined by the phase error signal. The absolute
current values are programmable by ’CURR1’
and ’CURR2’ bits and controlled by an external
resistorR
connectedto Pin2 and GND.
ISET
3.7 LOW NOISECMOS OP-AMP
A low noise Op-Amp is available on chip. The
positive input of this Op-Amp is connected to an
internal voltage divider and to Pin 3 ’V
REF
’. The
negative input is connected to the charge pump
output. In cooperation with this internal amplifier
and external components, an active filter can be
provided. To increase the flexibility in application
the negative input can be switched to two input
pins (Pins 15 and 16). This switch is controlled by
’LPF’ register with ’LPF’ low Pin 15 is active and
’LPF’ high Pin 16 is active. This feature allows
two separate active filters with different performance.
3.8 TESTFUNCTION
The test pin (Test Out) is used only for testing:it
has no use in real applications. The three bits
test0, test1, test2, of the test REGISTERmust be
programmed as 0,0,0 in application.
Some device internal signals can be checked at
pin 9 (TSTOUT) and pin 7 (OSC IN) by programming different codes of the test register according
to the Table1.
For example by programming the code 110 the
”fsyn out” will be available at pin 9 and ”f
REF
in-
put” at pin 7.
TABLE1:
Test Register
Status
test0test1test
000S
100 f
010 P
110 f
001 P
PIN9 (TEST/OUT) PIN 7 (OSCIN)
2
out (appl.mode) Oscin (appl.mode)
Test Function
ref Output Oscin (appl.mode)
hi Output fref Input
syn Output fref Input
hi input Oscin (appl. mode)
3.9 C-BUS INTERFACE
This interface allows communication between the
PLL deviceand µp systems.A bus controlsystem
check the format of transmission, only eight bit
word transmission is allowed. Four registers with
6 bit are user programmable. The selection of this
four registersis controlledby twoaddress bits.
9/16
TDA7326
4.0 BIT ORGANIZATION OF THE BUS TRANSFER OPERATION
Loading registers for all bytes of the programmable counters and all control registers
0 1 PC7 PC6
LPF1/
LPF2
CURR 1
SWM
DIRAMFM
1 0 PC5 PC4 PC3 PC2 PC1 PCO ⇒
11
Loading registers for all bytes of the programmable counters and all control registers
0 1 PC7 PC6
11
Loading registers for 11 or 12 bits of the programmable counters
1 0 PC5 PC4 PC3 PC2 PC1 PC0 1 1
Loading registers for 5 or 6 bits of theprogrammable counters
11
Setting control register for loop filter selection charge pump currentbit 1, mode AM/FM selection
01XX
Test mode inizialization(Test0 = Test1 = Test2 = 0)
0 0 TST0 TST1 TST2 S
SC5
SC4 SC3 SC2 SC1 SC0 0 0 0 0 0 S
(0)*
LPF2/
CURR 1
LPF1
SC5
SC4 SC3 SC2 SC1 SC0
(0)*
SC5
SC4 SC3 SC2 SC1 SC0
(0)*
LPF2 /
CURR1 SWM/
LPF1
OUT CURR2 fREF
SWM
DIRAMFM
DIRAMFM
1 0 PC5 PC4 PC3 PC2 PC1 PCO ⇒
SC5
SC4 SC3 SC2 SC1 SC0
(0)*
CURR2 fref
OUT
Setting control register for switch output pin 9, chargepump current bit 2, reference frequency select
00000S
OUT CURR2 fREF
(*) This bit hasto be ”0” for fREF =”1”(fREF =25kHz in FM mode or 2.5KHzAMswallow mode)
5.0 FREQUENCY PROGRAMMATION
5.1 AM/FMComputation Resume
FM SWALLOW MODE
f
=12.5KHz F
REF
= 25KHz F
f
REF
where:
PC =Program CounterValue (PC7 to PC0)
10/16
= (64 ⋅ PC + SC + 64) ⋅ f
VCO
=(DIV_VAL+ 64) ⋅ f
F
VCO
= (32 ⋅ PC + SC + 32) ⋅ f
VCO
F
=(DIV_VAL+ 32) ⋅ f
VCO
REF
REF
REF
REF
swallow6bit
swallow5bit (bit SC5= 0)
SC =Swallow Counter Value(SC5 to SC0)
DIV_VAL= DividerFactor
AMSWALLOWMODE
f
=1KHz F
REF
=(64 ⋅ PC + SC + 64) ⋅ f
VCO
F
= (DIV_VAL+ 64) ⋅ f
VCO
REF
TDA7326
REF
swallow6bit
=2.5KHz F
f
REF
=(32 ⋅ PC + SC + 32) ⋅ f
VCO
F
= (DIV_VAL+ 32) ⋅ f
VCO
REF
REF swallow5bit (bit SC5 =0)
AMDIRECT MODE
F
=(DIV_VAL+1) ⋅ f
VCO
REF
5.2: Examples
a) CONDITIONS:
FM MODE (f
it follows: that F
DIV_VAL =
10000111000000
=
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0
= 98.1MHz, f
RF
= 98.1 + 10.7 = 108.8MHz
VCO
F
VCO
- 32 =4352 - 32 = 4320 = 10 E0 Hex
f
ref
= 25KHz; IF = 10.7MHz
REF
SC = 0 (*)
binary ⇒
PC = 135
b) CONDITIONS:
FM MODE (f
it follows: F
= 98.8MHz, f
RF
= 98.8 + 10.7 = 109.5MHz
VCO
REF
= 25KHz; IF = 10.7MHz
DIV_VAL = 4380 -32 = 4348 = 10 FC Hex
10000111011100
=
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0
NOTE: (*) The bit SC5 isFORCED = 0,and higher weigth bits are left shift ed one position.
SC = 28(*)
binary ⇒
PC = 135
11/16
TDA7326
c) CONDITIONS:
FM MODE (f
it follows: F
= 98.8MHz, f
RF
= 98.8 + 10.7 = 109.5MHz
VCO
= 12.5KHz;IF = 10.7MHz
REF
DIV_VAL = 8760 -64 = 8696 = 21 F8 Hex
10000111111000
=
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0
d) CONDITIONS:
AM DIRECTMODE, (f
it follows: F
DIV_VAL =
00001111010011
=
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0
= 530 + 450 = 980KHz
VCO
F
VCO
± 1 =
f
REF
=530KHz, f
RF
980
± 1 = 979 = 3D3 Hex
1
= 1KHz; IF =450KHz
REF
SC = 56
binary ⇒
PC = 135
binary
e) CONDITIONS:
AM DIRECTMODE, (f
it follows: F
DIV_VAL =
00100001101111
=
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0
= 1710 + 450 = 2160KHz
VCO
F
VCO
± 1 =
f
REF
=1710KHz, f
RF
2160
± 1 = 2159= 86F Hex
1
=1KHz; IF = 450KHz
REF
binary
12/16
Figure5: Application with two loop-filters
TDA7326
*) C7 must be connected as closed aspossible between pin 10 and pin 13
Figure6: PC Board and Component Layout of fig. 5
13/16
TDA7326
DIP16PACKAGE MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
mm inch
14/16
SO16PACKAGE MECHANICAL DATA
TDA7326
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.2 0.004 0.012
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45° (typ.)
D 10.1 10.5 0.398 0.413
E 10.0 10.65 0.394 0.419
e 1.27 0.050
e3 8.89 0.350
F 7.4 7.6 0.291 0.299
L 0.5 1.27 0.020 0.050
M 0.75 0.030
S8°(max.)
mm inch
15/16
TDA7326
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change withoutnotice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All RightsReserved
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