TDA7317
FIVEBANDSDIGITALCONTROLLEDGRAPHICEQUALIZER
VOLUMECONTROLIN 0.375dBSTEP
FIVE BANDS STEREO GRAPHIC EQUAL-
IZER
CENTER FREQUENCY, BANDWIDTH, MAX
BOOST/CUT DEFINED BY EXTERNAL COMPONENTS
±14dB CUT/BOOSTCONTROL IN2dB/STEP
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIALBUS
VERYLOW DISTORTION
VERY LOW NOISE AND DC STEPPING BY
USE OF A MIXED BIPOLAR/CMOS TECHNOLOGY
ORDERING NUMBER: TDA7317
SDIP30
DESCRIPTION
The TDA7317 is a monolithic, digitally controlled
graphicequali zerrealizedin BiCM OS mixedtechnology. The ster eosignal,beforeany filtering,can be at-
BLOCK DIAGRAM
tenuated up to -17.625dB in 0.375dB step.
All the functions can be programmed via serial
bus making easy to build a µPcontrolledsystem.
Signalpath is designedfor verylownoiseanddistortion.
November 1999
1/12
TDA7317
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
T
op
T
stg
R
tjvins
ELECTRICAL CHARACTERISTICS (T
Supply Voltage 10.2 V
S
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -55 to +150 °C
Thermal Resistance Junction pins max 85
=25°C, VS= 9V, RL= 10KΩ,Rg= 600Ω, f = 1KHz VIN=
amb
1Vrms, all controlsin flat position (AV = 0dB) unlessotherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
V
S
I
S
SVR Ripple Rejection f = 300Hz to 10KHz 60 80 dB
Supply Voltage 6 9 10 V
Supply Current 8 14 20 mA
C/W
°
2/12
TDA7317
ELECTRICALCHARACTERISTICS(continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT
V
R
I
IN max
I
NS
Input Resistance 20 30 40 KΩ
Max Input Signal THD = 0.3% 2 2.5 V
Input Separation (1) 80 100 dB
VOLUMECONTROL
C
RANGE
A
A
A
V
VMIN
VMAX
STEP
E
A
E
T
DC
Control Range 17.625 dB
Min. Attenuation -0.5 0 0.5 dB
Max. Attenuation 16.7 17.625 18.6 dB
Step Resolution 0.175 0.375 0.575 dB
Attenuation Set Error -1 1 dB
Tracking Error 0.5 dB
DC Steps adjacent attenuation steps 0 3 mV
GRAPHIC EQUALIZER
THD Distortion 0.01 0.1 %
C
s
e
NO
Channel Separation 80 100 dB
Output Noise BW = 20Hz to 20KHz
820µV
flat, AV = 0dB
A curve 6
BW = 20Hz to 20KHzAV =0dB
S/N Signal to Noise Ratio A
B
C
RANGE
step
Step Resolution 1 2 3 dB
Control Range max boost/cut ±12 ±14 ±16 dB
All bands = max. boost
All bands = max. cut
= 0dB; V
V
ref
=1V
RMS
24
6
100 dB
VDC DC Steps Adiacent Control Steps 0.5 3 mV
AUDIO OUTPUTS
RMS
V
µ
µV
V
µ
V
O
R
L
C
L
R
O
V
OUT
Output Voltage THD = 0.3% 2 2.5 V
Output Load Resistance 2 KΩ
Output Load Capacitance 10 nF
Output Resistance 5 10 20
DC Voltage Level 4.2 4.5 4.8 V
BUS INPUTS
V
IL
V
IH
I
IN
V
O
Input Low Voltage 1V
Input High Voltage 3 V
Input Current -5 +5
Output Voltage SDA
IO= 1.6mA 0.4 V
Acknowledge
ADDRESSPIN (Internal 50KΩ pull down resistor)
V
IL
V
IH
NOTE: The input is grounded thru the 2.2µP capacitors
Input Low Voltage 1V
Input High Voltage VCC-1V V
RMS
Ω
A
µ
3/12
TDA7317
DEVICEDESCRIPTION
The TDA7317 is a five bands, digitally controlled
stereo Graphic Equalizer.
The device is intended for high quality audio application in Hi-Fi, TV and car radio systems where
feature like low noise and THD are key factors. A
mixed Bipolar Cmos Technologyallows:
Cmos analog switches for pop free commutations, high frequency op.amp. (GWB = 10MHz)
and high linearity polisilicon resistor for THD =
0.01 (at Vin = 1Vrms) and a S/N ratio of 102dB.
The internal Block Diagramis shownon page1.
The first stage is a volume control. The control
range is 0 to -17.625dBwith 0.375dBstep.
The very high resolution (0.375dB step) allows
the implementation of closed loop amplitude control system completely free from any acustical effect (steppingvariation and pumping effect).
The volume control is followed by a serial five
bands equalizer. Each filtering cell is the biquad
cell shown in fig. 1
The internal resistor string is fixing the boost/cut
value while the buffer makes the Q (quality factor)
and central frequency, set by external components, fully indipendentfrom the internalresistors.
Each filtering cell is realized using only 4 external
components (2 capacitorsand 2 resistors)allowing a flexible selection of centre frequency fo, Q
factor and gain. Here below the basic formulae
and the key features of each band pass filter are
reported:
= center frequency
f
o
Gv = gain/lossat the centerfrequencyf
Gv = 20log(Av)
o
f
o
=
Q
f2− f
1
wheref2,f1= 3dB Bandwidth limits.
(R2⋅C2)+(R2⋅C1)
=
A
v
(R2 ⋅ C1 )+(R2 ⋅ C2 )
√(R1
=
Q
(R2 ⋅C1 )+(R2 ⋅ C2 )
=
f
o
2π ⋅√(R1 ⋅ R2 ⋅
+ (R1⋅
⋅ C1 ⋅ R2 ⋅ C2 )
1
C1⋅ C2)
C1
)
If C1 is fixed, then:
2
Q
R2 =
C2
π⋅C1⋅
2
R1
=
A
− 1− Q
v
f
(A
v
=
Av− 1 −Q
− 1)
o
1
(A
⋅
A
(
2
⋅ C1
2
−1 ) ⋅ Q
v
− 1 −Q2)
v
⋅
R2
2
Likewise, the components’values can be determinedby fixing oneof theother three parameters.
Referring to fig. 1 the suggested R2 value should
be higher than 2KΩin order to have a good THD
(internalop. amp. current limit).
Viceversa the R1 value should be equal or lower
than 51KΩ in order to keep the ”click”(DC step)
very low.
A typical applicationis shownby fig. 2
Fig. 1
4/12
Figure 2: ApplicationCircuit
TDA7317
The five bands graphic equalizer is used in conjunction with a TDA7318(or anotheraudioprocessor of the SGS-THOMSON731X family).
The audioprocessorbass and treble tone can furnish twoextra filter bands.
Application requiring higher number of external
equalizer bands could be implemented by cascading 2 or more TDA7317 devices. In fact the
dedicated ADDR pin allows 2 addresses selection. Anyway,the addressof the graphicequalizer
is different from the audioprocessorone.
For example 11 bands are implemented by use of
2 TDA7317 plus an audioprocessor (TDA731X
family).
In case one filteringcell is not needed, a shortcircuit must be provided between the P1xy and
P2xypins.
5/12
TDA7317
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7317 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externallyconnected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of theSDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledgebit. TheMSB is transferredfirst.
2
Figure 3: Data Validityon the I
CBUS
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAlineisstableLOWduringthis clockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then
sendsthe new data.
This approach of course is less protected from
misworkingand decreasesthe noise immunity.
Figure 4: TimingDiagram of I
2
Figure 5: Acknowledgeon theI
6/12
CBUS
2
CBUS
TDA7317
SOFTWARESPECIFICATION
Interface Protocol
The interfaceprotocol comprises:
A start condition (s)
A chip address byte, containing the TDA7317
TDA7316 ADDRESS
MSB first byte LSB MSB LSB MSB LSB
S100001A0
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED100kbits/s
ACK
DATA
Data Transferred (N-bytes + Acknowledge)
address(the 8th bit of the bytemust be 0). The
TDA7317must always acknowledgeat theend
of each transmitted byte.
A sequenceof data (N-bytes+ acknowledge)
A stop condition (P)
ACK
DATA
SOFTWARESPECIFICATION
Chip address (84 or 86 Hex)
1
MSB
00001A0
LSB
ACK
P
A = Logic level on pin ADDR
A = 1 if ADDRpin = open
A = 0 if ADDRpin = connectedto ground
SOFTWARESPECIFICATION (continued)
DATA BYTES(detailed description)
Volume
MSB LSB FUNCTION
0 X B2 B1 B0 A2 A1 A0 Volume 0.375dB steps
0
0
0
0
1
1
1
1
0 X B2 B1 B0 A2 A1 A0 Volume -3dB steps
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.375
-0.75
-1.125
-1.875
-2.25
-2.625
0
-1.5
0
-3
-6
-9
-12
-15
7/12
TDA7317
Graphic Equalizer
MSB LSB FUNCTION
1 D3D2D1D0S2C1C0
0
0
0
0
1
D3
D3
0
0
1
1
0
D2
D2
0
1
0
1
0
D1
D1
1
0
C2
C2
0
0
0
0
1
1
1
1
C1
C1
0
0
1
1
0
0
1
1
AX =0.375dB steps, BX = 3dB steps, CX = 2dB steps,X = dont’care
STATUS AFTER POWER-ON RESET
Volume -17.25dB
Graphic equalizer bands -12dB
C0
C0
0
1
0
1
0
1
0
1
Band 1
Band 2
Band 3
Band 4
Band 5
cut
Boost
0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
APPLICATIONINFORMATION
A typical application is indicated in figure 4, while
the P.C. Board and components layout are reported in figure 5. The external components, are
calculatedfor 2 different max boost/cut conditions
TABLE 1: Max Boost/cut= 20 dB (each cell = ±14dB)
F (HZ) Q R1 (KΩ)R2(K
BAND 1 10363.38 1.49 47 5.1 0.820 1.2 13.52
BAND 2 261.03 1.49 47 5.1 33 47 13.63
BAND 3 1036.34 1.49 47 5.1 8.2 12 13.52
BAND 4 3168.08 1.49 47 5.1 2.7 3.9 13.57
BAND 5 59.75 1.11 43 7.5 220 100 13.88
For THD performance the sequence Band 1, 2, 3, 4, 5, is recommended
) C1 (nF) C2 (nF) Av max (dB)
Ω
TABLE2: Max Boost/cut= 17dB (each cell = ±12dB)
F (HZ) Q R1 (KΩ)R2(K
BAND 1 10158.00 1.15 33 6.2 1.2 1 11.83
BAND 2 250.81 1.21 30 5.1 47 56 11.33
BAND 3 977.34 1.20 39 6.8 10 10 11.75
BAND 4 3429.00 1.25 39 6.2 2.7 3.3 11.67
BAND 5 61.82 1.15 33 6.2 180 180 11.27
) C1 (nF) C2 (nF) Av max (dB)
Ω
8/12
Figure 4
Figure 5: PCP Board and componentslayout of the figure 4 (scale 1:1)
TDA7317
9/12
TDA7317
Measurements done on the test jig of fig. 5 using
in figg. 6, 7,8.
the components indicated in table2, are reported
Figure 6: FrequencyResponse Figure7 THDvs FrequencyMax Boost/cut=
:±14dB
Figure 8: Cross Talk vs Frequency
2
Purchaseof I
2
I
C Patent Rights to use these components in an I2C system, provided that the system conforms to
2
the I
C StandardSpecificationsas defined by Philips.
10/12
C Components of SGS-THOMSONMicrolectronics, conveys a license underthe Philips
TDA7317
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 5.08 0.20
A1 0.51
A2 3.05 3.81 4.57 0.12 0.15 0.18
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 0.76 0.99 1.40 0.030 0.039 0.055
C 0.20 0.25 0.36 0.008 0.01 0.014
D 27.43 27.94 28.45 1.08 1.10 1.12
E 10.16 10.41 11.05 0.400 0.410 0.435
E1 8.38 8.64 9.40 0.330 0.340 0.370
e 1.778 0.070
e1 10.16 0.400
L 2.54 3.30 3.81 0.10 0.13 0.15
M0°(min.),15°(max.)
S 0.31 0.012
mm inch
0.020
OUTLINE AND
MECHANICAL DATA
SDIP30 (0.400”)
11/12
TDA7317
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy– All Rights Reserved
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