SGS Thomson Microelectronics STW8NC80Z Datasheet
STW8NC80Z
N-CHANNEL 800V - 1.3 Ω - 6.7A T O-247
Zener-Protected PowerMESH™III MOSFET
TYPE V
DSS
R
DS(on)
I
D
STW8NC80Z 800 V < 1.5 Ω 6.7 A
n
TYPICAL RDS(on) = 1.3 Ω
n
EXTREMELY HIGH dv /d t C APABILITY GATETO-SOURCE ZENER DIODES
n
100% AVALANCHE TESTED
n
VERY LOW INTRINSIC CAPAC ITANCES
n
GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH O VERLAY™ Power
MOSFETs for very high voltage exhibits unsurpassed on-resistance per unit area while integrating
back-to-back Zener diodes between gate and
source. Such arrangement gives extra ESD capability with higher ruggedness performance as requested by a large variety of single-switch applications.
APPLICATIONS
n
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
n
WELDING EQUIPMENT
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
I
GS
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns
T
stg
T
j
(•)Pu l se width limited by safe operat i ng area
≤6.7A, di/dt ≤100A/µs, VDD ≤ V
(1)I
SD
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
800 V
800 V
Gate- source Voltage ±25 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(●)
Drain Current (pulsed) 27 A
Total Dissipation at TC = 25°C
6.7 A
4.2 A
160 W
Derating Factor 1.28 W/°C
Gate-source Current ±50 mA
Gate source ESD(HBM-C=100pF, R=15KΩ) 3KV
Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C
, Tj ≤ T
(BR)DSS
JMAX.
1/8December 2001
STW8NC80Z
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.78 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
∆BV
DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
= 25 °C, ID = IAR, VDD = 50 V)
j
ID = 250 µA, VGS = 0 800 V
6.7 A
275 mJ
Breakdown Voltage
/∆TJBreakdown Voltage Temp.
ID = 1 mA, VGS = 0 0.9 V/°C
Coefficient
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±20V ±10 µA
GS
1µA
50 µA
ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS, ID = 250 µA
DS
= 10 V, ID = 3.3 A
V
GS
345V
1.3 1.5 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 164 pF
Reverse Transfer
Capacitance
ID=3.3 A
V
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
6
2350 pF
17 pF
S
2/8
STW8NC80Z
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON (RESISTIVE LOAD)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
t
r
Q
Q
gs
Q
gd
g
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge 12 nC
Gate-Drain Charge 15 nC
SWITCHING OFF (INDUCTIVE LOAD)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
f
c
Off-voltage Rise Time
Fall Time 13 ns
Cross-over Time 20 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Source-drain Current 6.7 A
(2)
Source-drain Current (pulsed) 24 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 6 µC
Reverse Recovery Current 18 A
= 400V, ID = 3A
DD
R
= 4.7Ω VGS = 10V
G
(see test circuit, Figure 3)
V
= 640V, ID = 6 A,
DD
VGS = 10V
V
= 640V, ID = 6 A,
DD
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
ISD = 6 A, VGS = 0
I
= 6 A, di/dt = 100A/µs,
SD
VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
33 ns
12 ns
43 58 nC
13 ns
1.6 V
680 ns
GATE-SOURCE ZENER DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 25 V
Voltage
αT Voltage Thermal Coefficient T=25°C Note(3) 1.3
I
Rz Dynamic Resistance
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 % .
2. Pulse width li mited by safe operating area .
3. ∆V
= αT (25°-T ) BV
BV
GSO
(25°)
= 20 mA, VGS = 0
D
90 Ω
10
-4
/°C
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specif ically been designed to enhanc e not only t he dev ice’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient and
cost-effective intervention to protect the device’s int egrity. These integrated Zener diodes th us avoid the
usage of external components.
3/8
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