STW40NS15
N-CHANNEL 150V - 0.042Ω - 40A TO-247
MESH OVERLAY™ MOSFET
PRELIMINARY DATA
TYPE V
DSS
STW40NS15 150 V <0.052
■ TYPICAL R
■ EXTREMELY HIGH dv /d t C APABILITY
■ VERY LOW INTRINSIC C APAC ITANCES
■ GATE CHARGE MINIMIZED
(on) = 0.042Ω
DS
R
DS(on)
I
D
Ω
40A
DESCRIPTION
This powermos MOSFET is designed using the
company’s consolidated strip layout-based MESH
OVERLAY
™ process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
■ HIGH CURRENT SWITCHING
■ UNINTERRUPTIBLE POWER SUPPLY (UPS)
■ PRIMARYSWITCH IN ISOLATED DC-DC
CONVERTERS
3
2
1
TO-247
I
NTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt Peak Diode Recovery voltage slope 9 V/ns
T
stg
T
j
(•)Pu l se width limited by safe operating area
October 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
150 V
150 V
Gate- source Voltage ±20 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(1)
Drain Current (pulsed) 160 A
Total Dissipation at TC = 25°C
40 A
25 A
180 W
Derating Factor 0.933 W/°C
Storage Temperature –65 to 175 °C
Max. Operating Junction Temperature 175 °C
1/6
STW40NS15
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.83 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
= 25 °C, ID = IAR, VDD = 50 V)
j
ID = 250 µA, VGS = 0 150 V
40 A
500 mJ
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±20V ±100 nA
GS
1µA
10 µA
(1)
ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS, ID = 250µA
DS
VGS = 10V, ID = 40 A
234V
0.044 0.052
Resistance
I
D(on)
On State Drain Current VDS > I
D(on)
x R
DS(on)max,
40 A
VGS=10V
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 380 pF
Reverse Transfer
Capacitance
ID= 20A
V
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
20 S
2400 pF
160 pF
Ω
2/6
STW40NS15
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Q
Q
gs
Q
gd
g
Turn-on Delay Time
Rise Time
Total Gate Charge VDD = 120V, ID = 40A,
Gate-Source Charge 17 nC
Gate-Drain Charge 47 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
T
t
r(Voff)
t
t
f
f
c
Turn-off Delay Time
Fall Time
Off-voltage Rise Time V
Fall Time 35 ns
Cross-over Time 70 ns
= 75V, ID = 20A
V
DD
RG= 4.7Ω, VGS = 10V
(see test circuit, Figure 3)
VGS = 10V
V
= 75V, ID = 20A
DD
R
=4.7Ω, VGS = 10V
G
(see test circuit, Figure 3)
= 120V, ID = 20 A,
clamp
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
25 ns
45 ns
100 110 nC
85
47 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c yc l e 1.5 %.
2. Pulse width li mited by safe operating area.
Source-drain Current 40 A
(2)
Source-drain Current (pulsed) 160 A
Forward On Voltage
Reverse Recovery Time ISD = 40A, di/dt = 100A/µs,
ISD = 40A, VGS = 0
270 ns
VDD = 50V, Tj = 150°C
(see test circuit, Figure 5)
Reverse Recovery Charge 200 nC
Reverse Recovery Current 1.5 A
1.5 V
3/6
STW40NS15
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
4/6
TO-247 MECHANICAL DATA
STW40NS15
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.7 5.3 0.185 0.209
D 2.2 2.6 0.087 0.102
E 0.4 0.8 0.016 0.031
F 1 1.4 0.039 0.055
F3 2 2.4 0.079 0.094
F4 3 3.4 0.118 0.134
G 10.9 0.429
H 15.3 15.9 0.602 0.626
L 19.7 20.3 0.776 0.779
L3 14.2 14.8 0.559 0.582
L4 34.6 1.362
L5 5.5 0.217
M 2 3 0.079 0.118
mm inch
P025P
5/6
STW40NS15
6/6
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical compo nents in life support devices or systems without express written approval of STMicroelectronics.
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