SGS Thomson Microelectronics STW12NK80Z Datasheet
STW12NK80Z
N-CHANNEL 800V - 0.65Ω - 10.5A T O-247
Zener-Protected SuperMESH™Power MOSFET
TYPE V
DSS
R
DS(on)
I
Pw
D
STW12NK80 Z 800 V < 0.75 Ω 10.5 A 190 W
■ TYPICAL R
■ EXTREMELY HIGH dv /d t C APABILITY
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPAC ITANCES
■ VERY GOOD MANUFACTURING
(on) = 0.65 Ω
DS
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST ’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the
most demanding applications. Such series com plements ST full range of high voltage MOSFE Ts including revolutionary MDmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRAM
ORDERING INFORMATION
SALES TYPE MARKING PACKAGE PACKAGING
STW12NK80Z W12NK80Z TO-247 TUBE
1/9October 2002
STW12NK80Z
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
T
j
T
stg
(l) Pulse wi dth limited by safe operating ar ea
(1) I
≤10.5A, di/dt ≤200A/µs, VDD ≤ V
SD
(*) Limited only by maximum temperature allowed
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W
Rthj-amb
T
l
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
800 V
800 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
(l)
Drain Current (pulsed) 42 A
Total Dissipation at TC = 25°C
10.5 A
6.6 A
190 W
Derating Factor 1.51 W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V
Operating Junction Temperature
Storage Temperature
, Tj ≤ T
(BR)DSS
JMAX.
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
-55 to 150 °C
50
300
°C/W
°C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
10.5 A
400 mJ
GATE-SOURCE ZENER DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/9
STW12NK80Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
ON/OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID = 1 mA, VGS = 0 800 V
Breakdown Voltage
I
I
V
GS(th)
R
DS(on)
DSS
GSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
VDS = Max Rating, TC = 125 °C
V
= ± 20V ±10 µA
GS
V
= VGS, ID = 100 µA
DS
3 3.75 4.5 V
1
50
VGS = 10V, ID = 5.25 A 0.65 0.75 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS = 15 V, ID= 5.25 A 12 S
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3) Equivalent Output
= 25V, f = 1 MHz, VGS = 0 2620
V
DS
250
53
VGS = 0V, VDS = 0V to 640V 100 pF
Capacitance
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Q
Q
Q
Turn-on Delay Time
t
r
g
gs
gd
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 400 V, ID = 5.25 A
RG= 4.7Ω VGS = 10 V
(Resistive Load see, Figure 3)
= 640V, ID = 10.5 A,
V
DD
VGS = 10V
30
18
87
14
44
µA
µA
pF
pF
pF
ns
ns
nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
Turn-off Delay Time
t
f
Fall Time
VDD = 400 V, ID = 5.25 A
RG=4.7Ω VGS = 10 V
70
20
(Resistive Load see, Figure 3)
t
r(Voff)
t
t
Off-voltage Rise Time
f
c
Fall Time
Cross-over Time
= 640 V, ID = 10.5 A,
V
DD
RG=4.7Ω, V
GS
= 10V
(Inductive Load see, Figure 5)
16
15
28
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area.
3. C
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
V
.
DSS
ISD = 10.5 A, VGS = 0
I
SD
V
DD
(see test circuit, Figure 5)
= 10.5 A, di/dt = 100A/µs
= 100 V, Tj = 150°C
635
5.9
18.5
when VDS increase s fr om 0 to 80%
oss
10.5
42
1.6 V
ns
ns
ns
ns
ns
A
A
ns
µC
A
3/9
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