- ADC TRIGGER DURING RETRACE TIME OFA
PROGRAMMED LINE
■ INCLUDES FACILITIES FOR SCREEN SIZE &
CENTERING AUTO SETUP
- HS, VS, VIDEO TIMING MEASUREMENTS
■ 100MHz MAX. PIXEL CLOCK, AVAILABLE FOR
ANY LINE FREQUENCY BETWEEN 15 AND 140
kHz
■ 12 x 18 CHARACTER ROM FONT INCLUDES:
- 240 MONOCOLOR CHARACTERS
- 16 MULTICOLOR CHARACTERS
■ CHARACTER FLASHING
■ UP TO 1K CHARACTERS TEXT DISPLAY
■ ULTRAHIGH FREQUENCY PLL FOR
■ JITTER-FREE DISPLAY
■ FLEXIBLE DISPLAY:
- ANY CHARACTER WIDTH AND HEIGHT
- ANYWHERE IN THE SCREEN
■ SINGLE BYTE CHARACTER CODES AND
COLOR LOOK-UP TABLE FOR EASY PROGRAMMING AND FAST ACCESS
■ CHARACTER FLIP OPERATIONS
■ WIDE DISPLAY WINDOW ALLOWS PATTERN
GENERATION FORFACTORY ADJUSTMENTS
2
■ I
C BUS MCU INTERFACE
■ FIVE 8 BITS PWM DAC OUTPUTS
DESCRIPTION
Connected to a host MCU via its serial I2C Bus, the
STV9432TAP is a multifunction slave peripheral
device integrating the following blocks:
- On-screen Display. It includes a MASK PROGRAMMABLE ROM that holds the CUSTOM
CHARACTER FONT, a 1Kbytes RAM that stores
the code strings of the different lines of text to be
displayed, and a set of registers to program character sizes and colors. A built-in digital PLL, oper-
ating at very high frequency, gives an accurrate
display without visible jitter for a wide line frequency range from 15 to 140 kHz.
- Cut-off Monitoring Circuitry includes: 5 x 8 bits
PWM DACs, 3 x 8 bits ADCs and a programmable
ADC sampling trigger. It gives the possibility to
measure the three beam currents, during the horizontal flyback, at a given line in the frame, provided that the three ADC inputs are connected to a
beam current sensing circuitry. The values are
stored in three BEAM CURRENT REGISTERS,
and available for MCU read.
- Video Timing Analyzer. Using the HorizontalSync,
Vertical Sync, Horizontal Flyback, and ”Video
Active” inputs, a set of counters give the different
timing measurements necessary to analyze the
current Video timing characteristics in order to
make the automaticset-up of screen size and centering. The measurements are initialized on the
same programmable trigger line than in the above
cut-offmonitoring circuitry.
.
SO28
(Plastic Micropackage)
ORDER CODE:STV9432TAP
Version 4.0
February 20001/25
This ispreliminary information on a new product indevelopment orundergoing evaluation. Details are subject tochange without notice.
Power+5V Supply for the RGB Outputs
PowerAnalog +5V Power Supply
24BCIIBlue Beam Current Input
25GCIIGreen Beam Current Input
26RCIIRed Beam Current Input
27ADCREFI/OADC Reference Voltage Pin
28TESTI/OPin to be connected to ground
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Low Voltage
Input High VoltageHS, VS, AV
Schmidt Trigger Hysteresis
Pull-up Source Current (VIN= 0V)
Horinzontal Synchro Input Range
Output Low Voltage (IOL= 3mA)
Output Low Voltage (IOL= 3mA)
Output High Voltage (IOH= 3mA)
XTI Input Source Current (VIN= 0V)
XTI Input Sink Current (VIN=VDD)
XTI Input Low Voltage
XTI Input High Voltage
XTI Output Low Voltage (IOL= 3mA)
XTI Output High Voltage (IOH= 3mA)
Output Voltage Reference
Output Low Voltage (IOL= 1.6mA)
Output High Voltage (IOH= -0.8mA)
PWM Period
Supply Threshold Level
Input Voltage
Input Impedance
Input Offset Voltage
Input Leakage Current
Integral Linearity Error (Note 2)
Differential Linearity Error (Note 2)
HFLY
4.7555.25V
--150mA
2.4V
-1+1µA
2.4
3.6
15-140kHz
00.4V
00.4V
0.8V
DD
315µA
315µA
0.7V
DD
00.4V
0.8V
DD
00.4V
VCC- 0.5V
0V
-2+2LSB
-0.5+0.5LSB
STV9432TAP
0.8V
0.8V
V
0.4V
100µA
V
DD
1.4V
V
DD
3.3V
256t
3.6V
ADCREF
100k
3LSB
050µA
V
V
V
OSC
V
Ω
5/25
STV9432TAP
6 - TIMINGS
SymbolParameterMin.Typ.Max.Unit
OSCILLATOR
f
OSC
f
PXL
R, G, B, FBLK (C
2
I
C INTERFACE: SDAAND SCL (see Figure 1)
t
ANALYZER (HS, HFLY,AV)
t
LOAD
t
R
t
F
t
SKEW
f
SCL
t
BUF
t
HDS
t
SUP
t
LOW
t
HIGH
t
HDAT
SUDAT
t
F
t
R
t
HLOW
HHIGH
Hs
ANALYZER (VS)
t
VLOW
t
VHIGH
Clock Frequency
Maximum PixelFrequency
= 30pF)
Rise Time (see Note 1)
Fall Time (see Note 1)
Skew between R, G, B, FBLK
SCL Clock Frequency
Time the bus must be free between 2 access
Hold Time for Start Condition
Set up Time for Stop Condition
The Low Period of Clock
The High Period of Clock
Hold Time Data
Set up Time Data
Fall Time of SDA
Rise Time of both SCL and SDA
Low Pulse Width(see Note 3)
High Pulse Width
Hs Frequency
Low Pulse Width
High Pulse Width
0400kHz
500ns
500ns
500ns
400ns
400ns
0ns
500ns
Depend on the pull-up resistor and the
24091t
24091t
24091Lines
24091Lines
Notes:
- These parameters are not tested on each unit. They are measured during our internal qualification procedure which
includes characterization on batches coming from corners of our processes and also temperature characterization.
- The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal
devices.
-t
HTIM
=3t
OSC
: 40.
Figure 1.
8MHz
100MHz
5ns
5ns
5ns
20ns
load capacitance
HTIM
HTIM
Hfly
6/25
STOP STARTDATA
t
BUF
SDA
t
HDS
SCL
t
HIGH
t
SUDAT
t
HDAT
t
LOW
t
SUP
STOP
7 - SERIAL INTERFACE
The 2-wires serial interface is an I2C interface. To be
connected to the I
address; the slave addressof the STV9432TAP is BA
(in hexadecimal).
A6A5A4A3A2A1A0RW
1011101
7.1 - Data Transfer in Write Mode
The host MCU can write data into the STV9432TAP
registers or RAM.
To write data into the STV9432TAP, after a start, the
MCU must send (Figure2):
- First, the I
the R/W bit,
- The two bytes of the internal address where the
MCU wants to write data,
Figure 2. I2C Write Operation
SCL
SDA
2
C bus, a device must own its slave
2
C address slave byte with a lowlevel for
R/W
A7 A6 A5 A4 A3 A2 A1 A0-- A13 A12 A11 A10 A9 A8
I2C Slave Address
ACKLSB AddressACKMSB AddressACKStart
STV9432TAP
- The successivebytes of data.
All bytes are sent MSB bit first and the write data
transfer is closed by a stop.
7.2 - Data Transfer in ReadMode
The host MCU can read data from the STV9432TAP
register, RAM or ROM.
To read data from the STV9432TAP (Figure 3), the
MCU must send 2 different I
one is made of I
2
C slave address byte with R/W bit at
low level and the 2 internal address bytes.
The second one is made of I
with R/W bit at high level and all the successive data
bytes read at successive addresses starting from the
initial address given by the first sequence.