128 ALPHANUMERIC CHARACTERS OR
GRAPHIC SYMBOLS IN INTERNAL ROM
(12 x 18 DOTMATRIX)
.
UP TO 26 USERDEFINABLECHARACTERS
.
INTERNALHORIZONTAL PLL(15 TO120kHz)
.
PROGRAMMABLE VERTICAL HEIGHT OF
CHARACTER WITH A SLICEINTERPOLATOR
TO MEET MULTI-SYNCH REQUIREMENTS
.
PROGRAMMABLE VERTICAL AND HORIZONTALPOSITIONING
.
FLEXIBLESCREENDESCRIPTION
.
CHARACTER BY CHARACTER COLOR SELECTION(UP TO 8 DIFFERENT COLORS)
.
PROGRAMMABLE BACKGROUND (COLOR,
TRANSPARENTOR WITH SHADOWING)
.
CHARACTER BLINKING
.
2-WIRES ASYNCHRONOUS SERIAL MCU
INTERFACE (I
.
4 x 8 BITS PWM DAC OUTPUTS ON THE
STV9421
.
SINGLEPOSITIVE5V SUPPLY
2
C PROTOCOL)
STV9420
STV9421
DIP16
(Plastic Package)
ORDER CODE : STV9420
DESCRIPTION
The STV9420/21is an ON SCREEN DISPLAYfor
monitor.It is built as a slaveperipheralconnected
to a host MCU via a serial I
display memory, controls all the display attributes
and generatespixels from the data read in its on
chip memory. The line PLL and a special slice
interpolator allow to have a display aspect which
doesnotdependonthelineandframefrequencies.
2
C interface allows MCU to make transparent in-
I
ternal accessto preparethe next pagesduring the
display of the current page. Toggle from one page
to anotherby programmingonly one register.
4 x 8 bits PWM DAC are available (STV9421) to
provide DC voltage control to other peripherals.
The STV9420/21providesthe user aneasy to use
and cost effective solutionto displayalphanumeric
or graphicinformation on monitor screen.
Output Low Voltage (IOL= 1.6mA)00.4V
Output High Voltage (IOL= -0.1mA)0.8 V
DD
V
DD
9420-02.TBL
V
A
V
9420-03.TBL
Figure 1 : TypicalR, G, B OutputsCharacteristics
(V)
V
,
V
OH
V
OL
I (A)
10
-4
10
-3
10
-2
10
-1
5
2.5
0
V
10
OLOH
-5
9420-17.EPS
4/16
STV9420 - STV9421
TIMINGS
SymbolParameterMin.Typ.Max.Unit
OSCILATOR INPUT : XTI (see Figure 2)
t
WH
t
WL
f
XTAL
f
PXL
RESET
t
RES
R, G, B, FBLK (C
t
R
t
F
t
SKEW
2
I
C INTERFACE : SDA AND SCL (see Figure 3)
f
SCL
t
BUF
t
HDS
t
SUP
t
LOW
t
HIGH
t
HDAT
t
SUDAT
t
F
t
R
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
Clock High Level35ns
Clock Low Level35ns
Clock Frequency615MHz
Pixel Frequency30MHz
Reset High Level Pulse4
= 30pF)
LOAD
Rise Time (Note 1)5ns
Fall Time (Note 1)5ns
Skew between R, G, B, FBLK (Note 1)5ns
SCL Clock Frequency01MHz
Time the bus must be free between 2 access500ns
Hold Time for Start Condition500ns
Set up Time for Stop Condition500ns
The Low Period of Clock400ns
The High Period of Clock400ns
Hold Time Data0ns
Set up Time Data375ns
Fall Time of SDA20ns
Rise Time of Both SCL and SDA
characterization on batches comming from corners of our processes and also temperature characterization.
Depend on the pull-up resistor
and the load capacitance
µs
9420-04.TBL
Figure2
XTI
Figure 3
STOP STARTDATASTOP
t
t
WL
SDA
t
WH
SCL
9420-03.EPS
BUF
t
HDS
t
HIGH
t
S UDAT
t
HDAT
t
SUP
t
LOW
9420-04.EPS
5/16
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