SGS Thomson Microelectronics STV5348 Datasheet
MONOCHIP TELETEXT AND VPS DECODER
.
COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A SINGLE CHIP
.
UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS SGS-THOMSON’s MULTICHIP
SOLUTIONS (SAA5231, SDA5243, STV5345)
.
PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE SEPARATLY
.
DEDICATED "ERROR FREE" OUTPUT FOR
VALID PDC DATA
.
INDICATION OF LINE 23 FOR EXTERNAL
USE
.
SINGL E +5V SUPPLY VOLTAGE
.
SINGLE 13.875MHz CRYSTAL
.
REDUCED SET OF EXTERNAL COMPONENTS, NO EXTERNA L ADJUSTMEN T
.
OPTIMIZED NU MBER OF DIGITAL SIGNALS
REDUCING EMC RADIATION
.
HIGH DENSITY CMOS TEC HNOLO GY
.
DIGITAL DATA SLICER AND DISPLAY
CLOCK PHASE LOCK LOOP
.
28 PIN D I P & SO PACKAGE
STV5348
STV5348/H - STV5348/T
WITH 8 INTEGRATED PAGES
DIP28
(Plastic Package)
ORDER CODE :
STV5348 West European
STV5348/H East European
STV5348/T Turkish & European
SO28
(Plastic Package)
ORDER CODE :
STV5348D West European
STV5348D/H East European
STV5348D/T Turkish & European
PIN CONNECTIONS
DESCRIPTION
The STV5348 decoder is a computer-controlled
teletext device including an 8 page internal memory . Data slicing and capturing extracts the teletext
information embedded in the composite video signal. Control is accomplished via a two wire serial
2
I
C bus . Chip address is 22h. Internal ROM provides a character set suitable to display text using
up to seven national languages. Hardware and
software features allow selectable master/slave
synchronization configurations. The STV5348 also
supports facilities for reception and display of current level protocol data.
September 1998
CVBS
MA/SL
V
DDA
POL
STTV/LFB
FFB
V
SSD
RGB REF
BLAN
COR
1
2
3
4
5
6
7
R
8
G
9
B
10 19
11 18
12 17
13 16
14 15ODD/EVEN
28
27
26
25
24
23
22
21
20
CBLK
TEST
V
SSA
V
SSO
XTI
XTO
V
DDD
VCR/TV
RESERVED
DV
L23
SDA
SCL
Y
5348-01.EPS
1/22
STV5348 - STV5348/H - STV5348/T
PIN DESCRIPTION
o
Pin N
1 CVBS Input Composite Video Signal Input through Coupling Capacitor 9
2
3V
4 POL Input STTV / LFB / FFB Polarity Selection 12
5 STTV/LFB Output / Input Composite Sync Output, Line Flyback Input 15
6 FFB Input Field Flyback Input 12
7V
8 R Output Video Red Signal 13
9 G Output Video Green Signal 13
10 B Output Video Blue Signal 13
11 RGBREF Supply DC Voltage to define RGB High Level 13
12 BLAN Output Fast Blanking Output TTL Level 15
13
14
15 Y Output Open Drain Foreground Information Output 15
16 SCL Input Serial Clock Input 16
17 SDA Input/ Output Serial Data Input/Output 17
18 L23 Output Line 23 Identification 15
19
20 RESERVED Test To be connected to V
21
22 V
23 XTO Crystal Output Oscillator Output 13.875MHz 14
24 XTI Crystal Input Oscillator Input 13.875MHz 14
25 V
26 V
27 TEST Test Grounded to V
28 CBLK Input / Output To connect Black Level Storage Capacitor 28
Symbol Function Description Figure
MA/SL Input Master/Slave Selection Mode 11
DDA
SSD
Analog Supply +5V -
Ground Digital Ground -
COR Output Open Drain Contrast Reduction Output 15
ODD/EVEN Output 25Hz Output Field synchronized for non-interlaced display 15
DV Output VPS Data Valid 15
through a resistor 15
SSD
VCR/TV Input PLL Time Constant Selection 15
DDD
SSO
SSA
Digital Supply +5V -
Ground Oscillator Ground Ground Analog Ground -
SSA
11
5348-01.TBL
BLOCK DIAGRAM
2/22
CVBS
CBLK
VCR/TV
XTI
XTO
V
SSO
SCL
SDA
STTV/LFB
1
28
21
24
23
25
16
17
STV5348
POLFFB
MA/SL
CLAMPING
SYNCHRONIZING
DATA EXTRACTION
OSCILLATOR
FREQUENCY
SYNTHETIZER
TIME BASE
2
I C BUS
INTERFACE
7 26 1411
V
V
SSD
SSA
L23
18
Data
Clock
27
TEST
V
DATA DECODING
DATA
PROCESSING
Data
8 PAGES
MEMORY
Data
Address
DISPLAY
INTERFACE
RGB REF
ODD/EVEN
DDD
CTRL
Address
V
CTRL
DDA
3225 6 2 4
19
20
12
13
8
9
10
15
DV
TEST
BLAN
COR
RED
GREEN
BLUE
Y
5348-02.EPS
STV5348 - STV5348/H - STV5348/T
ABSOL UT E MAXIMUM R ATING S
Symbol Parameter Value Unit
V
DD
V
V
O
∆
V
DD
T
oper
T
stg
Positive Supply Voltage on V
Input Voltage (any input) - 0.3, VDD + 0.5 V
I
DDD
and V
DDA
- 0.3, 6.0 V
Output Voltage (any output) - 0.3, VDD + 0.5 V
Difference between V
DDD
, V
DDA
0.25 V
Operating Ambient Temperature 0, + 70
Storage Temperature - 40, + 150
o
C
o
C
5348-02.TBL
ELECTRICAL CHARACTERISTICS
= 5V, VSS = 0V, TA = 25oC)
(V
DD
Symbol Parameter Min. Typ. Max. Unit
SUPPLIES
V
I
I
DD
DDD
DDA
Supply Voltage 4.75 5 5.25 V
V
Pin Supply Current 30 mA
DDD
V
Pin Supply Current 5 mA
DDA
INPUTS
CBLK
I
BLKO
I
BLKI
Source Current (V
Sink Current (V
CBLK
= 2V, V
CBLK
= 2V, V
= 0V) 80
CVBS
= 1V)) - 10
CVBS
CVBS
CVBSI Video Input Amplitude (peak to peak) 1 V
CVBSC Input Capacitance 10 pF
t
SYNC
V
CLAMP
I
CLPH
I
CLPL
Delay from CVBS to TCS Output from STTV Pin 200 ns
Clamping Level at Synchro Pulse 0 mV
High Level Clamp Current (CVBS = V
Low Level Clamp Current (CVBS = V
+ 1V) 5
CLAMP
- 0.3V) - 400
CLAMP
MA/SL, POL, LFB, FFB, VCR/TV
V
V
IH
I
IL
C
Input Voltage Low Level - 0.3 + 0.8 V
IL
Input Voltage High Level 2 V
Input Leakage Current (VI = 0 to V
Input Capacitance 10 pF
I
) - 10 + 10
DDD
DD
SCL, SDA
V
V
I
f
SCL
tR, t
C
IL
IH
IL
Input Voltage Low Level - 0.3 + 1.5 V
Input Voltage High Level 3 V
Input Leakage Current (VI = 0 to VDD) - 10 + 10
Clock Frequency (SCL) 100 kHz
Input Rise and Fall Time (10 to 90%) 2
F
Input Capacitance 10 pF
I
DD
RGB REF
V
I
I
Input Voltage VDD - 0.5V V
I
DDVDD
Input Current 50 mA
+ 0.3V V
µ
A
µ
A
µ
A
µ
A
V
µ
A
V
µ
A
µ
s
5348-03.TBL
3/22
STV5348 - STV5348/H - STV5348/T
ELECTRICAL CHARACTERISTICS -
= 5V, VSS = 0V, TA = 25oC (continued)
V
DD
Symbol Parameter Min. Typ. Max. Unit
OUTPUTS
RGB
V
V
C
t
R
Output Low Voltage (IOL = 2mA) 0.4 V
OL
Output High Voltage (IOH = -2mA, RGB REF = VDD/2) RGB REF - 0.5 RGB REF V
OH
Load Capacitance 50 pF
L
, t
Rise and Fall Time (10 to 90%) 20 ns
F
BLAN
V
V
C
t
R
Output Low Voltage (IOL = 2mA) 0 0.4 V
OL
Output High Voltage (IOH = -0.2mA) VDD - 0.5 V
OH
Load Capacitance 50 pF
L
, t
Rise and Fall Time (10 to 90%) 20 ns
F
ODD/EVEN, STTV, L23, DV
V
V
C
t
R
Output Low Voltage(I
OL
Output High Voltage (IOH = -0.2mA) VDD - 0.8 V
OH
Load Capacitance 50 pF
L
, t
Rise and Fall Time (10 to 90%) 20 ns
F
COR AND Y (with Pull up to V
V
I
C
OLL
Output Low Voltage (IOL = 2mA) 0 0.5 V
OL
Load Capacitance 25 pF
L
t
Fall Time (RL = 1.2kΩ, V
F
Output Leakage Current -10 +10
= 2mA) 0 0.5 V
OL
)
DDD
- 0.5V to 1.5V) 50 ns
DDD
DD
SDA
V
C
Output Low Voltage (IOL = 3mA) 0 0.5 V
OL
t
Fall Time (3.0 to 1.0V) 200 ns
F
Load Capacitance 400 pF
L
CRYSTAL OSCILLATOR
XTI, XTO
f
XTAL
R
BIAS
C
Crystal Frequency 13.875 MHz
Internal Bias Resistance 0.4 1 3 M
Input Capacitance 7pF
I
TIMING
SERIAL BUS (referred to VIH = 3V, VIL = 1.5V)
Clock :
t
LOW
t
HIGH
t
SU, DAT
t
HD, DAT
t
SU, STO
t
BUF
t
HD, STA
t
SU, STA
●
Low Period
●
High Period
4
4
Data Set-up Time 250 ns
Data Hold Time 170 ns
Stop Set-up Time from Clock High 4
Start Set-up Time following a Stop 4
Start Hold Time 4
Start Set-up Time following Clock Low to High Transition 4
V
µ
A
Ω
µ
s
µ
s
µ
s
µ
s
µ
s
5348-04.TBL
4/22
STV5348 - STV5348/H - STV5348/T
Figure 1 :
Figure 2 :
SDA
Display Output Timing
LSP
(TCS)
R.G.B.Y
(1)
R.G.B.Y
(1)
Serial Bus Timing
t
BUF
04.66 64
0
0
16.67 56.67
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
(b) FIELD RATE
t
LOW
40ms
(a) LINE RATE
all timings in ms
31229141
line numbers
5348-03.EPS
t
F
SCL
SDA
VIH = 3V , VIL = 1.5V
Figure 3 :
Master Synchronization Mode - Hardware Configuration
+5V
MA/SL
POL
t
HD,STA
t
R
t
HD,DAT
t
SU,STA
t
HIGH
t
SU,STO
t
SU,DAT
5348-04.EPS
Output signal on STTV Pin :
Synchro
1
Extractor
Line PLL Line PLL
POL grounded
VCS when R1D2 = 0
TCS when R
2
= "0"
R
1D2
4
VCS
TCS
R
1D2
= "1"
Bit R1D
2
I2C
Control
POL to V
DD
VCS when R
TCS when R
1D2
1D2
1D2
= 1
= 0
= 1
STTV
5348-05.EPS
5/22
STV5348 - STV5348/H - STV5348/T
Figure 4 :
Figure 5 :
Master Synchronization Mode - Delivered Composite Synchronization Signal
VCS, TCS
(interlaced)
621
622
623
624
(308)
(309)
(310)
VCS, TCS
(interlaced)
309 310 311 312 313 314
TCS
(non-interlaced)
308 309 310 311 312 1 2 3 4 5 6
The number positions indicate the end of lines.
Internal signals :
- VCS composite synchro from CVBS signal,
- TCS Teletext composite synchro.
(311)
625
(312)
12 3456
315
316
317
(1)
(2)
(3)
(4)
318
(5)
Slave Synchronization Mode
LFB
SCS
6
FFB
+5V
MA/SL
+5V
2 5
POL
4
319
(6)
5348-06.EPS
Figure 6 :
POL grounded, Inputs Signals :
LFB line flyback synchro on Pin 5
are
FFB field flyback synchro on Pin 6
or SCS synchro composite signal on Pins 5 and 6
Note : R1D0 and R1D1 must be set to 1.
Data Valid Timing (
DV)
Field 0
DV for
VPS Data
Line 16
POL to VDD, Inputs Signals :
are LFB line flyback synchro on Pin 5
FFB field flyback synchro on Pin 6
or SCS synchro composite signal on Pins 5 and 6
5348-07.EPS
Field 1 Field 0
5348-08.EPS
6/22
FUNCTIONAL DESCRIPTION
I - Displayable Page Memory Map
The organization of a page-memory is shown in
Figure 7.
The display area consists of 25 rows of 40 characters per row.
The organization is as follows :
- Row zero contains the page header :
•
The first seven characters (0 - 6) are used for
messages regarding the operational status.
•
The eighth character is an alphanumeric control
character either "white" or "green" defining the
"search" status of the page. When it is "white"
the operational state is normal and the header
appears white ; when it is "green" the opera-
Figure 7 :
Page Memory Organization
Fixed characters
7 Status
Characters
Alphanumerics white
for normal,
green on search
24 characters from page header
rolling on page search
STV5348 - STV5348/H - STV5348/T
tional state cor responds to the "s earch mode"
and the header appears green.
•
The following twenty-four characters give the
header of the requested page when the system
is in search mode.
•
The last eight characters display the time of day .
- Row number twenty-four is used by the microprocessor for the display of information, or used
to display X/24 colored key data according to
R0D7 bit.
- Row twenty-five comprises ten bytes of control
data concerning the received page (see T able 1)
and fourteen free bytes which can be used by the
microprocessor.
8 scrolling
time characters
ROW
17248
MAIN PAG E DISPLAY AREA
row free for status (R0D7 = 0) or packet X/24 (R0D7 = 1)
10 14
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10 bytes for received
page information
14 bytes free
for use by
µ
C
5348-09.EPS
7/22
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