SGS Thomson Microelectronics STV0118 Datasheet

PAL/NTSCHIGH PERFORMANCE DIGITALENCODER

NTSC-M, PAL-B, D, G, H, I, N, M, PLUS NTSC-4.43 ENCODING (OPTIONAL PEDES-

TALIN ALL STANDARDS)

SMALL AND ECONOMICAL SO28 PACKAGE

LINE SKIP/INSERT CAPABILITY SUPPRESSINGTHE NEED FOR AN EXTERNALVCXO, THUSREDUCINGAPPLICATIONCOST

4 SIMUL TANEOU SANALOG OUTPUTS : RGB + CVBS,or S-VHS(Y/C)+ CVBS1+ CVBS2

54MHz INPUT MULTIPLEX INTERFACE FOR DOUBLE ENCODING APPLICATIONS

(TOBEABLE TOENCODE ORNOTTHE OSD CONTENTOF THEVIDEOINPUTSTREAM)

CROSS-COLOR REDUCTION BY SPECIFIC TRAP FILTERING ON LUMA WITHIN CVBS FLOW

CLOSED CAPTION IN G, CGMS ENCODIN G AND TELETEXT ENCODING

STV0118

PRELIMINARY DATA

24-BIT DIRECT DIGITAL FREQUENCY SYNTHESIZERFORCOLORSUBCARRIER

PROGRAMMABLE RESET OF COLOR SUBCARRIERPHASE (4 MODES)

EASYCONTROLVIAFASTI2C BUS

TWOI2C ADDRESSES

AUT OTEST OPE R ATION MOD E (ON-CH IP COLORBARPATTERN100/0/75/0)

CMOS TECHNOLOGY WITH 3.3V POWER SUPPLY

APPLICATIONS : SATELLIT E, CABLE & TER RESTRIALDIGIT ALTV DECOD ER S,MULTIMEDIATERMINALS,DVDPLAYERS

ITU-R/CCIR601 ENCODING WITH EASILY PROGRAMMABLE COLOR SUB-CARRIER FREQUENCIES

DIGITAL FRAME SYNC INPUT/OUTPUT (ODDEV/VSYNC), PROGRAMMABLE POLARITYAND RELATIVEPOSITION

DIGITAL HORIZONTAL SYNC INPUT/OUPUT (HSYNC), PROGRAMMABLEPOLARITYAND RELATIVE POSITION

DIGITAL LINE OR FRAME SYNC EXTRACTION FROM ITU-R/CCIR656 / D1 DATA

MASTER OPERATION MODE, PLUS 6 SLAVEMODES

INTERLACED/NON-INTERLACED OPERATION MODES

FULLOR PARTIAL VERTICALBLANKING

LUMAFILTERINGWITH 2XOVERSAMPLING& SINY/YCORRECTION

CHROMINANCE FILTERINGWITH 4X OVERSAMPLING TO EITHER 1.1MHz, 1.3MHz,

1.6MHzor 1.9MHz

WIDE CHROMINANCE BANDWIDTH FOR RGB ENCODING (2.45MHz)

SO28

(Plastic Micropackage)

ORDER CODE : STV0118

May 1997

This isadvanceinformationon a new product now in development or undergoing evaluation. Detailsare subject to change without notice.

1/42

STV0118

CONTENTS Page

I GENERALDESCRIPTION............................................... 3

II PIN INFORMATION .................................................... 3

II.1 PIN CONNECTIONS. . . . ................................................ 3

II.2 PIN DESCRIPTION. .................................................... 4

III BLOCK DIAGRAM..................................................... 5

IV FUNCTIONAL DESCRIPTION............................................ 6

IV.1 DATA INPUT FORMAT. ................................................. 6

IV.2 VIDEOTIMING . ....................................................... 6

IV.3 RESETPROCEDURE . ................................................. 10

IV.4 MASTERMODE . . . . ................................................... 11

IV.5 SLAVEMODES . . . . ................................................... 12

IV.5.1 Synchronizationonto a LineSync Signal . . . . . . . ............................. 12

IV.5.2 Synchronizationonto a FrameSync Signal . . .. . . . . . ......................... 13

IV.5.3 Synchronizationonto Data-embeddedSync Words . . . . . . . . . ................... 14

IV.6 INPUTDEMULTIPLEXER . .............................................. 15

IV.7 SUB-CARRIER GENERATION. ........................................... 15

IV.8 BURSTINSERTION. . . . ................................................ 16

IV.9 LUMINANCEENCODING. . . . . . . . . . . . . . . . . .. . . . . ......................... 16

IV.10 CHROMINANCE ENCODING. . . . . . . . . . . . . . . . . . . . . . . ...................... 17

IV.11 COMPOSITEVIDEO SIGNAL GENERATION. . . . . . .......................... 17

IV.12 RGB ENCODING . . .. . . . . . . . . . . . . . . . . . . . . . . . ........................... 18

IV.13 CLOSEDCAPTIONING . . . . ............................................. 18

IV.14 CGMSENCODING. .................................................... 19

IV.15 TELETEXTENCODING . . . . ............................................. 19

IV.15.1 Signals Exchanged. .................................................... 19

IV.15.2 Transmission Protocol. . . . . . . . . . . . . . . . . .. . . . ............................. 19

IV.15.3 Programming. . . . ...................................................... 20

IV.15.4 Teletext Pulse Shape . . . . . . . . . . . . . . . . . . . . . . ............................. 20

IV.16 I

IV.17 DUAL ENCODING APPLICATIONWITH 54MBIT/S YCRCB INTERFACE . . . . . . . . . . 22

IV.18 LINE SKIP / LINE INSERTCAPABILITY . . . . . . . ............................. 24

IV.19 CVBS,S-VHS AND RGB ANALOG OUTPUTS . . . .. . . . . ...................... 24

CBUS............................................................ .. 21

V CHARACTERISTICS ................................................... 25

V.1 ABSOLUTEMAXIMUM RATINGS . ........................................ 25

V.2 THERMAL DATA . . .. . . . . . . . . . . . . . . . . . . . . . . . ........................... 25

V.3 DC ELECTRICALCHARACTERISTICS. . . . ................................. 25

V.4 AC ELECTRICALCHARARCTERISTICS. . . . . . . ............................. 26

VI REGISTERS.......................................................... 27

VI.1 REGISTERMAPPING . ................................................. 27

VI.2 REGISTERCONTENTS AND DESCRIPTION. . . . . . .......................... 28

VII APPLICATION ........................................................ 41

VIII PACKAGE MECHANICAL DATA ......................................... 42

2/42

I - GENERALDESCRIPTION

The STV0118 is a high performance PAL/NTSC digital encoderin a low cost pakage. It converts a 4:2:2 digital video stream into a standard analog basebandPAL/NTSCsignal and into RGB analog components.The STV0118can handle interlaced mode(with 525/625 line standards)and non-interlaced mode. It can perform Closed-Captions, CGMSor Teletextencoding.

II - PIN INFORMATION II.1 - Pin Connections

STV0118

Four analog output pins are available, on which it is possible to output either S-VHS(Y/C) + CVBS1 + CVBS2or RGB + CVBS. Moreover,it is possible to use two STV0118 in parallel to interface with SGS-THOMSON’s MPEG decoder ICs that are able to deliver a 54Mbit/s “double” YCrCb stream (e.g. the STi3520M). This allows for example to encode OSD in one of the streamsonly.

HSYNC YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0

CVBS

VR_CVBS

REF(CVBS)

SSA

1 2 3 4 5 6 7 8 9

10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VSYNC/ODDEVEN SDA SCL RESET CKREF TTXD TTXS/CSI2C V

G/Y R/C B/CVBS VR_RGB I

REF(RGB)

DDA

0118-01.EPS

3/42

STV0118

II - PIN INFORMATION (continued) II.2 - Pin Description

Pin Name Type Function

1 HSYNC I/O LineSynchronization Signal :

YCrCb7

YCrCb6

YCrCb5

YCrCb4

YCrCb3

YCrCb2

YCrCb1

YCrCb0

10 V

Supply Digital Ground

11 CVBS Output Analog Composite VideoOutput (current-driven).

12 VR_CVBS I/O Internal Reference Voltage for the 9-bit DAC CVBS.

13 I

REF(CVBS)

14 V 15 V 16 I

REF(RGB)

SSA DDA

Supply Analog ground for DACs Supply Analog positive power supply for DACs (+3.3V nom.)

17 VR_RGB I/O Internal reference voltage for the 9bit Tri-DAC R/Y,G/C,B/CVBS.

18 B/CVBS O Analog ‘Blue’ or CVBS output (current-driven).

19 R/C O Analog ‘Red’ or S-VHS Chrominance output (current-driven).

20 G/Y O Analog ‘Green’ or S-VHS Luminance output (current-driven).

21 V

Supply Digital positive supply voltage (+3.3V nom.)

22 TTXS/CSI2C I/O Output : positive sync pulse for control of Teletext buffer in external demultiplexer or

23 TTXD I/O Teletext data stream from external demultiplexer or Transport IC synchronous to rising

- Input in ODDEV+HSYNC or VSYNC + HSYNC or VSYNC slave modes

- Output in all other modes (master/slave)

- Synchronous to rising edge of CKREF

- Default polarity : negative pulse

I/O

Input : time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R

I/O

Rec601-2 and Rec656 (except for TTL input levels).Thisbus interfaceswith MPEG video

I/O

decoder output port and typically carries a stream of Cb,Y,Cr,Y digital video at CKREF

I/O

frequency, clocked on the rising edge (by default) of CKREF. A 54-Mbit/s ‘double’Cb, Y,

I/O

Cr, Y input multiplex is supported for double encoding application (rising and falling edge

I/O

of CKREF are operating). Output: for test purpose only. I/O I/O

CVBS must be connected to analog ground over a load resistor (R

Following the load resistor, a simple analog low pass filter is recommended CVBS

amplitude is proportional to I

511] V

OUT(Max.)

=1VPPand I

OUT(Max.)

REF(CVBS)(VOUT(N)

= 5mA

=NxR

LOADxIREF(CVBS)

LOAD

VR_CVBS must be connected to analog ground over a capacitor (6.8nF typ.),

VR_CVBS = 1.9V I/O Reference current source for the9-bit DAC CVBS.

-I

REF(CVBS)

-R

REF(CVBS)(Min.)

REF(CVBS)=VREF(CVBS)/RREF(CVBS)

must be biased to analog ground over a reference resistor R

= 5.95 x R

LOAD/VOUT(Max.)

with V

), V

REF(CVBS)(Typ.)

OUT(Max.)

= 1.12V.

=1VPPand I

OUT(Max.)

REF(CVBS)

I/O Reference current source for Tri-DAC R/Y,G/C,B/CVBS.

-I

REF(RGB)

-R (I

must be connected to analog groundover a reference resistor R

REF(RGB)(Min.) REF(RGB)=VREF(RGB)/RREF(RGB)

= 5.95 x R

LOAD/VOUT(Max.)

), V

REF(RGB)(Typ.)

, with V

OUT(Max.)

= 1.12V.

=1VPPand I

OUT(Max.)

VR_RGBmustbe biasedtoanalog ground overa typical 6.8nFcapacitor,VR_RGB = 1.9V.

This output must be connected to analogground over a load resistor(R Following the load resistor, a simple analog low pass filter is recommended. V

OUT(Max.)

with N = [0-511].

=1VPPand I

OUT(Max.)

= 5mA (V

OUT(N)

=NxR

LOADxIREF(RGB)

This output must be connected to analogground over a load resistor(R Following the load resistor, a simple analog low pass filter is recommended. V

OUT(Max.)

with N = [0-511].

=1VPPand I

OUT(Max.)

= 5mA (V

OUT(N)

=NxR

LOADxIREF(RGB)

This output must be connected to analogground over a load resistor(R Following the load resistor, a simple analog low pass filter is recommended. V

OUT(Max.)

with N = [0-511].

=1VPPand I

OUT(Max.)

= 5mA (V

OUT(N)

=NxR

LOADxIREF(RGB)

LOAD

/96)

LOAD

/96)

LOAD

/96)

Transport IC.

edge of CKREF signal average rate of6.9375Mbit/s. Output in test mode only.

/96) with N = [0-

= 5mA

REF(RGB)

= 5mA

4/42

II - PIN INFORMATION (continued) II.2 - Pin Description(continued)

Pin Name Type Function

24 CKREF I Master clock reference signal.

25 RESET I Hardware reset, active LOW.

26 SCL I I

27 SDA I/O I

28 VSYNC/

ODDEVEN

Its rising edge is the default reference for set-up and hold times of all inputs, and for propagation delay of alloutputs (exceptfor SDA output). CKREF nominal frequency is 27MHz (CCIR601) : input pad with pull down (50kΩ Typ.)

Ithas priorityoversoftware reset.NRESET imposesdefaultstates (seeRegisterContents). Minimum Low level required duration is 5 CKREF periods : input pad with pull down (50kΩ Typ.)

C bus clock line (internal 5-bit majority logic with CKREF forreference) : input pad with

pull down (50kΩTyp.)

C bus serial data line. Input : internal 5-bit majority logic with CKREF for reference Output : open drain

I/O Frame sync signal :

- input in slave modes, except when sync isextracted from YCrCb data

- output in mastermode and when sync is extracted from YCrCb data

- synchronous to rising edge of CKREF

- ODDEVEN default polarity :

odd (not-top) field : LOW level even (bottom) field : HIGH level

STV0118

III - BLOCK DIAGRAM

YCRCB7 YCRCB6 YCRCB5

YCRCB4 YCRCB3

YCRCB2 YCRCB1 YCRCB0

VSYNC/ODDEVEN

HSYNC

RESET

2 3 4 5 6 7 8 9

10V

1 25 24CKREF

TTXS/

TTXD

CSI2C

2223

TELETEXT

CB-CR

DEMULTIPLEXER

SYNC CONTROL & VIDEO TIMING

GENERATOR

CSI2C

TTXS

RGB ENCODING

PROCESSING

CHROMA

PROCESSOR

CSI2C

LUMA

CLOSED

CAPTIONS

CGMS

CTRL + CFG

SDA SCL

C BUS

AUTOTEST

COLOR BAR

PATTERN

TRAP

2627

SWITCH

STV0118

DDA

9-BIT TRIDAC

DDA

9-BIT

DAC

G/Y

R/C

B/CVBS

VR_RGB

REF(RGB)

SSA

DDA

CVBS

VR_CVBS

REF(CVBS)

SSA

0118-02.EPS

5/42

STV0118

IV- FUNCTIONALDESCRIPTION

The STV0118can operate either in mastermode, where it supplies all sync signals, or in 6 slave modes,where it locksonto incomingsync signals.

The main functions are controlledby a micro-controller via an I Register Description” for an exhaustivelist of the controlpossibilities available.

IV.1 - Data Input Format

The digital input is a time-multiplexed ITU-R656 /D1-type [Cb, Y, Cr, Y] 8-bit stream. Note that “ITU-R”was formerly knownas “CCIR”.Inputsamples are latched in on the rising edge (by default) of the clock signal CKREF, whose nominal frequencyis 27MHz.Figure1 illustratesthe expected datainput format. Alternatively,a 54-Mbit/sstream can be fed to the STV0118,refer to SectionIV.17 (“dualencoding”)for details.

The STV0118 is able to encode interlaced and non-interlacedvideo. One bit is sufficient to automaticallydirect the STV0118to process non-interlaced video. Update is performed internallyon the firstframesync activeedgefollowingthe programing of this bit. The non-interlaced mode is a 624/2= 312 linemode or a 524/2= 262line mode, whereall fieldsare identical.

An ‘autotest’ mode is available by setting 3 bits (sync[2:0]) within the configurations register0. Inthis mode,a color bar patternis produced,independentlyfrom video input, in the adequatestandard. As this mode sets the STV0118 in master mode, VSYNC/ODDEVand HSYNC pins are then in output mode.

IV.2 - Video Timing

TheSTV0118outputsinterlaced or non-interlaced video in PAL-B, D, G, H, I, PAL-N, PAL-M or NTSC-M standardsand ‘NTSC- 4.43’ is also possible.

The4-frame (for PAL)or 2 frame (for NTSC)burst sequences are internally generated, subcarrier generation being performed numerically with CKREF as reference. Rise and fall times of synchronizationtipsandburst enveloppeareinternally controlled according to the relevant ITU-R and SMPTErecommendations.

Figures2 to 7 depict typicalVBI waveforms. It is possibleto allow encodingof incomingYCrCb

dataon thoselines of the VBIthatdo not bearline sync pulses or pre/post-equalisation pulses (see Figures2 to 7). This mode of operation is refered to as “partial blanking” and is the default set-up. It

C 2-wire bus. Refer to the “User’s

allows to keep in the encoded waveform any VBI data present in digitized form in the incoming YCrCb stream (e.g. WSS data, VPS, supplementary Closed-Captions line or StarSightdata, etc.). Alternatively,thecompleteVBImaybe blanked(no incomingYCrCb data encodedonthese lines,“full blanking”).

ThecompleteVBIcomprisesof the followinglines:

- for 525/60systems (SMPTEline numberingconvention): lines1to 19andsecondhalf ofline263 to line 282.

- for 625/50 systems (CCIR line numbering convention) : second half of line 623 to line 22 and lines 311to 335.

The ‘partial’VBI consists of :

- for 525/60systems (SMPTEline numberingconvention): lines 1 to 9 and secondhalf of line263 to line 272.

- for 625/50 systems (CCIR line numbering convention): secondhalf ofline623toline 5andlines 311to 318.

Fullorpartialblankingiscontrolledby configuration bit ‘blkli in configurationregister1’.

Note that :

- line 282 in 525/60/SMPTEsystems is either fully blankedor fullyactive.

- line 23 in 625/60/CCIR systems is always fully active.

InanITU-R656-compliantdigitalTVline, theactive portion of the digital line is the portion included between the SAV (Start of Active Video) and EAV (End of Active Video) words. However,this digital active line starts somewhat earlier and may end slightlylater than the active line usually definedby analog standards. The STV0118 allows two approaches:

- It is possible to encode the full digital line (720 pixels/ 1440clockcycles).Inthiscase,theoutput waveform will reflect the full YCrCb stream included betweenSAV and EAV.

- Alternatively,it is possible to drop some YCrCb samples at the extremities of the digital line so that the encoded analog line fits within the ‘analog’ ITU-R/SMPTEspecifications.

Selection between these two modes of operation is performed with bit ‘aline’ in configuration register 4.

In all cases, the transitions between horizontal blankingand activevideo are shaped to avoid too steepedgeswithin theactive video. Figure8 gives timingsconcerning the horizontalblankinginterval and the active videointerval.

6/42

IV- FUNCTIONALDESCRIPTION(continued) Figure1 : Input Data Format

STV0118

4T4T

E A V

276T

Digital Standing Interval

(525 Line / 60Hz)

S A V

1716T

1440T

Digital Active LineNTSC, PAL M

Line Duration

PAL B, D, G, H, I, N

(625 Line / 50Hz)

288T

1728T

1440T

Figure2 : PAL-BDGHI, PAL-N TypicalVBI Waveform, Interlaced Mode (CCIR-625Line Numbering)

308 309 310 311 312 313 314 315 316 317 318 319 320

PartialVBI1

624 625 1 2 3 4 5 6 7 23621 622 623

Partial VBI2

Full VBI1

Full VBI2

E A V

0118-08.EPS

335

I, II, III, IV : A: B: C:

311 312 313 314 315 316 317 318 317 336308 309 310

62462512345678621 622 623

Frame synchronizationreference

and 5th,2ndand6th,3rdand 7th,4thand 8thfields Burst phase : nominal value +135° Burst phase : nominal value -135° Burst suppressioninternal

III

Figure3 : PAL-BDGHI,PAL-NTypicalVBI Waveform,Non-interlacedMode (“CCIR-like” LineNumbering)

Full VBI

7/42

Burst phase togglesevery line

31131212345678308 309 310

PartialVBI

0118-09.EPS

0118-10.EPS

STV0118

IV- FUNCTIONALDESCRIPTION(continued) Figure4 : NTSC-MTypicalVBI Waveforms,InterlacedMode (SMPTE-525Line Numbering)

Partial VBI1

45678910 1819

Full VBI1

Partial VBI2

Full VBI2

HH0.5H

VBI3

12345678910 1819525

VBI4

H0.5HHH

282273272271270269268267266265264263262

282273272271270269268267266265264263

Figure5 : NTSC-MTypicalVBI Waveforms,Non-interlacedMode (“SMPTE-like” LineNumbering)

Full VBI

PartialVBI

262

233H4563H7893H10 18 19

H0.5HHH

0118-11.EPS

0118-12.EPS

8/42

IV- FUNCTIONALDESCRIPTION(continued) Figure6 : PAL-MTypical VBI Waveforms,Interlaced Mode(CCIR-525 Line Numbering)

F’

PartialVBI1

FullVBI1

STV0118

519F520F’521F522 523 524 525 1 2 3 4 5 6 7 8 9

257F’258F259 260

519F’520F521 522

F’

257F258 259 260

0V:

Framesynchronizationreference

I, II, III, IV :

1stand5th,2ndand6th,3rdand7th,4thand8thfields

Burstphase: nominalvalue +135°

Burstphase: nominalvalue -135°

Burstsuppressioninternal

261 262 263 264 265 266 267 268 269 270 271 280

523 524 525 1 2 3 4 5 6 7 8 9

261 262 263 264 265 266 267 268 269 270 271 272

PartialVBI2

III

FullVBI2

Figure7 : PAL-MTypical VBI Waveforms,Non-interlacedMode (“CCIR-like” Line Numbering)

Partial VBI

Full VBI

16 17

279

0118-13.EPS

256257258259260261262123456789

Burstphase toggles every line

10 16 17

0118-14.EPS

9/42

STV0118

IV- FUNCTIONALDESCRIPTION(continued) Figure8 : HorizontalBlanking Intervaland Active Video Timings

(bit”aline” = 0)

c1 c2 (bit ”aline” = 1)

Full Digital Line Encoding

(720Pixels - 1440T)

”Analog” Line Encoding

(710Pixels - 1420T)

NTSC-M

5.38µs(even lines)

5.52µs(odd lines)

Actual values will depend on the static offset programmed for subcarrier generation.

c1 c2

1.56µs

8.8µs

9.3µs

9 Cyclesof 3.58MHz

PAL-BDGHI

5.54µs(A-type)

5.66µs(B-type) Theseare typical values.

1.28µs

9.3µs

10.1µs

10 Cyclesof 4.43MHz

IV.3 - Reset Procedure

Ahardwarereset is performedbygroundingthepin NRESET. The master clock must be running and pin NRESET kept low for a minimum of 5 clock cycles.This setsthe STV0118in HSYNC+ODDEV (line-locked) slave mode, for NTSC-M, interlaced ITU-R601 encodin g. Closed-captioning and Teletextencodingare all disabled.

Then the configuration can be customized by writing into the appropriateregisters. A few registers

PAL-N

5.54µs(A-type)

5.66µs(B-type)

1.28µs

9.3µs

10.1µs

9 Cyclesof 3.58MHz

PAL-M

5.73µs(A-type)

5.87µs(B-type)

1.28µs

9.3µs

10.1µs

9 Cyclesof 3.58MHz

are neverreset, their contentsis unknownuntilthe first loading (refer to the Register Contents and Description).

It is also possible to perform a software reset by settingbit’softreset’in Reg6. The IC’s response in that caseis similarto itsresponseafter a hardware reset, except that Configuration Registers (Reg0 to6) anda fewotherregisters(seedescription of bit‘softreset’)are not altered .

0118-15.EPS

10/42

STV0118

IV- FUNCTIONALDESCRIPTION(continued) IV.4 - Master Mode

In this mode, the STV0118 supplies HSYNC and ODDEVsyncsignals(withindependentlyprogrammable polarities) to drive other blocks. Refer to Figure9 and 10 for timings and waveforms.

The STV0118 starts encoding and counting clock Figure9 : ODDEVEN,VSYNC and HSYNC Waveforms

Active edge (programmable polarity)

ODDEVEN

(see Note 1)

Active edge (programmable polarity)

VSYNC

Active edge (programmable polarity)

HSYNC

(see Note 2)

Line Numbers :

SMPTE-525

CCIR-62541

Notes : 1. When ODDEVEN is a sync input, only one edge (“the active edge”) of the incoming ODDEVEN is taken into account for

synchronization. The “non-active” edge (2nd edge on this drawing) is not critical and its positionmaydiffer by H/2 from the location shown.

2. The HSYNC pulse width indicated is valid when the STV0118 supplies HSYNC.In those slave modes where it receives HSYNC, only the edge defined as active is relevant, and the width of the HSYNC pulse it receives is not critical.

128 T

5 2

6 3

ckref

= 4.74µs

cycles as soon as the master mode has been loadedinto the control register (Reg.0).

Configurationbits“Syncout_ad[1:0]”(Reg4)allowto shift the relative position of the syncsignals by up to 3 clockcyclesto cope with any YCrCb phasing.

266 313

267 314

268 315

269 316

0118-16.EPS

Figure10 : MasterMode Sync Signals

CKREF

ODDEVEN

(out)

HSYNC

(out)

YCRCB

Note : 1. This figureis valid for bits “syncout_ad[1:0]” = default.

Active Edge (programmable polarity)

CKREF

Cr Y’

Active Edge (programmable polarity)

Cb Y Cr Y’

Duration of HSYNC Pulse: 128 T

CKREF

0118-17.EPS

11/42

STV0118

IV- FUNCTIONALDESCRIPTION(continued) IV.5 - Slave Modes

Six slave modes are available : ODDEV+HSYNC based (line-based sync), VSYNC+HSYNC based (another type of line-based sync), ODDEV-only based (frame-based sync), VSYNC-only based (another type of frame-based sync), or sync-indatabased (line locked or frame locked).

ODDEV refers to an odd/even (also known as not-top/bottom) field flag, HSYNC is a line sync signal,VSYNCis averticalsync signal.Theirwaveforms are depicted in Figure 9. The polarities of HSYNC and VSYNC/ODDEV are independently programmablein all slave modes.

IV.5.1- Synchronizationontoa Line SyncSignal IV.5.1.1- HSYNC+ODDEV BasedSynchronization

Synchronizationis performedon a line-by-linebasis by locking onto incoming ODDEV and HSYNC signals. Refer to Figure 11 for waveforms and timings. The polarities of the active edges of HSYNCand ODDEVare programmableandindependent.

Thefirstactiveedge of ODDEVinitializesthe internal line counter but encoding of the first line does not start until an HSYNC active edge is detected (atthe earliest,HSYNC maytransitionat thesame timeas ODDEV).At thatpoint, the internalsample counter is initialized and encoding of the first line starts. Then, encoding of each subsequent line is individuallytriggeredby HSYNCactive edges.The phase relationship between HSYNC and the incoming YCrCB data is normally such that the first clockrising edgefollowingthe HSYNCactiveedge samples “Cb” (i.e. a ‘blue’ chroma sample within theYCrCb stream). It is however possible to internally delay the incoming sync signals (HSYNC+ODDEV) by up to 3 clock cycles to cope withdifferentdata/syncphasings,using configurationbits “Syncin_ad” (Reg. 4).

Figure11 : HSYNC+ ODDEVENBased SlaveMode Sync Signals

The STV0118 is thus fully slaved to the HSYNC signal, which means that lines may contain more or less samples than typical 525/625 system requirement.

If the digital line is shorter than its nominal value: the samplecounteris re-initializedwhen the ‘early’ HSYNC arrives and all internal synchronization signals are re-initialized.

If the digital line is longer than its nominal value : the sample counter is stoppedwhen it reachesits nominal end-of-line value and waits for the ‘late’ HSYNCbefore reinitializing.

The field counteris incrementedon each ODDEV transition.The linecounteris reseton theHSYNC followingeach active edge of ODDEV.

IV.5.1. 2- HSYNC + VSYNC BasedSynchron ization

Synchronizationis performed on a line-by-line basis by locking onto incoming VSYNC and HSYNC signals. Refer to Figure 12 for waveforms and timings. The polaritiesof HSYNC and VSYNC are programmableand independent.

The incomingVSYNC signal is immediately transformed into a waveformidentical to the odd/even waveform of an ODDEVsignal, therefore the behavior of the core is identical to that described above for ODDEV+HSYNC based synchronization. Again, the p hase relationship between HSYNC and the incoming YCrCb data is normally such that the first clock rising edge following the HSYNC active edge samples “Cb” (i.e. a ‘blue’ chroma sample within the YCrCb stream). It is however possible to internally delay the incoming sync signals (HSYNC+VSYNC) by up to 3 clock cycles to cope with different data/sync phasings, using configurationbits “Syncin_ad”(Reg. 4).

The field counter is incremented on each active edge of VSYNC.

CKREF

ActiveEdge (programmablepolarity)

ODDEVEN

(in)

HSYNC

(in)

YCRCB

Note : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

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ActiveEdge (programmablepolarity)

Cb Y Cr Y’ Cb

0118-18.EPS

IV- FUNCTIONALDESCRIPTION(continued) Figure12 : HSYNC + VSYNC Based Slave Mode SyncSignals

CKREF

Active Edge (programmablepolarity)

VSYNC

(in)

Active Edge (programmablepolarity)

HSYNC

(in)

STV0118

YCRCB Cb Y Cr Y’ Cb

Notes : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

2. The active edges of HSYNC and VSYNC should normally be simultaneous. Itis permissible that HSYNC transitions before VSYNC, but VSYNC must not transition before HSYNC.

Figure13 : ODDEVENBasedSlave Mode Sync Signals

CKREF

Active Edge (programmable polarity)

ODDEVEN

(in)

YCRCB

Note : 1. Thisfigure is valid for bits “syncin_ad[1:0]” = default.

IV .5 .2-Synchro niz a tio nontoa FrameSyncSignal IV.5.2.1 - ODDEV-only Based Synchronization

Synchronizationis performedon a frame-by-frame basis by locking onto an incoming ODDEV signal. A line sync signal is derived internally and is also output as HSYNC. Refer to Figure 13 for waveformsandtimings.Thephaserelationshipbetween ODDEVand the incomingYCrCB data is normally such that the first clock rising edge following the ODDEV active edge samples “Cb” (i.e. a ‘blue’ chroma sample within the YCrCb stream). It is however possible to internally delay the incoming ODDEVsignalby up to3 clock cyclesto copewith different data/sync phasings, using configuration bits“Syncin_ad” (Reg. 4).

Thefirst active edgeofODDEVtriggersgeneration of the analog sync signals and encoding of the incomingvideo data.Framesbeingsupposedtobe of constantduration, the next ODDEVactive transition is expected at a precise time after the last ODDEVdetected.

So, once an active ODDEV edge has been detected, checks that the following ODDEV are present at the expected instants are performed.

Cb Y Cr Y’ Cb

Encodingand analogsync generationcarryon unlessthreesuccessivefailsof thesechecksoccur.

In that case,threebehaviorsare possible,according to the configurationprogrammed (Reg. 1-2) :

- if ‘free-run’ is enabled, the STV0118 carries on outputtingthe digitalline sync HSYNCand generating analog video just as though the expected ODDEV edge had been present. However, it will re-synchronizeontothe nextODDEVactiveedge detected,whateverits location.

- if ‘free-run’ is disabled but bit ‘sync_ok’ is set in configuration register1, the STV0118 sets the active portion of the TV line to black level but carrieson outputtingthe analogsync tips (on Ys and CVBS) and the digital line sync signal HSYNC.

- if ‘free-run’is disabledand the bit ‘sync_ok’is not set, allanalog videois at blacklevel andneither analog sync tips nor digital linesync are output.

Note that this mode is a frame-based sync mode, asopposedtoa field-basedsyncmode,thatis,only one type of edge (rising or falling, according to bit ‘polv’in Reg 0) is of interest to the STV0118,the other one is ignored.

0118-19.EPS

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