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■ SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V
■ TYPICAL PEAK OUTPUT CURRENT:
SOURCE -2A, SINK 3.5A
■ OPERATING FREQUENCY: 20 TO 750 KHZ
■ SMART TURN-OFF ANTICIPATION TIMING
■ OPERATION INDEPENDENT FROM THE
FORWARD MAGNETIC RESET TECHNIQUE
■ POSSIBILITY TO OPERATE IN
DISCONTINUOUS MODE
STSR2
FORWARD SYNCHRONOUS
RECTIFIERS SMART DRIVER
SO-8
DESCRIPTION
STSR2 Smart Driver IC provides two
complementary high current outputs to drive
Power Mosfets. The IC is dedicated to properly
drive secondary Synchronous Rectifiers in
medium power, low output voltage, high efficiency
Forward Conv erte rs. From a synchronizing clock
input, STSR2 generates two driving signals with
the self-setting of dead time between
complementary pulses. The IC operation prevents
secondary side shoot-through conditions
providing proper timing at the outputs turn-off
transition. This smart function operates through a
fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator,
synchronized by the clock signal. A fixed
anticipation in turning-off the OU T
GATE1
with
respect to the c lock signal transition is provided,
SCHEMATIC DIAGRAM
while the anticipation in turning off the OUT
can be set through external components. The
adopted transitions revelation mechanism makes
circuit operation ind ependent by the forward
magnetic reset tec hnique used, avoiding most of
the common problems inherent in self-driven
synchronous rectifiers. A special Inhibit function
allows the shut-off of OUT
GATE2
makes discontinuous conduction m ode possible
and prevents the freewheeling mosfet from
sinking current from the output.
STSR2 automatically turns off the outputs when
duty-cycle is lower than 13%, while STSR2M
works even at v ery low duty-cycle values.
Vcc
2
BIAS
UVLO
+
5.7V
GATE2
. This feature
CK
INHIBIT
PEAK
4
DETECTOR
+
HIGH
5
FREQUENCY
OSCILLATOR
+
25mV
DIGITAL
CONTROL
6
SGLGND
ANTICIPATION
SET
OUTPUT
BUFFERS
8
PWRGND
+
SETANT2
3
1 OUTGate1
OUTGate2
7
1/12June 2003
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STSR2
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
OUTGATE
V
INHIBIT
V
I
LX
P
TOT
ESD Human Body Model Pins 1,2, 4, 5, 6, 7, 8 ±1KV
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum
THERMAL DATA
Symbol Parameter SO-8 Unit
R
thj-amb
R
thj-amb
(*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 °C/W can be
obtained improving thermal conductivity of the board
DC Input Voltage
CC
Max Gate Drive Output Voltage -0.3 to V
Max INHIBIT Voltage (*) -0.6 to V
Clock Input Voltage Range (*) -0.3 to V
CK
Switching Peak Current
-0.3 to 6 V
CC
CC
CC
2A
Continuous Power Dissipation at TA=105°C without heatsink 270 mW
Pin 3 ±0.9 KV
Storage Temperature Range
stg
Operating Junction Temperature Range -40 to +125 °C
op
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient (*)
-55 to +150 °C
40 °C/W
160 °C/W
V
V
V
ORDERING CODES
TYPE SO-8 SO-8 (T&R)
STSR2 STSR2CD STSR2CD-TR
STSR2M STSR2MCD STSR2MCD-TR
CONNECTION DIAGRAM (top view)
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PIN DESCRIPTION
Pin N° Symbol Name and Function
1OUT
2V
3 SET
GATE1
CC
ANT2
4 CK This input provides synchronization for IC’s operations, being the transitions
5 INHIBIT This input enables OUT
6 SGLGND Reference for all the control logic signals. This pin is completely separated from
7OUT
GATE2
8 PWRGND Reference for power signals, this pin carries the full peak currents for the two
Gate Drive signal for Rectifier MOSFET. Anticipation (t
OUT
is provided when the clock input goes to low level.
GATE1
The supply voltage range from 4.5V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.
The voltage on this pin sets the anticipation (t
is possible to choose among three different anticipation times by discrete
partitioning of the supply voltage.
between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual
shoot-through situation on secondary side at both transitions. Smart clock
revelation mechanism makes these operations independent by false triggering
pulses generated in light load conditions and by particular demagnetization
techniques.Absolute maximum voltage rating of the pin can be exceeded limiting
the current flowing into the pin to 10mA max.
to work when its voltage is lower than the negative
threshold voltage (V
minimum conduction time (t
GATE2
INHIBIT<VH
ON(GATE2)
). If V
INHIBIT>VH
). In typical forward converter application, it
is possible to turn off the freewheeling MOSFET when the current through it tends
to reverse, allowing discontinuous conduction mode and providing protection to
the converter from eventual sinking current from the load.Absolute maximum
voltage rating of the pin can be exceeded limiting the current flowing into the pin
to 10mA max.
the PWRGND to prevent eventual disturbances to affect the control logic.
Gate Drive signal for Freewheeling MOSFET. Anticipation [t
OUT
is provided when the clock input goes to high level.
GATE2
outputs.
) in turning off
ANT1
) in turning off the OUT
ANT1
the OUT
GATE2
ANT2
STSR2
GATE2
will be high for a
] in turning off
.It
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STSR2
ELECTRICAL CHARACTERISTICS(VCC=5V, CK= 250kHz, V
INHIBIT
=-200mV, TJ=-40 to 125°C, unless
otherwise specified.)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT
V
CCON
V
CCOFF
V
I
GATE DRIVER OUTPUTS
V
V
I
OUT
R
OUT
t
t
TURN-OFF ANTICIPATION TIME
t
ANT1
t
ANT2
I
SETANT2
INHIBIT OUT
V
t
ON(GATE2)
V
I
D
t
PW
Note1:tRis measured between 10% and 90% of the final voltage; tFis measuredbetween 90%and 10% on theinitialvoltage
Note2: Parameter guaranteed by design
Start Threshold 3.8 4 V
Turn OFF Threshold After
3.5 3.6 V
Start
Zener Voltage CK=0V IZ= 2mA 5.5 5.8 6 V
Z
Unloaded Supply Current OUT
CC
Output Low Voltage I
OL
Output High Voltage I
OH
Output Source Peak
CK=0V OUT
OUTGATE1,2
OUTGATE1,2
= no load 22 30 mA
GATE1,2
= no load 3 5
GATE1,2
=-200mA 0.10 0.16 V
=200mA 4.70 4.85 V
2A
Current
Output Sink Peak Current 3.5
Output Series Source
Resistance
Output Series Sink
Resistance
OUT
t
R
t
F
P1
P2
GATE1,2
OUT
GATE1,2
Clock Propagation Delay to
Turn ON of OUT
Clock Propagation Delay to
Turn ON of OUT
OUT
GATE1
Rise Time C
Fall Time C
GATE1
GATE2
Turn-off
I
OUTGATE1,2
I
OUTGATE1,2
LOAD
LOAD
=-200mA 0.75 1.5 Ω
=200mA 0.5 0.8
=5nF (Note 1) 40 ns
=5nF (Note 1) 30 ns
No Load 130 ns
No Load 50 ns
No Load 20 ns
Anticipation Time
OUT
Anticipation Time
GATE2
Turn-off
V
= 0 to 1/3VCC; no load 75 ns
ANT2
=1/3VCCto 2/3VCC; no load 150
V
ANT2
=2/3VCCto VCC; no load 225
V
ANT2
Leakage Current (Note 2) -0.1 0.1 µA
ENABLE
GATE2
Threshold Voltage TJ= 25°C -30 -25 mV
H
Leakage Current (Note 2) V
I
H
OUT
GATE1
Turn-off
V
V
= 200mV -400 nA
INHIBIT
= -200mV 1 µA
INHIBIT
= 200mVNo Load 250 ns
INHIBIT
Anticipation Time
Reference Voltage TJ= 25°C 2.6 2.8 V
CK
LX Leakage Current 600 µA
CK
Duty Cycle Shut Down TJ= 25°C for STSR2 13 14 %
OFF
Duty Cycle Turn ON after
Shut Down
T
= 25°C for STSR2 18 20
J
Minimum Pulse Width STSR2M 200 ns
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