STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ BATTERY MANAGEMENT IN NOMADIC
EQUIPMENT
■ POWER MANAGEMENT IN CELLULAR
PHONES
SO-8
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
DS
V
DGR
V
GS
I
D
(
I
DM
P
tot
(
Puls e width limit ed by safe opera ti ng are a.Note: F or t he P- CHA NNE L MOS FE T ac tu al po la rity o f v olt ages a nd
•)
.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage± 16V
Drain Current (continuos) at TC = 25°C Single Operation
Drain Current (continuos) at T
•)
Drain Current (pulsed)16A
Total Dissipation at TC = 25°C Dual Operation
Information furnished is believed to be accurate an d rel i able. However, STMicroelectro ni cs assumes no responsibility for the consequen ces
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent ri ghts of STM i croelectr onics. Sp ecifications mentioned in thi s publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approv al of STMicroel ectronics.
The ST log o i s registered trademark of STMicroelectronics
2002 STMi croelectronics - All Ri ghts Rese rved
All other names are the property of their respective ow ners.
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8/8
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