STQ1NE10L
N-CHANNEL 100V - 0.3 Ω - 1A TO-92
STripFET™ POWER MOSFET
TYPE
V
DSS
STQ1NE10L 100 V <0.4
■ TYPICAL R
■ EXCEPTIONA L HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ AVALANCHE RUGGED TECHNOLOGY
■ LOW THRESHOLD DRIVE
(on) = 0.3 Ω
DS
R
DS(on)
I
D
Ω
1 A
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ DC MOTOR CONTROL (DISK DRIVES, etc.)
■ DC-DC & DC-AC CONVERTERS
■ SYNCHRONOUS RECTIFICATION
TO-92
TO-92
(Ammopack)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
(
I
DM
(1)
P
tot
dv/dt
E
AS
T
stg
T
j
(
Pulse widt h l i m i ted by safe operating area.
•)
(1)
Related to Rthj -l
.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
100 V
100 V
Gate- source Voltage ± 16 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
•)
Drain Current (pulsed) 4 A
Total Dissipation at TC = 25°C
1A
0.6 A
3W
Derating Factor 0.025 W/°C
(2)
Peak Diode Recovery voltage slope 6 V/ns
(3)
Single Pulse Avalanche Energy 400 mJ
Storage Temperature
Operating Junction Temperature °C
(2) ISD ≤1A, di/dt ≤200A/ µ s , VDD ≤ V
(3) Starting Tj = 25 oC, ID = 1A, VDD = 50V
-55 to 150
(BR)DSS
, Tj ≤ T
°C
JMAX
1/9December 2002
STQ1NE10L
THERMA L D ATA
Rthj-
Lead
Rthj-amb
T
l
Thermal Resistance Junction-Lead
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
40
125
260
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C unless otherwise specified)
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 250 µA, VGS = 0
V
(BR)DSS
Drain-source
I
D
100 V
Breakdown Voltage
V
= Max Rating
DS
V
= Max Rating TC = 125°C
DS
V
= ± 16 V
GS
1
10
±100 nA
ON
(*)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
V
= V
DS
GS
= 10 V ID = 0.5 A
V
GS
= 5 V ID = 0.5 A
V
GS
ID = 250 µA
1 2.5 V
0.30
0.35
0.40
0.45
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 15V ID = 0.5 A
DS
= 25V f = 1 MHz VGS = 0
V
DS
2S
345
45
20
µA
µA
Ω
Ω
pF
pF
pF
2/9
STQ1NE10L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 50 V ID = 0.5 A
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %.
(
•)Pulse width limited by s afe operating area.
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
V
DD
= 4.7
R
Ω
G
VGS = 10 V
(Resistive Load, Figure 3)
= 80 V ID= 1 A VGS= 5 V
V
DD
= 50 V ID = 0.5 A
V
DD
= 4.7Ω, V
R
G
GS
= 5 V
(Resistive Load, Figure 3)
I
= 1 A VGS = 0
SD
I
= 1 A di/dt = 100A/µs
SD
= 30 V Tj = 150°C
V
DD
(see test circuit, Figure 5)
11
12
7
1.5
3.5
20
13
1
4
1.5 V
52
90
3.5
ns
ns
nC
nC
nC
ns
ns
A
A
ns
nC
A
Saf e Operating Area
Thermal Impedance Junction-lead
3/9
STQ1NE10L
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
4/9
STQ1NE10L
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics .
. .
5/9
STQ1NE10L
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Induct ive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/9
TO-92 MECHANICAL DATA
STQ1NE10L
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.58 5.33 0.180 0.210
B 4.45 5.2 0.175 0.204
C 3.2 4.2 0.126 0.165
D 12.7 0.500
E1.27 0.050
F 0.4 0.51 0.016 0.020
G0.35 0.14
mm inch
7/9
STQ1NE10L
8/9
STQ1NE10L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroe l ectronics.
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