SGS Thomson Microelectronics STP5NK65Z Datasheet
1/9April 2002
STP5NK65Z
N-CHANNEL 650V - 1.5Ω - 5A TO-220
Zener-Protected SuperMESH™Power MOSFET
■ TYPICAL R
DS
(on) = 1.5 Ω
■ EXTREMELY HIGH dv /d t C APABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPAC ITANCES
■ VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST ’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the
most demanding applications. Such s eries com pl ements ST full range of high voltage MOSFE Ts including revolutionary MDmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SU PPLIES,
ADAPTORS AND PFC
ORDERING INFORMATION
TYPE V
DSS
R
DS(on)
I
D
Pw
STP5NK65Z 650 V < 1.8 Ω 5 A 85 W
SALES TYPE MARKING PACKAGE PACKAGING
STP5NK65Z P5NK65Z TO-220 TUBE
TO-220
INTERNAL SCHEMATIC DIAGRAM
STP5NK65Z
2/9
ABSOLUTE MAXIMUM RATINGS
(l) Pulse wi dth limited by saf e operating ar ea
(1) I
SD
≤ 5A, di/dt ≤100 µA, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX.
(*) Limited only by maximum temperature allowed
THERMA L D ATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and costeffective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage
of external components.
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
650 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
650 V
V
GS
Gate- source Voltage ± 30 V
I
D
Drain Current (continuous) at TC = 25°C
5A
I
D
Drain Current (continuous) at TC = 100°C
3.1 A
I
DM
(l)
Drain Current (pulsed) 20 A
P
TOT
Total Dissipation at TC = 25°C
85 W
Derating Factor 0.6 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 2000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
-55 to 150
°C
°C
Rthj-case Thermal Resistance Junction-case Max 1.64 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 50 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
4.2 A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, ID = IAR, VDD = 50 V)
190 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs=± 1mA (Open Drain) 30 V
3/9
STP5NK65Z
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
ON/OFF
DYNAMIC
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pu l se duration = 300 µ s, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when VDS increase s fr om 0 to 80%
V
DSS
.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
ID = 1 mA, VGS = 0 650 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
VDS = Max Rating, TC = 125 °C
1
50
µA
µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ± 20V ±10 µA
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 50µA
3 3.75 4.5 V
R
DS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 2.1 A 1.5 1.8 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance VDS = 10 V, ID= 2.1 A 5 S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, VGS = 0 680
80
17
pF
pF
pF
C
oss eq.
(3) Equivalent Output
Capacitance
VGS = 0V, VDS = 0V to 480 V 98 pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
VDD = 325 V, ID = 2.1 A
RG= 4.7Ω VGS = 10 V
(Resistive Load see, Figure 3)
20
15
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 520V, ID = 4.2 A,
VGS = 10V
25
4.4
13.7
35
nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
VDD = 325 V, ID = 2.1 A
RG=4.7Ω VGS = 10 V
(Resistive Load see, Figure 3)
140
40
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 520 V, ID = 4.2 A,
RG=4.7Ω, V
GS
= 10V
(Inductive Load see, Figure 5)
12
7
15
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
5
20
A
A
VSD (1)
Forward On Voltage
ISD = 5 A, VGS = 0
1.6 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 4.2 A, di/dt = 100A/µs
V
DD
= 100V, Tj = 150°C
(see test circuit, Figure 5)
375
1.76
10
ns
µC
A
Loading...