N-CH A NNEL 900V - 3.2Ω - 3.5A TO-220/TO-220FP/I2PAK
Zener-Protected PowerMESH™III MOSFET
TYPEV
DSS
STP3NC90Z/FP900V< 3.5
STB3NC90Z-1900V< 3.5
■ TYPICAL R
■ EXTREMELY HIGH d v/dt AND CAPA BILITY GATE
(on) = 3.2Ω
DS
R
DS(on)
I
D
Ω
Ω
3.5 A
3.5 A
TO - SOURCE ZENER DIODES
■ 100% AVALANCHE TESTED
■ VERY LOW GATE INPUT RESISTANCE
■ GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH OVERLAY™ Power
MOSFETs for very high voltage exhibits unsurpassed
on-resistance per unit area while integrating back-toback Zener diodes between gate and source. Such arrangement gives extra ESD capability with higher ruggedness performance as request ed b y a l arge variety
of single-switch applications.
APPLICATIONS
■ SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
■ WELDING EQUIPMENT
TO-220
3
2
1
I2PAK
(Tabless TO-220)
TO-220FP
1
3
2
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
STP(B)3NC90Z(-1) STP3NC90ZFP
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
I
GS
V
ESD(G-S)
dv/dtPeak Diode Recovery voltage slope3V/ns
V
ISO
T
stg
T
j
(•)Pu l se width limited by safe operati ng area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
900V
900V
Gate- source Voltage± 25V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(●)
Drain Current (pulsed)1414A
Total Dissipation at TC = 25°C
3.53.5(*)A
2.22.2(*)A
10035W
Derating Factor0.80.28W/°C
Gate-source Current (*)±50mA
Gate source ESD(HBM-C=100pF, R=15K
Ω)
2.5KV
Insulation Withstand Voltage (DC)--2000V
Storage Temperature–65 to 150°C
Max. Operating Junction Temperature150°C
VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
28ns
14ns
2738nC
16ns
1.6V
712ns
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)25V
Voltage
α
TVoltage Thermal CoefficientT=25°C Note(3)1.3
I
RzDynamic Resistance
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area .
3.∆V
= αT (25°-T) BV
BV
GSO
(25°)
= 50 mA
D
90
10
-4
/°C
Ω
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally
be applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient
and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid
the usage of external components.
3/11
STP3NC90Z/FP/STB3NC90Z-1
Safe Operating Area For TO-220FPSafe Operating Area For TO-220 / I²PAK
Thermal Impedance For TO-220 / I²PAK
Output Characteristics
Thermal Impedance For TO-220FP
Transfer Characteristics
4/11
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