SGS Thomson Microelectronics STLVD112CTR, STLVD112BTR Datasheet
HIGH SPEED PROTECTION SWITCH
■ 24mA CMOS OUTPUT DRIV E CURRENT
■ LVTTL INPUT THRESHOLDS
■ CONTROLLEDSKEW BETWEEN DATA AND
CLOCK SIGNALS
■ LVDS INPUT-OUTPUT UP TO 155 MHZ
■ IMPROVED LATCH-UP IMMUNITY UP TO
300mA
DESCRIPTION
The STLVD112 is a low voltage differential to
LVTTL signal converter with enhanced l oop-back
and crosspoint features. The synchronous design
allows a phase alignment between a clock and its
data; this means a better BER (Bit Error Rate)
performance.
The advanced 0.35µm tec hnology makes the
STLVD112 suitable for data rates up to 200Mbit.
The main application field is SDH/SONE T telecom
infrastructure. The STLVD112 flexible switch
architecture makes it eas y to implement multiple
protection schemes in STM1 access systems.
Thanks to the flexibl e multiplexing allowed, it
becomes simple to redirect the data/c lock signal
coming from the faulty access card to the spare
card. In normal mode the STLVD11 2 c onv ert s the
differential data levels of the LVDS and related
STLVD112
TSSOP
clock s ignal from (to) the line interface in LVTTL
level signals to (from) the backpanel. In addition
the switch functions prevent the equipment from
line interface faults. In fact, it is possible to switch
the signals coming from a different line interface to
the local line interface or the signals from the loca l
line interface to a different line interface.
ORDERING CODES
Type
STLVD112BTR -40 to 85 °C TSSOP48 (Tape & Reel) 1000 parts per reel
STLVD112CTR 0 to 70 °C TSSOP48 (Tape & Reel) 1000 parts per reel
Temperature
Range
Package Comments
1/11April 2003
STLVD112
PIN CONFIGURATION
2/11
PIN DESCRIPTION
PlN N° SYMBOL NAME AND FUNCTION
1, 6, 14, 22 VS1 Main Power Supply
2 CKsp_in LVTTL Clock Input
3 DATAsp_in LVTTL Data Input
4, 9, 13, 17, 21,
25, 36, 44, 48
5 LOSch Control Output
7 CKsp_out LVTTL Clock Output
8 DATAsp_out LVTTL Data Output
10, 18, 31, 38 VS2 Second Power Supply
11 CKch_in LVTTL Clock Input
12 DATAch_in LVTTL Data Input
15 CKprev_in LVTTL Clock Input
16 DATAprev_in LVTTL Data Input
19 CKch_out LVTTL Clock Output
20 DATAch_out LVTTL Data Output
23 CKprev_out LVTTL Clock Output
24 DATAprev_out LVTTL Data Output
26, 30, 37, 43 N.C. Not Connected
27 Kloop_sp Control Input
28 Kloop_I Control Input
29 Ki Control Input
32 DATAinB LVDS Data Input 33 DATAinA LVDS Data Input +
34 CKinB LVDS Clock Input 35 CKinA LVDS Clock Input +
39 CKoutB LVDS Clock Output 40 CKoutA LVDS Clock Output +
41 DATAoutB LVDS Data Output 42 DATAoutA LVDS Data Output +
45 LOSsp Control Output
46 LOSi Control Input
47 LOSprev Control Input
GND
Ground
STLVD112
TRUTH TABLES FOR THE FIVE MUX
INPUTS OUTPUT
Ki Kloop_sp Kloop_i DATA_out
LOW X X DATAch_in
HIGH X X DATAsp_in
INPUTS OUTPUT
Ki Kloop_sp Kloop_i DATAch_out
X X LOW DATAin
X X HIGH DATAch-in
3/11
STLVD112
INPUTS OUTPUT
Ki Kloop_sp Kloop_i DATAsp_out
LOW LOW X DATAprev_in
HIGH LOW X DATA_in
X HIGH X DATAsp_in
INPUTS OUTPUT
Ki Kloop_sp Kloop_i LOSch
X X LOW LOSi
X X HIGH LOW
INPUTS OUTPUT
Ki Kloop_sp Kloop_i LOSsp
LOW LOW X LOSprev
HIGH LOW X LOSi
X HIGH X LOW
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VS1, VS2 Supply Voltage
VS2 Supply Voltage
V
V
DC Input Voltage
I
DC Output Voltage
O
Iik DC Input Diode Clamp Current ±20 mA
Iok DC Output Diode Clamp Current ±20 mA
I
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
DC Output Current
O
Lead Temperature (10sec)
L
Storage Temperature Range
stg
-0.3 to 4.6 V
-0.3 to (VS1 + 0.3) V
-0.3 to (VS1 + 0.3) V
-0.3 to (VS1 + 0.3) V
±50 mA
300 °C
-65 to 150 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
VS1, VS2 Supply Voltage
VS2 Supply Voltage
V
V
DC Input Voltage
I
DC Output Voltage
O
Top Operating Temperature -45 to 85 °C
dt/dv Maximum Input Rise and Fall Time 10 ns/V
4/11
3 to 3.6 V
3 to (VS1 + 0.3) V
0 to VS1 V
0 to VS1 V
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