SGS Thomson Microelectronics STLC60134S Datasheet
TOSCA INTEGRATEDADSL CMOS
FULLY INTEGRATEDAFEFORADSL
OVERALL 12 BIT RESOLUTION, 1.1MHz
SIGNAL BANDWIDTH
8.8MS/sADC
8.8MS/sDAC
THD: -60dB @FULL SCALE
4-BIT DIGITAL INTERFACE TO/FROM THE
DMT MODEM
1V FULL SCALEINPUT
DIFFERENTIAL ANALOGI/O
ACCURATE CONTINUOUS-TIME CHANNEL
FILTERING
3rd & 4th ORDER TUNABLE CONTINUOUS
TIME LP FILTERS
0.5 WATTAT 3.3V
0.5µm HCMOS5 LA TECHNOLOGY
64 PIN TQFP PACKAGE
DESCRIPTION
STLC60134S is the Analog Front End of the
STMicroelectronics Tosca ADSL chipset and
when coupled with STLC60135 (DTM modem)al-
Figure 1. Block Diagram
STLC60134S
ANALOG FRONT-ENDCIRCUIT
TQFP64
ORDERING NUMBER: STLC60134S
lows to get a T1.413Issue 2 compliantsolution.
The STLC60134S analog front end handles 2
transmissionchannels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream channel
and a 1.536 to 8.192Mbit/sdownstreamchannel.
A 256 carrier DMT coding (frequency spacing
4.3125kHz) transforms the downstream channel
to a 1MHz bandwidth analog signal (tones 32-
255) and the upstream channel (tones 8-31) to a
100kHzbandwidthsignal on the line.
This asymmetricaldata transmission system uses
high resolution, high speed analog to digital and
digital to analog conversion and high order analog filtering to reduce the echo and noise in both
August 1999
TXP
TXN
RXP(0:1)
RXN(0:1)
G=-15...0dB
step=1dB
+
+
-
AGCtx
G=0..31dB
step=1dB
+
+
-
AGCrx
1.1MHz
HC2
R-MOS-C
TUNING
1.1MHz
HC1
I/V-REF
138KHz
SC2
XTAL-DRIVER
VCXO
DAC
ANALOG
LOOP
ADC
DAC MUX
ERROR
CORRECTION
MUX
DIGITAL
LOOP
12 bits 4 bits
13 bits
4 bits
D99TL453
DIGITAL
IF
1/22
STLC60134S
the ATU-C/ATU-R receivers and transmitters.External low noise driver and input stage used with
STLC60134Sguarantee low noise performances.
The STLC60134S chip can be used at ATU-C
and ATU-R ends (behaviour set by LTNT pin).
The selection consists mainly of a filter interchange between the RX and TX path. The filters
(with a programmablecutoff frequency) use automatic Continuous Time Tuning to avoid time varying phase characteristicwhich can be of dramatic
consequencefor DMT modem. It requiresfew external components, uses a 3.3V supply (a separate 3.0V supply of the digital part is possible)
and is packaged in a 64-pin TQFP in order to reduce PCB area.
The Receiver (RX) part
The DMT signal coming from the line to the
STLC60134S is first filtered by the two following
external filters:
POTSHP filter: Attenuation of speech and POTS
Channel filter:
signalling
Attenuation of echo signal to
improve RX dynamic
An analog multiplexer allows the selection between two input ports which can be used to select
an attenuated(0, 10dB for ex.) version of the signal in case of short loop or large echo. The signal is amplified by a low noise gain stage (031dB) then low-pass filtered to avoid anti-aliasing
and to ease further digital processing by removing unwantedhigh frequencyout-of-bandnoise.
A 12-bit A/D converter samples the data at
8.832MS/s (or 4.416MS/s in alternative mode),
transforms the signal into a digital representation
and sends it to the DMT signal processor via the
digital interface.
The Transmitter(TX) part
The 12-bit data words at 8.832MS/s (or
4.416MS/s) coming from the DMT signal processor through the digital interface are transformed
by D/A converterinto a analog signal.
This signal is then filtered to decrease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band
noise (which can be echoedto the RX path)to an
acceptable level. The pre-driver buffers the signal
for the external line driver and in case of short
loop provide attenuation(-15...0dB).
The VCXO part
The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery.
The XTAL driver is able to operateat 35.328MHz
and provides an amplitude regulation mechanism
to avoid temperature / supply / technology de-
pendent frequencypulling.
The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and
can be used to tune the XTAL frequency with the
help of external components. A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed
with the help of an external capacitor (on VCOC
pin).
See chapter ’VCXO’ for the external circuit related to the VCXO
.
The Digital Interfacepart
The digital part of the STLC60134S can be divided in 3 sections:
The data interface converts the multiplexed
data from/to the DMT signal processor into
valid representation for the TX DAC and RX
ADC. It performs also the error correction
mechanism needed at the (redundant) ADC
output.
The control interface allows the board processor to configure the STLC60134S paths
(RX/TX gains, filter band, ...) or settings (OSR,
vcodac enable,digital / analog loopback,...).
The test interface to enable digital (Full Scan,
nandtree, loop backs, functional,...) or analog
(TIN, TOUT assignation) tests to be performed.
DMT Signal
A DMT signal is basically the sum of N independently QAM modulated signals, each carried
over a distinct carrier. The frequency separation
of each carrier is 4.3125kHz with a total number
of 256carriers (ANSI). For N large, the signal can
be modelledby a gaussianprocess with a certain
amplitude probability density function. Since the
maximum amplitude is expected to arise very
rarely, we decide to clip the signal and to tradeoff the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms= ”crest factor”) of 5 will be used resulting in a maximum
SNR of 75dB.
ADSLDMTsignalsarenominallysentat-40dBm/Hz
±3dB (-3.65dBm/carrier) with a maximal power of
100mW for down link transmitterand 15.7mWfor
uplink transmitter.
DMT symbols are transmitted without ’windowing’ causing sin (x)/x like sidelobes. For spectral
response shaping, the 1st sidelobe level is assumed to be 13dB under the carrier level with
an attenuationof -20dB/dec.
The minimum SNR + D needed for DMT carrier
⋅
demodulation is about (3
N + 20) dB with a
minimum of 38dB were N is the constellation size
of a carrier(in bits).
2/22
STLC60134S
Maximum/ minimumsignal levels
The following table gives the transmitted and received signal levels for both ATU-R and ATU-C
sides. All the levels are referred to the line volt-
mit power and line impedance signal amplitudes
can differ from thesevalues.
The referenceline impedance for all power calculationsis 100Ω.
ages (i.e. after hybrid and transformers in TX direction, before hybrid and transformer in RX direction).
Note that signal amplitudes shown below are for
illustration purpose and depending on the trans-
Table 1. Target Signal Levels
Parameter ATU - C ATU - R
Max level 839 mVpdif 15.8 Vpdif 3.95 Vpdif 3.4 Vpdif
Max RMS level 168 mVrms 3.16 Vrms 791 mVrms 671mVrms
Min level 54 mVpdif 3.95 Vpdif 42 mVpdif 839 mVpdif
Min RMS level 11 mVrms 791 mVrms 8 mVrms 168mVrms
Table 2. Total Signal Level
Parameter ATU - C ATU - R
Max level for receiver 4 Vpdif (Long line) 4.2 Vpdif (Short line)
(on the line).
RX TX RX TX
(on the line).
RX TX RX TX
PACKAGE
The STLC60134S is packaged in a 64-pin TQFP
package (body size 10x10mm,pitch 0.5mm).
Figure 2. Pin Connection
TX1
TX0
NU3
NU2
NU1
NU0
CTRLIN
DVSS1
CLKM
CLNIB
CLWD
RX3
RX2
RX1
RX0
TX3
TX2DVDD2
62
63
64
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16DVDD1
17 18 19 20 21
PDOWN
AVSS1
DVSS2
61
LTNT
RESETN
XTALO
XTALI
AVDD1
RES
VCXO
AVDD2
IVCO
IREF
AVSS2
60
59 58 57 56 5455 53 52 51 50 49
22 23 24 25 26
GP0
RES
VRAP
AVSS3
271128 29 30 31 32
VREF
VRAN
AVDD3
AVDD4
NC0
AVSS6
NC1
RXIP1
TXP
RXIN1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TXN
RXIP0
RXIN0
GC1
GC0
VCOC
GP2
AVDD6
AVDD5
RES
RES
AGND
RES
RES
AVSS5
AVSS4
GP1
D98TL355mod
3/22
STLC60134S
Table 3. Pin Functions.
N. Name Function PCB connection Supply
ANALOGINTERFACE
24 VRAP positive voltage reference ADC Decoupling network AVDD3
25 VREF ground reference ADC Decoupling network AVDD3
26 VRAN negative voltage reference ADC Decoupling network AVDD3
31 TXP pre driver output Line driver input AVDD4
32 TXN pre driver output Linedriver input AVDD4
38 AGND virtual analog ground (AVDD/2 = 1.65V) Decoupling network AVDD5
44 VCOC VCODAC time constant capacitor VCODAC cap. AVDD5
45 GC0 External gain control output LSB AVDD5
46 GC1 External gain control output MSB AVDD5
47 RXN0 analog receive negative input Gain0 Echo filter output AVDD5
48 RXP0 analog receive positive input Gain 0 Echo filter output AVDD5
49 RXN1 analog receive negative input Gain1 (most sensitive input) Echo filter output AVDD5
50 RXP1 analog receive positive input Gain 1 (most sensitive input) Echo filter output AVDD5
53 IREF current reference TX DAC/DACE Decoupling network AVDD2
55 IVCO current reference VCO DAC VCO bias network AVDD1
56 VCXO VXCO control current VCXO filter AVDD1
59 XTALI XTAL oscillator input pin Crystal + varicap AVDD1
60 XTALO XTAL oscillator output pin Crystal + varicap AVDD1
DIGITAL INTERFACE
1 TX1 digital transmit input, parallel data DVDD2
2 TX0 digital transmit input, parallel data DVDD2
7 CTRLIN serial data input (settings) Async Interface DVDD2
9 CLKM master clock output, f = 35.328MHz Load = CL<30pF DVDD2
10 CLNIB nibbleclock output,f = 17.664MHz(OSR= 2) or ground(OSR = 4) Load = CL<30pF DVDD2
11 CLWD word clock output, f = 8.832/4.416MHz Load =CL<30pF DVDD2
12 RX3 digital receive output, parallel data Load =CL<30pF DVDD2
13 RX2 digital receive output, parallel data Load =CL<30pF DVDD2
14 RX1 digital receive output, parallel data Load =CL<30pF DVDD2
15 RX0 digital receive output, parallel data Load =CL<30pF DVDD2
18 PDOWN power down select, ”1” = power down Power down input DVDD2
19 LTNT ATU-R / ATU-C select pin
20 RESETN reset pin (active low) RC- reset DVDD2
22 GP0 General purpose output 0 (on AVDD 1) Echo filter output AVDD
33 GP1 General purpose output 1 (on AVDD 1) Echo filter output AVDD
43 GP2 General purpose output 2 (on AVDD 1) Echo filter output AVDD
63 TX3 digital transmit input, parallel data Load =CL<30pF DVDD2
64 TX2 digital transmit input, parallel data Load =CL<30pF DVDD2
21 RES RESERVED Must be connected
36,
37,39,
40, 57
RES
mode MSB
SUPPLYVOLTAGES
8 DVSS1 DVSS
16 DVDD1 Digital I/O supplyvoltage DVDD
17 DVDD2 digital internal supply voltage DVDD
23 AVSS3 AVSS
27 AVDD3 ADC supplyvoltage AVDD
1
, ATU-R = 0 /ATU-C = 1 / test
RESERVED
VDD in ATU-C mode DVDD2
to DVSS (input)
Must be connected
to AVSS (input)
4/22
STLC60134S
Table 3. Pin Functions
(continued)
28 AVDD4 TX pre - drivers supply AVDD
34 AVSS4 AVSS
35 AVSS5 AVSS
41 AVDD5 CT filter supply AVDD
42 AVDD6 LNA supply AVDD
51 AVSS6 AVSS
52 AVSS2 AVSS
54 AVDD2 DAC and support circuit AVDD
58 AVDD1 XTAL oscillator supply voltage AVDD
61 AVSS1 AVSS
62 DVSS2 DVSS
SPARES
3 NU3 Not used inputs DVSS
4 NU2 Not used inputs DVSS
5 NU1 Not used inputs DVSS
6 NU0 Not used inputs DVSS
29 NC0
30 NC1
1
LT ↔ AUT-C; NT ↔ ATU-R
Figure 3. Grounding and DecouplingNetworks.
VRAP pin VRAN pin
10µF 100nF 10µF 100nF
10µF 100nF
10µF
VREF pin
ANALOG
VDD
IREF pin VCOC pin
ATU-C END: BLOCK DIAGRAM
The transformer at ATU-C side has 1:2 ratio. The
termination resistors are 12.5Ω in case of 100Ω
lines.
The hybrid bridge resistors should be < 2.5kΩ for
low-noise.
An HP filter must be used on the TX path to re-
4.7µ
H
L1
10µF 100nF
10µF100nF
10µF100nF
AVDD (each pin
have its own capacitor)
100nF
AGND pin
must
D98TL356
duce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a LP filter
must be used in order to reduce the echo signal
level and to avoid saturation of the input stage of
the receiver.
The POTS filter is used in both directions to reduce crosstalk between STLC60134S signals
and POTS speech and signalling.
5/22
STLC60134S
Figure 4. ATU-C ENDBlock Diagram.
POTS
LINE
Zo=100
2:1
HP POTS FILTER
RXT1 RXT2
RR
2R 2R
LP
POTS FILTER
12.512.5 LPF
GRX
RXP(0:1)
RXN(0:1)
0..31dB
LNA
35.328MHz
XTRAL
DRIVER
LP138KHz
SC2
12-bit A/D
CONVERTER
MASTER CLOCK
35.328MHz
NIBBLES 17.664MHz
WORD 8.832/4.416MHz
RXn
8.832MS/s
4.416MS/s
4
CTRLIN
LTNT=1
RESETN
TO
STLC60135
GTX
LINE
DRIVER
TXP
HPF
TXN
-15..0dB
PD
ATU-R END: BLOCK DIAGRAM
The ATU-R side block diagram is equal to the
ATU-C side block diagram with the following differences:
- Thetransformerratio is 1:1
- Terminationresistors are 50Ω for 100Ω lines.
An LP filter may be used on the TX path to re-
Figure 5. ATU-R END Block Diagram.
POTS
LINE
Zo=100
1:1
HP POTS FILTER
RXT1 RXT2
RR
5050 HPF
2R 2R
LP
POTSFILTER
GRX
RXP(0:1)
RXN(0:1)
VCXOUT
VCODAC
0..31dB
LNA
LP 1.1MHz
HC2
12-bit D/A
CONVERTER
4
D98TL357mod
TXn
8.832MS/s
4.416MS/s
duce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a HP filter
must be used in order to reduce the echo signal
level and to avoid saturation of the input stage of
the receiver.
The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS
speech and signalling. Low pass POTS filter can
be verysimple for Lite - ADSLapplication
35.328
MHz
MASTER CLOCK
XTAL
DRIVER
LP 1.1MHz
HC2
12- bitA/D
CONVERTER
35.328MHz
NIBBLES17.664MHz
WORD 8.832/4.416MHz
RXn
8.832MS/s
4.416MS/s
4
CTRLIN
LTNT=0
RESETN
TO
STLC60135
6/22
GTX
LINE
DRIVER
LPF
TXP
TXN
-15..0dB
PD
LP 138KHz
SC2
12-bit D/A
CONVERTER
4
D98TL358mod
TXn
8.832MS/s
4.416MS/s
STLC60134S
RX PATH
Speech filter
An external bi-directional LC filter for up and
downstream POTS service splits the speech signal from the ADSL signal to the POTS circuits on
ATU-C.
The ADSL analog front end integrated circuit
does not contain any circuitry for the POTS service but it guarantees that bandwidth is not disturbed by spurious signals from the ADSL-spectrum.
Channel Filters
The external analog circuits provide partial echo
cancellation by an analog filtering of the receive
signal for both ATU-R (Reception of downstream
channel) and ATU-C (Reception of upstream
channel). This is feasible because the upstream
and the downstream data can be modulated on
separatecarriers (FDM).
Line Noise Model
The power spectral density of the crosstalk noise
sources as described in ANSI document is given
in the figure below (no HDB3 interferer signals).
Also given in dotted line, is the noise model used
in this document to specify the sensivity requirements which are strongerthan the original ones.
Figure 6. CrosstalkPSD.
dBm/Hz
-100
-110
-120
-130
-140
D98TL359
79.5 138 250 795 kHz
the frequency band of interest. The maximum
noise density within the pass band can exceed
the average valueas follows:
ATU-R RX path (max AGCsetting):
<100nVHz
<31nVHz
-1/2
@ 138kHz
-1/2
for 250kHz< f
ATU-C RX path (max AGCsetting):
<100nVHz
-1/2
for 34.5kHz< f <138kHz
RX-PATHNOISE AT MINIMUM GAIN
At the minimum AGC the total average thermal
noise of the analog RX-path at the ADC input
should be lower than the ADC quantisationnoise.
The maximumnoise density within the pass band
can exceed the average value as follows:
ATU-R RX path (min AGCsetting):
<500nVHz
-1/2
@ 138kHz< f
ATU-C RX path (min AGCsetting):
<1.5µVHz
-1/2
@ 34.5kHz < f < 138kHz
These noise specifications correspond with 10bit
resolutionofthe complete RX-path.
Table 4. RX Common-mode Voltage
Description Value/Unit
Common mode signal V
at RXIN1 and RXIN2:
CM
1.6V < V
CM
<1.7V
AGC of RX path
The AGC gain in the RX-path is controlled
through a 5-bits digital code.
Four inputs are provided for RX input and the selection is made with the RXMUX bits of the
CTRLIN interface. This can be used to make
lower gain paths in case of high input signal.
Table 5. AGC Characteristics.
Signal to Noise Performance
RX- PATH SENSITIVITY AT MAXIMUM GAIN
The RX path sensitivity at the maximal RX-AGC
of the ATU-R receiver is defined at -140dBm/Hz
(for 100Ω ref) on the line. This figure corresponds
to the equivalent input noise of 31nVHz
-1/2
seen
on the line.
The sensitivity at the maximal RX - gain of the
ATU-C receiver is defined at -130dBm/Hz (for
100Ω ref) on the line. The figure corresponds to
the equivalent input noise of 100nVHz
-1/2
seen
on the line.
Both noise figures include the noise of the hybrid.
It is the equivalent average thermal noise over
Description Value/Unit
Input referred noise
(max. gain)
Max. input level 1Vpd
Max. output level 1Vpd
Gain range 0to 31dB withstep = 1dB
Gain and step accuracy
20nVHz
±
-1/2
0.3dB
RX Filters
The combination of the external filter (an LC ladder filter typically) with the integrated lowpass filter must provide:
- echo reduction to improve dynamicrange
- DMT sidelobe and out of band(anti-aliasing)
attenuation.
- Anti alias filter (60dB rejection @ image freq.)
7/22
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