SGS Thomson Microelectronics STLC5460 Datasheet
LINE CARD INTERFACE CONTROLLER
BOARD CONTROLLER FOR UP TO 16 ISDN
LINES OR16 VOICESUBSCRIBERS.
TWOSERIAL INTERFACES :
-PCM Four bidirectional multiplexes
-GCI One (ortwo) at 2 Mb/s.
NON BLOCKING SWITCH FOR 128 CHAN-
NELS (16, 32 OR 64 KB/S BANDWIDTH).
N CONSECUTIVE 64 kb/s CHANNELS FROM
AN INPUT MULTIPLEX CAN BE SWITCHED
AS A SINGLE N X 64 kbit/s CHANNEL TO AN
OUTPUTMULTIPLEX AT 2048 kb/s.
TIME SLOT ASSIGNMENT FREELY PROGRAMMABLE FOR EVERY CONNECTED
SUBSCRIBER.
PROGRAMMABLE PCM DATA RATES UP
TO 8192 kb/s.CONSTANT DATA RATE AT 2
Mb/s ON GCISIDE.
PCMinterface :
- Simpleanddoubleclockfrequencyselectable;.
- Programmableclock shift
- Tristatemodecontrolsignalsforexternaldrivers.
GCI interface :
- Sixbits or fourbitsCommand/indicatechannel
selectablefor analog or digital equipment
STLC5460
PLCC44
ORDERING NUMBER: STLC5460
- Command/IndicateMonitorchannelsvalidated
ornot
Microprocessoraccess to two selectedbidirectional channelsof GCI and/or PCM.
Multicontrollersfor layer1 functions:
- C/Iprotocolcontrollerfor up to 16 C/Ichannels
- Monitorprotocol controllerfor up to 16
Monitorchannels.
Standard microprocessor interface with multiplexed address/data bus or separate address
data buses.
PLCC44 pins PACKAGE
PIN CONNECTION(Topview)
February 1997
TSC0
TxD0
TSC1
TxD1
TSC2
TxD2
TSC3
TxD3
PFS
PDC
RxD2
7
A1
8
9
10
11
12
13
14
15
16
17
AD2
AD0A2AD1
123564
2322211918 20 28272624 25
AD4
AD3
RES
NRDY/NWAIT
AD5
AD6
P0
AD7
DOUT1
DOUT0
40414244 43
SS
V
DS/NRD
39
38
37
36
35
34
33
32
31
30
29
A3
DIN0
DIN1
VSS2
VDD2
FSC
DCL
INT
ALE/AS
NCS
RW/NWR
D94TL149B
VDD1
A0
RdD3
RxD1
RxD0
1/54
STLC5460
DESCRIPTION
The Line Card Interface Controller, STLC5460, is
a monolithic switching device for the path control
of up to 128 channels of 16, 32, 64 kbps bandwidth. Two consecutive 64 kbps channels may
also be handled as a quasi single 128 kbpschannel. For these channels, the LCIC performs nonblocking space time switching between two serial
interfaces: the system interface (or PCM interface) and the general componentinterface (GCI).
PCM interface can be programmed to operate at
different data rates between 2048 and 8192 kbps.
The PCM interface consists of up to four duplex
ports with a tristate indication signal for each output line. The GCI interface can be selected to be
PCM interfaceat 2Mbit/s.
The LCIC can be programmed to communicate
with GCI compatible devices such as STLC3040
(SLIC), STLC5411 (U interface) and others. The
device manages the layer 1 protocol buffering the
Command/Indicateand Monitor channels for GCI
compatible devices.
Due to its capability to switch channelsof different
BLOCK DIAGRAM
bandwidths, the STLC5460 can handle up to 16
ISDN subscribers with their 2B+D channel structure in GCI configuration,or up to 16 analog subscribers.Since its interfacescan operate at different data rates, the LCIC is an ideal device for
data rate adaptationbetween PCM interface up to
8Mb/sand GCI at 2Mb/s.
The device gives the possibility of checking the
correct communication inside the PBX or Public
CentralOffice providing:
- independentPCM delay setting
- PCM comparisonfunction
-Pseud oRando mSequenc eGener atorandAnalyse r.
Moreover, the LCIC is one of the key building
blocks for networks with either central, distributed
or mixed signaling and packet data handling architectures associated with ST5451 (HDLC controller).
The device iscontrolled by a standard8 bit parallel microprocessor interface with a multiplexed
address-data bus. The device may optionally be
controlledby separateaddress and data buses.
4 PCM
2 GCI
DESTINATION REG COMMAND REG SOURCE REGISTER
(ADDRESS) (DATA) (DATA)
COMMAND MEMORY
194 WORDS OF 14 BITS
6 bits
COUNTERS
1 bit for 16 tristate
PARALLEL
SERIAL
SHIFTING
C/I, MON
TRANSMIT
16
INDIPENDENT
CONTROLLERS
SPECIAL
SWITCH
16, 32, 64
KB/S
EXTRACTION
2x64
Kbit
CHANNEL
AT
SWITCHING
MEMORY
194
BYTES
(4PCM+2GCI + 2
CHANNEL -INSERTION- =
128+64+2=194)
RECEIVER
D94TL160A
C/I, MON
COUNTERS
SERIAL
PARALLEL
SHIFTING
INSERTION
2x64
Kbit
CHANNEL
4 PCM
2 GCI
2/54
PIN DEFINITIONSAND FUNCTIONS
Symbol Pin number Type(*) Function
VDD1 1 I Supply Voltage 5V,±5% .
A0 2 I (**) Non Multiplexed Mode:
RxD3
RxD2
RxD1
RxD0
3
4
5
6
I Receive PCM interface Data : Serial data is received at these lines at
A1 7 I (**) Non Multiplexed Mode:
TSC0
TSC1
TSC2
TSC3
TxD0
TxD1
TxD2
TxD3
8
10
12
14
9
11
13
15
OD Tristate control for the PCM interface. These lines arelow when the
O Transmit PCM interface Data : Serial data issent by theselines at standard
PFS 16 I PCM interface framesynchronization pulse.
PDC 17 I PCM interface data clock, singleor double rate.
A2 18 I (**) Non Multiplexed Mode:
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
19
20
21
22
23
24
25
26
I/O Address Data Bus. Ifthe multiplexed address/data µP interface bus mode is
VSS1 27 I Ground : 0V
DS/NRD 28 I Motorola like mode: Data Strobe
RW/NWR 29 I Motorola like mode: Read/Write
NCS 30 I Not Chip select. A low on this line selects the STLC5460 for a read/write
this input interfaces to the system’s address bus to select aninternal
register for a read or write access.
Multiplexed Mode:
A0 at VDD, NRDY/NWAIT pin delivers NWAIT
A0 at VSS, NRDY/NWAIT pin delivers NREADY
standard TTL orCMOS levels.
this input interfaces to the system’s address bus to select aninternal
register for a read or write access.
Multiplexed Mode:
A1 at VDD, NCS signal provided by the system is not inverted by the circuit.
A1 at VSS, NCS signal provided by the system is inverted by the circuit.
corresponding TxD outputs are valid.
TTL or CMOS levels. These pins can be tristated.
this input interfaces to the system’s address bus to select anintenal register
for a reador write access.
Multiplexed Mode:
A2at VDD, AS/ALE signal providedby the system is notinvertedby the circuit
A2 at VSS, AS/ALE signal providedby the system isinverted by the circuit
selected these pins transfer data and commands between theµP and the
STLC5460.
If a demultiplexed mode is used, these bits interface with the system data
bus.
Intel Like Mode: Not Read
The signal indicates aread operation, active low
Intel Like Mode: Not Write
The signal indicates aWrite operation, active low.
operation.
STLC5460
(*): (I)Input
(O) Output
(IO) In/Output
(OD) Open Drain
(**): With Pull up resistance.
3/54
STLC5460
PIN DEFINITIONSAND FUNCTIONS (continued)
Symbol Pin n PLCC Type Function
AS/ALE 31 I Multiplexed A/D mode:
INT 32 OD Interruptline, active low.
DCL 33 0 Data clock output.
FSC 34 O Frame synchronization output.
VDD2 35 I Power supply : 5V
VSS2 36 I Ground.
DIN1 37 I GCI Data input 1
DIN0 38 I GCI Data input 0
A3 39 I (**) Non Multiplexed Mode:
DOUT0 40 O GCI Data Output 0
DOUT1 41 O GCI Data Output 1
PO 42 I(**) P0 at VSS: variable access mode
NRDY/N
43 OD If P0 at VSS:
WAIT
RES 44 I Reset. A logical high onthis input forces theSTLC5460 into the reset state
(*): (I)Input
(O) Output
(IO) In/Output
(OD) Open Drain
(**): With Pull up resistance.
used to latch the address from ADn
Non Multiplexed A/D Mode:
This pin at VSS indicates Intel like interfaces
This pin at VDD indicates Motorola like interfaces.
this input interfaces to the system’s address bus to select aninternal
register for a read or write access.
Multiplexed Mode:
A3 at VDD, DS/NRD signal provided by the system is not inverted by the
circuit
A3 at VSS, DS/NRD signal provided by the system isinverted by the circuit
P0 at VDD: fixed access mode
Intel like mode: this pin delivers NRDY
Motorola mode: this pin delivers NWAIT
Figure 1:
4/54
GCI and PCM Interfaces.
DCL
FSC
DOUT0
DIN0
DOUT1
DIN1
CLOCKS
PCM0
MUX0/GCI0
PCM1
MUX1/GCI1
PCM2
PCM3
LCIC
MICROPROCESSOR INTERFACE
PDC
PFS
RxD0
TxD0
TSC0
RxD1
TxD1
TSC1
RxD2
TxD2
TSC2
RxD3
TxD3
TSC3
D94TL159A
STLC5460
LINE CARD APPLICATIONS
The LCIC is designed to fit both digital and analogue line cardarchitectures.
It supportsup to 16 ISDN subscribers or 16 voice
subscribers.The level 1 devicesare connectedto
ST5451 circuits to perform the D channel handling.
The clock frequency of PDC is equal to once or
twice the datarate, See fig 1 and 2. Whenoperating at single rate (2048 kb/s) and not at double
clock frequency (4096 kHz), an onchip clock frequency doubler providesa 4098 kHz clock for the
GCI interface (DCL).
The rising edge of PFS signal is used to determine the first bit of the first time slot of the frame.
The length of PFS pulse is one bit-time at least
Analogue Line Card
In analogue line cards LCIC controls signalling,
voice and datapath of 64 kb/s channels.
When used in combinationwith L3040/L3000N,it
allows to implement an optimised line card architecture:
the LCIC controls the configuration of L3040 and
exchange signalling with the L3040.
and the length between two pulses can be also
one bit time.
After reset,the LCICreaches synchronismhaving
received two consecutive correct PFS pulses.
Synchronisationis consideredlost by the device if
the PFS signal is not repeated with the correct
repetition rate which has been stored by the circuit at the beginningof synchronisation research.
The LSYNC bit in the Interrupt Register indicates
if the component is synchronised or not: a logical
Digital Line Card
In digital line cards LCIC controls the configuration of Level 1 circuits (U or S Interface) by
means of MON channel configuration and performs activation/deactivation by means of Command/Indicate protocol. LCIC switches the B
channels and can switch the D channels if the
processingis centralised.
0 indicates the synchronous state, a logical ”1”
showsthat the synchronismhas been lost.
The relation between the framing signal PFS and
the bit stream is controlled by the contents of
IPOF, OPOF and CPOF registers. These registers denote the number of bit times the PCM
frame is shifted. EachPCM multiplex can be programmed withdifferentshifts .
Without programming the bit shift function of the
FUNCTIONAL DESCRIPTION
PCM INTERFACE
PCM interface, the rising edge of the PFS signal
marks the first bit of input PCM frame and the
first bitof output PCM frame.See Fig 3
The PCM Interface Registers configure the data
transmitted or received at the PCM port, for one
PCM, the maximum data rate can change depending on the Mode selected:
PCM Mode 0: maxrate 2048kb/s with fourPCM
portsactive
PCM Mode 1: maxrate 4096 kb/s with two PCM
portsactive
PCM Mode 2: maxrate 8192 kb/s with one PCM
portsactive.
The ”actual data” rate may be varied in a wide
range without programming.
An automate computes the number of clock per
frame. Hence, the data rate can be stepped in 8,
16 or 32 kb/s in increments in PCM mode 0, 1, 2
GCI Interface
The Monitor and the Command/Indicatechannels
may be validated or not, in this second case the
B3 and B4 channels become standard channels
at 64 kb/s.
When validatedCommand/Indicatechannel may
be configured with fourbits for digital cards or six
bits for analogue cards.
The clocks (Bit clock and frame clock) are delivered by the device with double rate clocking or
simple rate clocking.
FSC and DCL are output signals derived from
PFSand PDC which are inputsignals.
respectively.
GCI PCM
DCL clock kHz
Simple (*) Double Simple Double
2.048 4.096 2.048 2.048 2.048 Mode 0
2.048 4.096 2.048 4.096 2.048 Mode 0
2.048 4.096 2.048 4.096 4.096 Mode 1
2.048 4.096 2.048 8.192 4.096 Mode 1
2.048 4.096 2.048 8.192 8.192 Mode 2
2.048 4.096 2.048 16.384 8.192 Mode 2
(*) as GCI formatbut with simple clock.
Data kb/s
PDC Clock (kHz)
Data rate kb/s Mode
5/54
STLC5460
Figure 1: PCMInterface. Alignmentin doubleclock mode.
Clocks received by the circuit
Mode not delayed:
PFS
DCL=1
DEL=0
PFSP=0
PDC
PFS
First bit of the frame
DCL=1
DEL=0
PFSP=1
Mode delayed:
DCL=1
DEL=1
PFSP=0
DCL=1
DEL=1
PFSP=1
PDC
First bit of the frame
PFS
PDC
First bit of the frame
PFS
PDC
First bit of the frame
6/54
Figure 2: PCMInterface. Alignmentin simpleclock mode.
Clocks received by the circuit
PFS
PDC
STLC5460
DCL=0
DEL=0
PFSP=0
PFS
DCL=1
DEL=0
PFSP=1
PDC
Mode not delayed
PFS
DCL=1
DEL=1
PFSP=0
PDC
First bit of the frame
First bit of the frame
First bit of the frame
PFS
DCL=1
DEL=1
PFSP=1
Mode delayed
PDC
First bit of the frame
7/54
STLC5460
Figure 3: PCMInterface. Clockand Data in/Data out.
PDC
ODL=0
GCI like
ODL=1
ISPP=0
ISPP=1
GCI like
DOUT
DOUT
DIN
DIN
Double clock DCP =1
PDC
ODL=0
DOUT
8/54
ODL=1
DOUT
DIN
Simple clock DCP=0
STLC5460
MEMORY STRUCTURE AND SWITCHING
The LCIC contains three memories: Auxiliary
Memory (AM), Data Memory (DM) and Control
Memory (CM).
The Auxiliary Memory consists of one block divided in four parts of 16 words.
This Auxiliary Memory is used for validated data
from Monitor and Command/IndicateRx channels
and to transmit data to Monitor and Command/IndicateTx channels.
The Data Memory buffers the data input from the
PCM and the GCI interface. It has a capacity of
128 + 64 time slots to buffer 4 PCM frame of 32
time slots and two GCI interfaces. It is written periodically onceevery 125 microseconds controlled
by theinput countersassociated to PCM interface
and to GCI interface.To perform the switching the
loopback function, this memory is read, random,
in accordancewith the controlmemory
The Control Memory has a capacity of 128 + 64
words of 14 bits: 8 of data and6 ofcode. The 14
bits are written random, via microprocessor interface and read cyclically under the control of
the output counters associated to PCM interface
and GCI interface.
For control memory access and different functions, threeregisters are provided:
destinationregister:
it contains the address of a specific location of
the controlmemory;
source register :
it contains the data (to be written or read) of the
control memory corrisponding to the address indicatedby thedestination register;
commandregister:
it contains the code (6 bits to be written or read)
of the control memory.
The content of command register defines the different capabilities: switching at 64 kb/s, 32 kb/s,
16 kb/s, loopback and also extraction/insertion
from themicroprocessorinterface.
A memory access using the actual command register and source registeris performedupon every
destination register write access. The processing
of the memory access takes at most 488ns.
MICROPROCESSORINTERFACE
After Reset, the Microprocessor interface is in
non-multiplexed mode (Address bus and Data
bus mustbe non-multiplexed):
if ALE pin is hardwired at VSS, the Microprocessor interface is Motorola like, Address/Data are
non-multiplexed.
if ALE pin is hardwired at VDD the Microprocessor interface is Intel like, Address/Data are nonmultiplexed.
After Reset,as soon as two successiveedges are
detected on ALE pin (Rising and falling edges)by
the circuit the Microprocessor interface switches
in multiplexed mode (Address bus and Data bus
must be multiplexed). The circuit is set automaticallyin Motorolalike or inIntel like mode.
For the circuit Address bus and Data bus multiplexed or not multiplexed, the difference between
Motorolalikeand Intellikemodeisshowedin fig. 4.
Figure 4.
9/54
STLC5460
The microprocessor interface type is set via P0
pin as shown hereafter :
P1 is an outputandit isnot used if P0 = 1.
The device selects automatically either Motorola
interfaceor IntelInterface.
P0 P1 Automatical selection
1 Z Intel MUX mode
Motorola MUX mode
Intel DEMUX mode
Motorola DEMUX mode
0 If A0 = 1 P1 pin delivers WAIT automatically
If A0 = 0 P1 pin delivers READY automatically
Moreover, for a multiplexed mode µP interface,
A1 to A3 pinsmean :
A1 = 1: CS signalprovided by the systemis not
inverted by the device
A1 = 0: CS signal provided by the system is inverted by the device
A2 = 1: AS signal provided by the system is not
inverted by the device
A2 = 0: AS signal provided by the system is inverted by the device
A3 = 1: DS signal provided by the system is not
inverted by the device
A3 = 0: DS signal provided by the system is inverted by the device.
C/I AND MON CHANNELS, EXTRA CHANNELS
The Command/indicateand Monitor channelscan
be validatedor not:
if validated, the C/I and MON protocol controllers
operate and it is not possible to use this channels
for switching, if not validated the protocols are inhibited and the channels can be used as extrachannels for switching.
Command/IndicateProtocol
Sixteen C/I channelsare implemented,one bit of
the configuration register MCONF1, indicates the
number of bits of the primitive (four or six bits) for
all the channels.
To transmit a primitive into one of the 16 channels, the mp loads the primitive (4 or 6 bits) into
source register and the number of the C/I channel into destination register with W/R bit of command registerat ”0”.
The two more significant bits of the source register indicates if the primitive, bit0/5 of the same
register, has not been transmittedyet, transmitted
once, twice or more .
When a new primitive has been received twice
identical, on one of the 16 C/Ichannels, an interrupt is generated,the number of the C/I channel
(4 bits) is written in the Receive C/I status register , and the primitive received is in the Auxiliary
Memory,all accessibleto theµp
Moreover, the microprocessor can read directly
the 16 primitives that have been received and
stored into the Receive C/I Memory. To read this
memory the µp load in the Source Register the
number of Receive C/I channel it wants, and in
the destinationregister reads the primitive (4 or 6
bits) with a seventh bit which indicates whether
the primitive has been received once or twice
identical. vedi figura read aux mem Receive C/I
channels.
Monitor Channel Protocol
Sixteen Monitor channels are implemented. To
transmit a message the µp load into destination
register with W/R bit of Command Register at 1
the number of MON channels, and into source
register the message; this byte is transmitted if
BYTE Bitof Command Register is at 1.
This procedure is repeated for each byte of the
message if it islonger than onebyte.
When a new byte has been received twice identical from oneof the sixteen Monitor channels
an interrupt is generated, the number of MON
channel (4 bits) is written in Receive Monitor
StatusRegister and the last byte received is written in Receive data Monitor Channel Memory.
The remote transmitter will transmit the next byte
after reading of this register by the local microprocessor.
INSERTION- EXTRACTION
This function allows to insert data into GCI and
PCM channels and to extract data from GCI and
PCM interface. These data are provided either by
the microprocessor or by an internal Pseudo Random SequenceGenerator.
Insertion
Two programmable registers (Insert A and B)
contain the data to insert into two output time
slots continuously. To perform an insertion, four
registersare programmedby the microprocessor:
- in the Insert A and/or B Registersit writes the
data to insert.
- in the Source registers it writesthe A and/or B
registeraddress
- in the DestinationRegister it writes the output
interface, PCM or GCI, and the Time Slot selected.
10/54
STLC5460
- in the Command Register it writes the indication if insert into 64 kb/s, 32 kb/s or 16 kb/s
channel.
When the data has been inserted, status bit
(INS) of status register is put at logical 1 and an
interrupt is generated.
Extraction
Two programmable registers (Extract A and B)
contain the data extracted from two input time
slots. To perform an extraction, three registers
LIST OF REGISTER
Name MUX Mode
AD5 to AD1 (H) RBS A3 to A0 RBS
IIR
COMP
MCONF1
MCONF2
PCONF
CPOF
IPOF
OPOF
IPSH1
IPSH2
OPSH1
OPSH2
IPASS
OPASS
IMASS
OMASS
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
(00)
(01)
(02)
(03)
(04)
(05)
(06)
(07)
(08)
(09)
(0A)
(0B)
(0C)
(0D)
(0E)
(0F)
are processed by the microprocessor:
- Extract A and/or B Registers to read the data
extracted.
- The Sourceregister to indicate the input interface, PCM or GCI, and the Time Slot selected.
When the data is loaded in Extract A or Extract B Register, the bit EXT of STATUS register is put at logical1,and an interrupt is generated.
Read
Only
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DEMUX Mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STATUS
ECR
CMR
SRC
DST
INSA
INSB
EXTA
EXTB
INT
MASK
RMOS
TMOS
RCIS
TEST
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(1A)
(1B)
(1C)
(1D)
(1E)
(1F)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NB in Mux Mode AD7, AD6, AD0 andRDS bits are ignored
R
R
R
R
R
R
R
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11/54
STLC5460
CONFIGURATION REGISTER DESCRIPTION
Initialisationand IdentificationRegister(IIR)
7 0
RBS RST T1 T0 V3 V2 V1 V0
After Reset 3F (H)
T1/T0 Testfunctions
T1 T0 Description
0 0 Normal State
0 1 Command Memory orAuxiliary Auto Reset.
1 1 Auto Test. This function is reserved for manufacturer.
1 1 Reserved. Initialise CM so that the content of each input Time Slot t of input multiplexm is
If CM = 1 (Bitof Command Register):
the six lower bits of command Register andthe eight bits of Source Register are stored
into each address of command Memory.
If CM = 0 (Bit of Command Register) :
the eight bits of Source Register are stored into each address of Monitor Auxililary
Memory and the six lower bits of SourceRegister are stored intoCommand/Indicate
Auxilliary Memory.
The 16 C/I and Monitor channels are ready to transmit and toreceive data.After
AutoReset, BUSY and T0 goes to ”0”.
- The Pseudo Random Sequence generator is connectedinstead of Insert A Register and
PseudoRandom Sequence Analyzer is connected instead of Extract A Register.
- The Command Memory is loaded thanks to a specialalgorithm in order to switch the
sequence provided by the generator into TSO of PCMO, then the contents of TSO of
PCMO into TS1 of PCMO, then the contents of TS1 of PCMO into TS2 of PCMO and
so on.
Finally, the contentsof TS31 of MUX1 are taken into account by the Pseudo Random
Sequence Analyzer.After loading Command Memory, 193 switching are setup in real
time.The analyzer receivesthe Pseudo Random Sequence from the generator after
switching.
If LP = 1, the loopback is internal.
If LP = 0, an external loopback must be performed. So, Command Memoryand Data
Memory can be checked in the same time.
switched to output Time Slot t of output multiplex m
RBS Register BankSelection.
RBS = 0. The 16 first main registersare selected(0 to 15).
RST Reset Soft.
the programmableregistersare reset.
V3/V0 these bits are fixed at 0
COMPARISONREGISTER (COMP)
7 0
NEWE TIM CP6 CP5 CP4 CP3 CP2 CP1
After Reset 00(H)
NEWE New EXTRACT.
When NEWE = 1, EXT interrupt is generated only if a new word is loaded into
EXTRACT Registers (A or B).
TIM Timer, associatedto INS of INTRegister and to TIMO/1of CPOFregister.
TIM = 1 TIM0/1bits of CPOFregister are taken into account
TIM = 0 an interrupt is generatedeach 125 µs.
12/54
CP 6/1 Comparison6 to 1.
Bit streamof one PCM and bit stream of another PCM are compared at each bit time, if
there is difference,PDIF interruptis generated.
Comparison between
CP1 = 1 PCM0 and PCM1
CP2 = 1 PCM1 and PCM2
CP3 = 1 PCM2 and PCM3
CP4 = 1 PCM0 and PCM2
CP5 = 1 PCM1 and PCM3
CP6 = 1 PCM0 and PCM3
MULTIPLEXCONFIGURATION 1 REGISTER (MCONF1)
7 0
CIM MOM CI4MI CI4M0 - - GCIM1 GCIM0
After Reset 3F (H)
CIM Command/IndicateMode.
CIM = 1: the controller ignores the new received primitive if the previous has not been
read by the microprocessor.
STLC5460
CIM = 0: the controller overwrites the previous primitive without condition when it
receivesa newprimitive.
MOM Monitor channelMode
MOM = 1: if bytesare not receivedtwice identical the message is aborted.
MOM = 0: if bytes are not received twice identical the MOM controller doesn’t
acknowledgethe receivedbyte (GCI standard).
CI4M1 Command Indicate4 bitsfor Multiplex 1.
CI4M1 = 0: commandIndicate primitive has six bits.
CI4M1 = 1: commandIndicate primitive has four bits.
CI4M0 Command Indicate4 bitsfor Multiplex 0.
CI4M0 = 0: commandIndicate primitive has six bits.
CI4M0 = 1: commandindicate primitive has fourbits.
GCIM1 GCI Multiplex1.
GCIM1 = 1: themultiplex M1 is GCI,it includes eight GCI channels.
GCIM1 = 0: themultiplex M1 includes32 TimeSlots. (PCM like channel)
GCIM0 GCI Multiplex0.
GCIM0 = 1: theMultiplex M0 is GCI,it includes eight GCI channels.
GCIM0 = 0: themultiplex M0 includes32 TimeSlots. (PCM like channel)
MULTIPLEXCONFIGURATION 2 REGISTER(MCONF2)
7 0
- - M1D M0D ISPM TIMD MOD DCKM
After Reset FF (H)
M1D Multiplex1 Disable.
M1D = 1. Multiplex1 output is at high impedancecontinuously,
multiplex 1 inputis forced to ”1”,if it is GCI.
13/54
STLC5460
M0D Multiplex0 Disable.
M0D = 1. Multiplex0 output is at high impedancecontinuously,
multiplex 0 inputis forced to ”1”,if it is GCI.
TIMD Timer Monitor Channel Disabled.
TIMD = 1. The timer1ms is disabledfor each TransmitMonitor Channel.
ISPM Input Sampling Multiplex.
ISPM = 0. The inputbit is sampled at half bit time.
ISPM = 1. The inputbit is sampled at 3/4 bittime.
MOD Multiplex OpenDrain.
MOD = 1. The twomultiplex outputs are open drain.
MOD = 0. The twomultiplex outputs are at low impedance
DCKM Double clock for Multiplex.
DCKM = 1.DCL is twice data rate(Ex : if Data Rate = 2048 kb/s,DCL = 4096 kHz).
DCKM = 0.DCL is simple clock.
PCM CONFIGURATIONREGISTER (PCONF)
7 0
0 TSNB DEL PFSP ODL ISPP POD SCKP
After Reset 00(H)
TSNB Time Slot numbering.
TSNB defines the order of TS on the PCM when the data rate is 4 Mb/s or 8 Mb/s
related to theorder of TS on the PCM at 2 Mb/s(see table hereafter).
DEL Delayed Mode for each PCM.
DEL = 1. A delay of one clockpulse is appliedto thefirst bit of the frameof eachPCM.
DEL = 0. PFS indicates the first bit of the frame for each PCM (if OFFSET and shift are
zero).
PFSP PCM FrameSynchronisationSampling.
PFSP = 0. PFS signal is sampled on the fall edge of PDC signal.
PFSP = 1. PFS signal is sampled on the rise edge of PDCsignal.
ODL Output Delay.
ODL = 0. The bits areshifted out withzero delay.
ODL = 1. The bits areshifted out witha delay of one half bittime.
ISPP Input Sampling PCM.
ISPP = 0. The input bit is sampled at half bit time.
ISPP = 1. The input bit is sampledat 3/4 bit time.
POD PCM OpenDrain.
POD = 1. The PCM outputs are open drain
POD = 0. The PCM outputs are at lowimpedance.
SCKP Simple clock for PCM.
SCKP = 0. PDC signal is twice data rate. (Ex : if data rate = 2048 kb/s, PDC = 4096
kHz).
SCKP = 1. PDC is simple clock
14/54
TS and PCMn
at 4 Mb/s
with n = 0 or 2
TSNB = 1
TSNB = 0
TS at
2Mb/s
PCM at
2Mb/s
TS at
2Mb/s
PCM at
2Mb/s
STLC5460
TS0 TS1 TS2 TS3 TS30 TS31 TS32 TS62 TS63
TS0 TS0 TS1 TS1 TS15 TS15 TS16 TS31 TS31
PCMn PCMn+1 PCMn PCMn+1 PCMn PCMn+1 PCMn PCMn PCMn+1
TS0 TS1 TS2 TS3 TS30 TS31 TS0 TS30 TS31
PCMn PCMn+1
TS and PCM0
at 8 Mb/s
TSNB = 1
TS and PCM
at 8Mb/s
TSNB = 0
TS at
2Mb/s
PCM at
2Mb/s
TS at
2Mb/s
PCM at
2Mb/s
TS0 TS1 TS2 TS3 TS4 TS124 TS32 TS62 TS63
TS0 TS0 TS0 TS0 TS1 TS31 TS31 TS31 TS31
PCM0 PCM1 PCM2 PCM3 PCM0 PCM0 PCM1 PCM2 PCM3
TS0 to TS31 TS32 to TS63 TS64 to TS95 TS96 to TS127
TS0 to TS31 TS0 to TS31 TS0 to TS31 TS0to TS31
PCM0 PCM1 PCM2 PCM3
COMPLEMENTARY PCM OFFSET REGISTER (CPOF)
7 0
PMD1 PMD0 TIM1 TIM0 OOF1 IOF0 IOF1 IOF0
After Reset 00(H)
PMD1/0 PCMMode
PMD1 PMD0 The PCM are at
0 0 2048 kbit/s
0 1 4096 kbit/s
1 0 8192 kbit/s
1 1 Not used.
TIM 1/0 thesebits are taken into account only if bit TIM of COMPregister is at 1; in this case an interrupt is generatedperiodicallyand TIM 1/0 definesthe period
TIM1 TIM0 Period
0 0 1ms
0 1 8ms
1 0 64ms
1 1 250ms
OOF1/0 Output Offset 1/0.
These two bitsare associated withOOF2/9 ofOPOFRegister.
IOF1/0 InputOffset 1/0.
These two bitsare associated withIOF2/9 of IPOFRegister.
15/54
STLC5460
INPUT PCM OFFSET REGISTER (IPOF)
7 0
IOF9 IOF8 IOF7 IOF6 IOF5 IOF4 IOF3 IOF2
IOF9/2 InputPCM Offset 9 to 2.
Associated with IOF1/0, these ten bits indicate the delay between PFS signal and the
first bit of the frame,for each input
OUTPUT PCM OFFSET REGISTER (OPOF)
7 0
OOF9 OOF8 OOF7 OOF6 IOF5 OOF4 OOF3 OOF2
OOF9/2 Output PCM Offset9 to2.
Associated with OOF1/0 of complementary offset register, these ten bits indicate the
delay betweenbit 0 of theframe out going versus bit 0 of the frame incoming.
INPUT PCM SHIFT 1 (IPSH1)
7 0
0 P1SH2 P1SH1 P1SH0 0 P0SH2 P0SH1 P0SH0
After Reset 00(H)
After Reset 00(H)
After Reset 00(H)
P1SH2/0 PCM1 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtainthe totalshift of the frame of
PCM1.
P0SH2/0 PCM0 shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtainthe totalshift of the frame of
PCM0.
INPUT PCM SHIFT 2 (IPSH2)
7 0
0 P3SH2 P3SH1 P3SH0 0 P2SH2 P2SH1 P2SH0
P3SH2/0 PCM3 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtainthe totalshift of the frame of
PCM3.
P2SH2/0 PCM2 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtainthe totalshift of the frame of
PCM2.
OUTPUT PCM SHIFT 1 (OPSH1)
7 0
P1E P1SH2 P1SH1 P1SH0 P0E P0SH2 P0SH1 P0SH0
After Reset 00(H)
After Reset 00(H)
P1E OutputPCM1 Enable.
P1E = 0. PCM1 outputis at high impedance.
P1E = 1. PCM1 outputis enable.
16/54
P1SH2/0 PCM1 shift 2/0.
This number (0 to 7)is addedto output PCM offsetto obtain the totalshift of the frame of
PCM1.
P0E OutputPCM2 Enable.
P0E = 0. PCM0 outputis at high impedance.
P0E = 1. PCM0 outputis enabled.
P0SH2/0 PCM0 Shift 2/0.
This number (0 to 7) is added to output PCM offset to obtain the total shiftof the frame of
PCM0.
OUTPUT PCM SHIFT 2 (OPSH2)
7 0
P3E P3SH2 P3SH1 P3SH0 P2E P2SH2 P2SH1 P2SH0
P3E OutputPCM3 Enable.
P3E = 0. PMC3 outputis at high impedance.
P3E = 1. PCM3 outputis enabled.
P3SH2/0 PCM3 Shift 2/0.
This number (0 to 7) is added to output PCM offset to obtain the total shiftof the frame of
PCM3.
STLC5460
After Reset 00(H)
P2E OutputPCM2 Enable.
P2E = 0. PCM2 outputis at high impedance.
P2E = 1. PCM2 outputis enabled.
P2SH2/0 PCM2 shift 2/0.
Thisnumber(0to7)isaddedto outputPCMoffsettoobtainthetotalshiftoftheframeof PCM2
INPUT PCM ASSIGNMENTREGISTER (IPASS)
7 0
IP31 IP30 IP21 1P20 1P11 1P10 1P01 1P00
After Reset E4(H)
IP31/IP30 Incoming PCM3 Assignment.
IP31 IP30 Incoming PCM3 receives data from
0
0
1
1
0
1
0
1
Pin RxD0
Pin RxD1
Pin RxD2
Pin RxD3 (Defaultvalue)
IP21/IP20 Incoming PCM2 Assignment.
IP21 IP20 Incoming PCM2 receives data from
0
0
1
1
0
1
0
1
Pin RxD0
Pin RxD1
Pin RxD2 (Defaultvalue)
Pin RxD3
IP11/IP10 Incoming PCM1 Assignment.
IP11 IP10 Incoming PCM1 receives data from
0
0
1
1
0
1
0
1
Pin RxD0
Pin RxD1(Defaultvalue)
Pin RxD2
Pin RxD3
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