SGS Thomson Microelectronics STLC5046 Datasheet

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STLC5046

PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER

PRODUCT PREVIEW

PROGRAMMABLE MONOLITHIC 4 CHANNEL CODEC/FILTER

SINGLE+3.3VSUPPLY PIN STRAP / MCUCONTROLMODE A/µ LAW PROGRAMMABLE LINEARCODING (16 BITS) OPTION PCM HIGHWAY FORMAT AUTOMATICALLY

DETECTED:1.536 or 1.544MHz;2.048, 4.096, 8192 MHz

TX GAIN PROGRAMMING: 16dB RANGE; <0.1dB STEP

RX GAIN PROGRAMMING: 26dB RANGE; <0.1dB STEP

PROGRAMMABLE TIME SLOT ASSIGNMENT

DIGITALAND ANALOG LOOPBACKS SLICCONTROLPORT

STATICMODE (16 I/Os) DYNAMICMODE (12 I/Os + 4 CS)

64 TQFP PACKAGE PCMIN HI-Z MODE

DESCRIPTION

The STLC5046 is a monolithic programmable 4 channel codec and filter. It operateswith a single +3.3V supply. The analog interface is basedon a receive output buffer driving the SLIC RX input and on an amplifier input stage. Due to the single supply voltagea proper midsupplyreference level is generated internally by the device and all analog signalsare referred to this level (AGND). The

ORDERING NUMBER: STLC5046

PCM interface uses one common 8KHz frame sync. pulse for transmit and receive direction. The bit clock can be selectedbetween four standards:

1.536/1.544MHz, 2.048MHz, 4.096MHz, 8192MHz. Device programmability is achieved by means of 41 registers allowing to set the different parameterslike TX/RX gains, encoding law (A/µ), time slot assignment, independent chan- nels power up/down, loopbacks, PCM bits offset. Thanks to pinstrap option, the most significant of the above parameters can be set by hardware connection of dedicated pins. This allow to use this device also on line card without MCU on board. When pin strap option is selecteddifferent pins of the device will change their function (see pin description).

In MCU control mode the STLC5046 can be programmedvia serial interface running up to 4MHz.

One interruptoutputpin is also provided.

TQFP64

December 1999

This is preliminaryinformation on a new product now in development. Details are subject to change without notice.

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STLC5046

BLOCK DIAGRAM

VEEVCC

VFRO0

VFRO1

VFRO2

VFRO3

VFXI0

VFXI1

VFXI2

VFXI3

GR0

GX0

GX1

GX2

GX3

GR0

GR1

GR2

GR3

Post

Filter

Post

Filter

Post

Filter

Post

Filter

Anti-Alias

A/D

Anti-Alias

A/D

Anti-Alias

A/D

Anti-Alias

A/D

PLL

ABSOLUTE MAXIMUM RATINGS

VDD VSS SUB

D/A

sigma-delta

INTERPOLATORS

RX FILTERS

TX FILTERS

DECIMATORS

17-bit Bus

DIGITAL PROCESSORANALOG FRONTEND

data

CAP

PROGRAMMABLE

GAIN TX

contlol

ARBITER

A/u Law ENCODER

A/u Law

DECODER

GAIN RX

M0M1

8bit

PCM

INTERFACE

& SLOT ASSGN

8bit

8-bit Bus

Programmable functions

SERIAL

CONTROL

INTERFACE

SLIC

CONTROL

PORT

to analog FE

CONFIG.

REGISTERS

FS/FS0 MCLK TSX DX

IO11 IO10 IO9 IO8 IO7 IO6 / FS3 IO5 / FS2 IO4 / FS1 IO3 / PD3 IO2 / GR3 IO1 / PD2 IO0 / GR2 CS3 / GX3 CS2 / GX2 CS1 / GX1 CS0 / GX0

INT / AMU CCLK / GR1

CI / PD0 CO / GR0 CS / PD1

Symbol Parameter Value Unit

OUT

STG

LEAD

VCCto V VDDto V

EE SS

-0.5 to 4.6 V

-0.5 to 4.6 V Digital Input Input Pin Voltage -0.5 to 5.5 V Output Pin Current ±1mA Storage Temperature Range -65 to +150 °C Lead Temperature (soldering, 10s) 300 °C Analog Pin Input Voltage -0.5 to 4.6 V

OPERATINGRANGE

Symbol Parameter Value Unit

CC,VDD

Supply Voltage 3.3 ±5% V Operating TemperatureRange -40 to +85 °C

THERMAL DATA

Symbol Parameter Value Unit

th j-amb

Thermal Resistance Junction-Ambient 70 °C/W

2/27

PIN CONNECTION (Topview)

RES RES

INT/AMU

CS/PD1

CO/GR0

CI/PD0

CCLK/GR1

VSS VDD

DR DX

TSX

MCLK

FS/FS0

N.C.

RES

N.C.N.C.

1 2 3 4 5 6 7 8 9

12 13 14

15 16N.C.

17 18 19 20 21

IO6/FS3

IO8

IO7

IO9

IO10

IO11

VCC4M1VEE4

59 58 57 56 5455 53 52 51 50 49

22 23 24 25 26

271128 29 30 31 32

CS2/GX2

CS3/GX3

VEE2

VEE3

N.C.

STLC5046

VFRO3

N.C.

VFXI3

VCC3

VCC2

VFXI2

VFRO2

SUB

CAP

VFRO1

VFXI1

VCC1

VCC0

36 35

VFXI0 N.C.

34 33

VFRO0

N.C.

IO1/PD2

IO0/GR2

IO3/PD3

IO2/GR3

IO4/FS1

IO5/FS2

VCC5

VEE5

CS0/GX0

CS1/GX1

VEE1

VEE0

N.C.

D98TL405

PIN DESCRIPTION

I/O DEFINITION

Type Definition

AI Analog Input

AO Analog Output

ODO Open Drain Output

DI Digital Input

DO Digital Output

DIO Digital Input/Output DTO Digital Tristate Output DPS Digital Power Supply

APS Analog Power Supply

ANALOG

N. Name Type Function

33 VFRO0 AO Receive analog amplifier output channel 0. PCM data received on the programmed

39 VFRO1 AO Receive analog amplifier output channel 1. PCM data received on the programmed

42 VFRO2 AO Receive analog amplifier output channel 2. PCM data received on the programmed

48 VFRO3 AO Receive analog amplifier output channel 3. PCM data received on the programmed

Time Slot on DR input is decoded andappears at this output.

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STLC5046

PIN DESCRIPTION(continued)

ANALOG

N. Name Type Function

35 VFXI0 AI TX Input Amplifier channel 0. Typ 1MΩ input impedance 38 VFXI1 AI TX Input Amplifier channel 1. Typ 1MΩinput impedance 43 VFXI2 AI TX Input Amplifier channel 2. Typ 1MΩinput impedance 46 VFXI3 AI TX Input Amplifier channel 3. Typ 1MΩinput impedance 40 CAP AI AGND Voltage filter pin. A 100nF capacitor must be connected between ground and

POWERSUPPLY

25, 36, 37, 44,

45, 56,

26,30,

31, 50,

51,55

VCC/0/1/2/3/

4/5

VEE/0/1/2/3/

4/5

9 VDD DPS DigitalPower supply 3.3V, require 100nF decoupling capacitor to VSS. 8 VSS DPS DigitalGround

41 SUB DPS Substrate connection. Must be shorted together with VEE and VSS pins as close as

APS Total 6 pins: 3.3V analog power supplies, should be shorted together, require 100nF

APS Total 6 pins: analog ground, should be shorted together.

this pin.

decoupling capacitor to VEE.

possible the chip.

NOT CONNECTED

15, 16, 17, 18, 32, 34, 47, 49,

1,2,63 RES Reserved: must be left not connected.

N.C. Not Connected.

DIGITAL

27 M0 DI Mode select,see M1 54 M1 DI

13 MCLK DI Master Clock Input.

12 TSX ODO Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high

11 DX DTO Transmit PCM interface. It remains in high impedance state except during the

10 DR DI Receive PCM interface. It remains inactive except during the assigned receive time

61 IO7 DIO Slic control I/O pin #7. Can be programmed as input or output via DIR register.

M1 M0 Mode Select

0 1 Pin-strapmode: Basic functions selected by proper pin strapping 1 0 MCU mode: Device controlled via serial interface 0 0 Reset status 1 1 NotAllowed

Four possible frequencies can be used:

1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect thefrequency applied. This signal is also used as bit clock and it is used to shift data into and out of the DR and DX pins.

impedance state except when a time slot is active on the DX output. In this case TSX output pulls low to enable the backplane line driver.

assigned time slots during wich the PCM data byte is shifted out onthe rising edge of MCLK.

slots during which the PCMdata byte is shifted in on the falling edge of MCLK.

Depending on content of CONF register can be a static input/output or a dynamic input/output synchronized with the CSn output signals controlling the SLICs.

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PIN DESCRIPTION(continued) DIGITAL

N. Name Type Function

60 IO8 DIO Slic control I/O pin #8. (see IO7 description). 59 IO9 DIO Slic control I/O pin #9. (see IO7 description). 58 IO10 DIO Slic control I/O pin #10. (see IO7 description). 57 IO11 DIO Slic control I/O pin #11. (see IO7 description).

DIGITAL(DUAL MODE)

STLC5046

14 FS/FS0 DI MCU control mode: FS.

19 IO0/GR2 DIO/DI MCU control mode: IO0.

20 IO1/PD2 DIO/DI MCU control mode: IO1.

21 IO2/GR3 DIO/DI MCU control mode: IO2.

22 IO3/PD3 DIO/DI MCU control mode: IO3.

23 IO4/FS1 DIO/DI MCU control mode: IO4

24 IO5/FS2 DIO/DI MCU control mode: IO4.

62 IO6/FS3 DIO/DI MCU control mode: IO4.

Frame Sync. Pulse. A pulse or a squarewave waveform with an 8kHz repetition rate is applied to this pin to define the start of the receive and transmit frame. Effective start of the frame can be then shifted of up to 7 clock pulses indipendently in receive and transmit directions by proper programming of thePCMSH register. Pin-strap control mode: FS0. Frame Sync. pulse of channel #0. One MCLK cycle long , starts PCM datatransfer in the Time Slot following its falling edge (Short Frame Delayed Timing).

Slic control I/O pin #0. Can be programmed as input or output via DIR register. Depending on content of CONF register can be a static input/output or a dynamic input/output synchronized with the CSn output signals controlling the SLICs. Pin-strap control mode: GR2. Receive gain programming channel 2: 1: Receive gain = = -0.8dB 0: Rec. gain = -4.3dB

Slic control I/O pin #1. (see IO0 description). Pin-strap control mode: PD2. Power Down command channel 2: 1: Channel2 Codec is in power down. (equivalent to CONF reg bit2 = 1) 0: Channel2 Codec is in power up. (equivalent to CONF reg. bit2 = 0)

Slic control I/O pin #2. (see IO0 description) Pin-strap control mode: GR3. Receive gain programming channel 3. (see GR2 description)

Slic control I/O pin #3. (see IO0 description). Pin-strap control mode: PD3. Power Down command channel 3. (see PD2 description)

Slic control I/O pin #4. (see IO0 description). Pin-strap control mode: FS1. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in the Time Slot following its falling edge (Short Frame Delayed Timing).

Slic control I/O pin #5. (see IO0 description). Pin-strap control mode: FS2. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in the Time Slot following its falling edge (Short Frame Delayed Timing).

Slic control I/O pin #6. (see IO0 description). Pin-strap control mode: FS3. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in the Time Slot following its falling edge (Short Frame Delayed Timing).

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STLC5046

PIN DESCRIPTION(continued)

N. Name Type Function

28 CS0/GX0 DO/DI MCU control mode: CS0.

Slic CS control #0. Depending on CONF reg. content can be a CS output for SLIC #0 or a static I/O. When configured as CS output it is automatically generated by the Codec with a repetition time of 31.25µs. In this mode also the IO proper data in and outsynchronous with CS. Pin-strap control mode: GX0. Transmit gain programming channel 0: 1: Transmitgain = 0dB 0: Transmitgain = -3.5dB

29 CS1/GX1 DO/DI MCU control mode: CS1:

Slic CS control #1, (see CS0 description). Pin-strap control mode: GX1. Transmit gain programming channel 1 (seeGX0 description)

53 CS2/GX2 DO/DI MCU control mode: CS2.

Slic CS control #2, (see CS0 description). Pin-strap control mode: GX2. Transmit gain programming channel 2 (seeGX0 description)

52 CS3/GX3 DO/DI MCU control mode: CS3.

Slic CS control #3, (see CS0 description). Pin-strap control mode: GX3. Transmit gain programming channel 3 (seeGX0 description)

4 CS/PD1 DI/DI MCU control mode: CS.

Chip Select of Serial Control Bus. When this pin is low control information can be written to or read from the device via the CI and CO pins. Pin-strap control mode: PD1. Power Down command channel 1. (see PD2 description).

7 CCLK/GR1 DI/DI MCU control mode: CCLK.

Clock of Serial Control Bus. This clock shifts serial control ilnformation into or out of CI or CO when CS input is low depending on the current instruction. CCLK may be asyncronous with the other system clocks. Pin-strap control mode: GR1. Receive gain programming ch. 1, (see GR2 description).

6 CI/PD0 DI/DI MCU control mode: CI.

Control Data Input of Serial Control Bus. Control data is shifted in the device when CS is low and clocked by CCLK. Pin-strap control mode: PD0. Power Down command channel 0. (see PD2 description).

5 CO/GR0 DTO/DI MCU control mode: CO.

Control Data Output of Serial Control Bus. Control data is shifted out the device when CS is low and clocked by CCLK. During the first 8 CCLK pulses the CO pin is H. I., valid data are shifted out during thefollowing 8 CCLK pulses. Pin-strap control mode: GR0. Receive gain programming ch. 0, (see GR2 description).

3 INT/AMU ODO/DI MCU control mode: INT.

Interrupt output (open drain), goes low when a data change has been detected in the I/O pins. One mask registers allow to mask any I/O pin.Interruptis reset when the I/O register is read. Pin-strap control mode: AMU. A/µlaw selection: AMU=0: µ law AMU=1: A law, even bit inverted

are synchronized and carry

11..0

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STLC5046

FUNCTIONAL DESCRIPTION

POWERON INITIALIZATION When power is first applied it is recommended to

reset the device by forcing the condition M1.0=00, in order to to clear all the internal registers. In MCU mode M0 is set steadilyLow and the device is reset by applying a negativepulse to M1 (its operative level in MCU mode is High); same result can be obtained by writing an High level into the controlbit RESof theCONF register. In Pin-strapmode M1 is set steadily Low and the device is reset by applying a negative pulse to M0 (its operative level in Pin-strap mode is High); at the end of the Reset phase (M0=High) the device is programmed according to the logical configurationof the control pins. During the Reset condition all the I/On and CS_n pins are set as inputs , DX is set in high impedanceandall VFROn outputsare forcedto AGND.

POWERDOWN STATE Each of the four channel may be put into power

down mode by setting the appropriate bit in the CONF register or strapping to VDD the proper pin. In this mode the eventual programmed DX channel is set in high impedancewhile the VFRO outputs are forced to AGND. In Pin strap mode the value forced on the input pin is internally updated everyFS signal.

TRANSMITPATH The analog VFXI signal through an amplifier

stage is applied to a PCM converter and the cor-

Figure 1. Transmit path.

respondingdigital signal is sent to DX output. In MCU mode, the amplifier gain can be pro-

grammed with two different values by means of TXG Reg.: 0dBor +3.52dB.

A programmablegain block after the A/D conversion allows to set transmit gain in 12dB range, with steps <0.1dB by writing proper code into GTXn register.

Setting GTXn=00h , the transmitted signal is muted, i.e. an idle PCM signal is generated on DX.

A/µ coding Law is selected by bit5 (AMU) of CONF reg.

Setting LIN=1 (bit6 of CONFreg.) the Linear coding Law is selected (16bits); in this case the signal sent on DX will take two adjacent PCM time slots.

In Pin-strap mode, the amplifier gain is set to 0dB; only two values of Transmitgain can be selected according to the level of GXn control input (in Pin-strap):

GXn=1 selects the gain corresponding to GTXn=FFh (0dB)

GXn=0 selects the gain corresponding to GTXn=8Fh ( -3.5dB)

Different gain value is obtained through proper voltage divider.

A/µ codingLaw is selected according to AMUpin level:

AMU=0 µ-Law selected. AMU=1 A-Law selected. VFXI input must be AC coupled to the signal

source; the voltage swing allowed is 1.0Vpp

VFXI

Ω

AGND

Figure 2. Receive path.

TXG: 0dB

+3.52dB

for TXG=0dB; GX=0dB (FF)

600Ω

-15dBm|

0dBm0

8 bit linear 1/4to1

Σ∆

conv.

Σ∆

conv.

8 bit linear 1/4 to 1

RXG: 0dB

-1.94dB

-4.44dB

-7.96dB

-13.98dB

for RXG=0dB; GR=0dB (FF)

0dBm0 => -3dBm|

600Ω

VFRO

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STLC5046

Figure 3. MCU mode: Time - Slot Assignment

FS FS

TS0 TS23/31/61/127

DXAnReg.

DRAnReg.

Receive Time Slot Transmit Time Slot

D7..................D0 D7...................D0

when the preamplifiergain is set 0dB or 0.66Vpp if the gain is set to 3.52dB (MCU mode only); higher levels must be reduced through proper dividers.

Typical impedanceof VFXIinputis 1Mohm.

RECEIVEPATH The received PCM signal DR through the de-

coder section, the gain select block and the D/A converter is converted in an analog signal which is transfered to VFRO output through an amplifier stage.

In MCU mode a programmablegain block before the A/D conversion allows to set receive gain in 12dB range, with steps <0.1dB by writing proper code into GRXn register.

The amplifier gain can be programmed with five different values by means of RXG Register: 0dB -1.94dB -4.44dB -7.96dB -13.98dB.

Setting GRXn=00h , the receive signal is muted and VFROoutput is set to AGND.

A/µ coding Law is selected by bit5 (AMU) of CONF reg.

Setting LIN = 1 (bit6 of CONF reg.) the Linear coding Law is selected (16bits); in this case the signal receivedon DR will take two adjacentPCM time slots.

in pin Strap mode only two values of Receive Gain can be selected according to the level of GRn controlinput (in Pin Strap)

GRn = 1 selectsthe gaincorrespondingto GRXn = E2h, RXG = 0dB (-0.8dB)

GRn = 0 selectsthe gaincorrespondingto GRXn = AFh,RXG = -1.94dB(-4.3dB)

Different gain value is obtained through proper voltage divider.

A/µ codingLaw is selected according to AMUpin level:

AMU=0 µ-Law selected. AMU=1 A-Law selected. VFRO output, referred to AGND must be AC

coupled to the load, referredto VSS, to preventa DC currentflow.

VFRO has a drive capability of 1.0mA (peak value),with a max AC swingof 2Vpp.

In order to get the best noise performances it is recommendedto keep the GRX value as closeas possible to the maximum (FFh) setting properly the additionalattenuationby meansof RXG.

PCM INTERFACE The STLC5046 dedicate five pins (sixin pin strap

mode) to the interface with the PCM highways. MCLK represents the bit clock and is also used

by the device as a source for the clock of the internal Sigma Delta converter timings. Four possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating frequency is automatically detected by the device when both MCLK and FS are applied. MCLK is synchronizing both the transmitdata (DX) and thereceive data (DR).

MCU mode:

The Frame Sync. signal FS is the common time base for all the four channels; Short (one MCLK period) or Long (more than one MCLK period) FS are allowed.

Transmit and Receive programmable Time-Slots are framedto an internal sync. signal that can be coincident with FS or delayed of 1 to 7 MCLK cycles depending on the programming of PCMSH

8/27

Figure 4. Pin Strap mode: TimeSlot Assignment

Receive /Transmit

Time Slot

CH0 CHn CHm

STLC5046

D7..................D0 D7...................D0

FS0

FSn

mains in high impedance state except during the assigned time slots during which the PCM data byte is shifted out on the rising edge of MCLK. The four channels can be shifted out in any possible timeslot as defined by the DXA0 to DXA3 registers. If one codec is set in Power Down by software programmingthe correspondingtimeslot is set in High Impedance. When linear coding mode is selectedby CONF register programming the output channel will need two consecutive timeslots(see registerdescription).

DR represent the receive PCM interface. It remains inactive except during the assigned time slots during wich the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible timeslot as defined by the DRA0 to DRA3 registers.

Pin StrapMode

When pinstrap mode is selected, dedicated Frame Sync. FS3..0 are provided on dual function pins:

MCU Pin-strap Pin

FS FS0 12 IO4 FS1 17 IO5 FS2 18 IO6 FS3 48

The PCMSHregister cannot be accessed,therefore the beginning of the transmit and receive frame is identified by the rising edge of the FSn signal.

Each channel has its dedicated Frame Sync.signal FSn. Short or Long frame timing is automatically selected; depending on the FS signal applied to FS0 input. The assigned Time Slot

TS23/31/61/127D7...................D0

FSm

(Transmit and Receive) takes place in the 8 MCLK cycles following the falling edge of FSn in case of Short Frame or the rising edge in case of Long Frame. If one codec is set in Power Down by proper pin strap configuration the corresponding timeslot is not loaded and the VFRO output is kept at steady AGND level.

Finally by means of the LOOPB register is possible to implement a digital or analog loopback on any of the selected channels.

TSX represent the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DX output. In this case TSX output pulls low to enable the backplane line driver. Should be strapped to VSS when not used.

Table 1. Control byte structure.

First Byte (Address)

76543210

R/W D/S A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

R/W = 0: Write Register R/W = 1: Read Register D/S = 0:Single byte D/S = 1:Two bytes A5..A0: Register Address

CONTROL INTERFACE STLC5046 has two control modes, a microproc-

essor control mode and a pin strap controlmode. The two modes are selected by M0 and M1 pins. When M0 = low, M1 = high (MCU control mode) the MCU port is activated;and the 41 registers of the device can be programmed.When M0 = high, M1 = low (Pin-strap mode) the microprocessor control port is disabled and some of the digital pins change their function allowing to perform a very basic programmingof the device.

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