SGS Thomson Microelectronics STE100P Datasheet

10/100 FAST ETHERNET 3.3V TRANSCEIVER

1.0 DESCRIPTION

The STE100P, also referred to as STEPHY1, is a highperformance Fast Ethernet physicallayer interfacefor 10BASE-Tand 100BASE-TX applications. It was designedwith advancedCMOStechnology to provide a MediaIndependent Interface(MII) for easy attachment to 10/100 Media Access Controllers (MAC)and a physical mediainterfacefor 100BASETXof IEEE802.3u and 10BASE-T ofIEEE802.3. TheSTEPHY1supports both half-duplexand full-duplexoperation,at 10 and100 Mbpsoperation. Itsoperating mode can be set using auto-negotiation, paralleldetection or manual control.It alsoallowsfor the support of auto-negotiation functions for speed andduplex detection.

2.0 FEATURE

2.1 Industry standard

n IEEE802.3u 100BASE-TX and IEEE802.3

10BASE-T compliant

STE100P

PRODUCT PREVIEW

PQFP64

ORDERING NUMBER: STE100P

n Support forIEEE802.3x flow control n IEEE802.3u Auto-Negotiation support for

10BASE-T and 100BASE-TX

n MII interface n Standard CSMA/CD or full duplex operation

supported

Figure 1. BLOCK DIAGRAM

LEDS

TX_CLK TXD[3:0] TX_ER TX_EN

MDC MDIO

Serial Management

RXD[3:0] RX_ER RX_DV

RX_CLK

HW configuration pins

LEDS

MII

Interface / Controller

HWConfig PowerDown

100Mb/s

4B/5B

10Mb/s

100Mb/s

4B/5B

10Mb/s

Scrambler

NRZ ToManchester Encoder

REGISTERS

Descrambler CodeAlign

NRZ ToManchester Encoder

TX Channel

Parallelto Serial

RX Channel

Serial to Parallel

NRZ ToNRZI Encoder

Link Pulse Generator

Auto Negotiation

NRZI ToNRZ Decoder

Link Pulse Detector

Binary ToMLT3 Encoder

Loopback

Binary ToMLT3 Decoder

Clock Recovery

10 TX Filter ClockRecovery

10 TX Filter

Adaptive Equalization

BaseLine Wander

SMART Squelch

TRANSMITTER 10/100

Clock Generation

RECEIVER 10/100

TXP TXN

System Clock

RXP RXN

January 2000

This ispreliminary information on a new product now in development. Details are subject to change without notice.

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STE100P

2.2 Physical Layer

n Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T n Provides Full-duplex operation on both 100Mbps and 10Mbps modes n Provides Auto-negotiation(NWAY) function of full/half duplex operationfor both 10 and 100 Mbps n Provides MLT-3 transceiver with DC restoration for Base-line wander compensation n Provides transmit wave-shaper, receive filters, and adaptive equalizer n Provides loop-back modes for diagnostic n Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder n Supports external transmit transformer with turn ratio 1:1 n Supports external receive transformer with turn ratio 1:1

2.3 LED Display

n Provides 2 kinds of LED display mode:

•First mode - 3 LED displays for ♦ 100Mbps(on) or 10Mbps(off) ♦ Link(Keeps on when link ok) or Activity(Blink with10Hz whenreceiving or transmitting but not

collision)

♦ FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding)

•Second mode – 4 LED displays for ♦ 100 Link(On when 100M link ok) ♦10 Link(On when 10M linkok) ♦ Activity (Blink with 10Hz when receiving or transmitting) ♦FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding)

2.4 Miscellaneous

n Standard 64-pin QFP package pinout

Figure 2. System Diagram of the STE100P Application

Serial

EEPROM

MAC

Device

PCI Interface

Boot ROM

STE100P

STEPHY1

25 MHz Crystal

LEDs

RJ-45

Transformer

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3.0 PIN ASSIGNMENT DIAGRAM Figure 3. Pin Connection4.Pin Description

CRS

TDS/MDIR

VCCE/I

CFG1

CFG0VCCA

MF4 MF3

MF1 MF0 FDE

GNDE/I

GNDA

VCCA

GNDA

X2 X1

VCCA

GNDA

IREF

1 2 3

4 5 6 7 8 9

12 13 14

15 16VCCA

17 18 19 20 21

59 58 57 56 5455 53 52 51 50 49

22 23 24 25 26

COL

TXD3

TXD2

TXD1

TXD0

TX_EN

TX_CLK

TX_ER/TXD

RX_ER/RXD

GNDE/I

271128 29 30 31 32

RX_CLK

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

STE100P

RX_DV RXD0 RXD1 VCCE/I RDX2 RDX3 MDC MDIO GNDE VCCE IEDR10 IEDTR IEDL IEDC IEDS SCAN_EN

RXN

RXP

GNDA

TXP

VCCA

TXN

GNDA

GNDE

TEST

RESET

VRDWN

RIP

N.C.

D99TL457

4.0 PIN DESCRIPTION Table 1. Pin Description

Pin No. Name Type Description

MII Data Interface

59 58 57 56 55

TXD4 TXD3 TXD2 TXD1 TXD0

54 TX-EN I Transmit Enable. Thc MAC asserts this signal when it drives valid data on the

53 TX-CLK I/O Transmit Clock. Normally the STE100P drives TX-CLK. Refer to the Clock

52 TX-ER I Transmit Coding Error. The MAC asserts this input when an error has occurred

I Transmit Data. The Media Access Controller (MAC) drives data to the STE100P

using these inputs. TXD4 is monitored only in Symbol (5B) Mode. These signals must be synchronized to the TX-CLK.

TXD inputs. This signal mustbe synchronized to the TX-CLK.

Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

in the transmit data stream. Whenthe STE100P is operating at 100 Mbps, the STE100P responds by sending invalid code symbols on the line. . In Symbol (5B) Mode this pin is also equivalent to TXD4.

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STE100P

Table 1. Pin Description

Pin No. Name Type Description

42 43 44 46 47

48 RX-DV O Receive Data Valid. ThcSTE100P asserts This signal when it drives valid data

51 RX-ER O Receive Error. The STE100P asserts this output when it receives invalid

49 RX-CLK O Receive Clock. This continuous clock provides reference for RXD. RXDV,and

60 COL O Collision Detected. The STE100P asserts this output when detecting acollision.

61 CRS O Carrier Sense. During half-duplex operation (PR0:8=0), the STE100P asserts

MII Control Interface

41 MDC I Management Data Clock. Clock for the MDIO serial data channel. Maximum

RXD4 RXD3 RXD2 RXD1 RXD0

O Receive Data. Thc STE100P drives received dataon these outputs,

synchronous to RX-CLK. RXD4 is driven only in Symbol (5B) Mode.

on RXD. This output is synchronous to RX-CLK.

symbols from thenetwork. This signal is synchronous toRX-CLK. InSymbol (5B) Mode this pin is also equivalent to RXD4.

RXER signals. Refer to the Clock Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

This output remains High for the duration of the collision. This signal is asynchronous and inactive during full-duplex operation.

this output when either transmit or receive medium is non idle. During full duplex operation (PR0:8=1), CRS is asserted only when the receive medium is non-idle.

frequency is 2.5 MHz.

40 MDIO I/O Management DataInput/Output, Bi-directional serial data channel for PHY

communication.

62 MDINT OD Management DataInterrupt. When any bit in PR18= 1, an active Low output

on this pin indicates statuschange in the corresponding bits in PR17. Interrupt is cleared by reading Register PR17

Physical (Twisted Pair) Interface

12 OSC1 I 25 MHz reference clock input. When an external 25MHz crystal is used, thispin

will be connected to one terminal of it. If an external 25 MHz clock source of oscillator is used, then this pin will be theinput pin of it.

11 OSC2 O 25 MHz reference clock output. When an external 25MHz crystal is used, this pin

will be connected to another terminal of if. Ifan external clock source is used, then this pin should be left open.

21 23

19 18

15 Iref O Reference Resistor connecting pin for reference current, directly connects a 5KΩ

TXP TXN

RXP

RXN

O The differential Transmit outputs of 100BASE-TX or 10BASE-T, these pins

directly output to the transformer.

I The differential Receive inputs of 100BASE-TX or 10BASE-T,these pins directly

input from the transformer.

± 1% resistor to Vss.

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Table 1. Pin Description

Pin No. Name Type Description

STE100P

37-33 LED/PAD

Pins

37 LED10/

PAD[4]

36 LEDTR/

PAD[3]

35 LEDL

/PAD[2]

34 LEDC

PAD[1]

I/O Pins 33-37 are multifunction pins used as LED outputs and PHY Address sensing

inputs for multiple PHY applications. PHY address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon power-up/reset. If a given PAD input is resistively pulled low, the corresponding LED output will be configured as an active high driver.Conversely, if a given PAD input is resistively pulled high then the corresponding LEDoutput willbe configured as anactive low driver.

These outputs are standard CMOS voltage drivers and not open-drain.

I/O LED display for 10Ms/s link status. This pin will be driven on continually when

10Mb/s network operating speed is detected. The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during power up/reset.

LED display for Tx/Rx Activity status. This pin will be driven on with 10 Hz blinking frequency when either effective receiving or transmitting is detected. The status of thispin is latched into the PR20 bit 6 during power up/reset.

I/O LED display for Link Status. This pin will be driven on continually when a good

Link test is detected. The status of thispin is latched into the PR20 bit 5 during power up/reset.

I/O LED display for Full Duplex or Collision status. This pin will be driven on

continually when a full duplex configuration is detected. This pin will be driven on with 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. The status of thispin is latched into the PR20 bit 4 during power up/reset.

33 LEDS

PAD[0]

31 CFG0 I Configuration Control 0.

32 CFG1 I Configuration Control 1.

Pin No. Name Type Description

29 RESET I Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset

63 RIP O Reset In Progress. This output is used to indicate when the device has

I/O LED display for 100Ms/s link status. This pin will be driven on continually when

100Mb/s network operating speed is detected. The status of thispin is latched into the PR20 bit 3 during power up/reset.

When A/N is enabled, CFG0 determines operating mode advertisement capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table2) When A/N is disabled, CFG1 disables MLT3 and directly affects PR19:0 When CFG0 is Low,MLT3 encoder/decoder is enabled and PR19:1 =0. When CFG0 is High, MLT3 encoder/decoder is bypassed and PR19:1 = 1.

When A/N is enabled, CFG1 determines operating mode advertisement capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table2) When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0 bit 14. When CFG1 is Low,Loopback mode is disabled and PR0:14 = 0. When CFG1 is High, Loopback mode is enabled and PR0:14 = 1.

the STE100P. During Power-up, the STE100P will be reset regardless of the state of this pin, and this reset will not be complete until after >1ms.

completed power-up/reset and the registers and functions can be accessed. When RIP is High, power-up/reset has been successful and the device can be used normally When RIP is Low, device reset is not complete.

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STE100P

Table 1. Pin Description

Pin No. Name Type Description

30 PWRDWN I Power Down. WhenHigh, forces STE100P into Power Down mode. This pin is

5 4 3 2 1

6 FDE I Full-Duplex Enable.

MF0 MF1 MF2 MF3 MF4

OR’ed with the Power Down bit (PR0:11). During the Power Down mode, TXP/ TXN outputs and all LED outputs are 3-stated, and the MII interface isisolated.

I Multi-Function pins. Each MFpin internally drives different configuration

functions. The functions of the five MF inputs are as follows:

Pin Function Register & Bit Affected

MF0 Auto-Negotiation PR0:12 ANE MF1 Enable NRZ-NRZI conversion PR19:7 ENRZI MF2 4B/5B Coding Enable PR19:6 EN4B5B MF3 Scrambler Operation Disable PR19:0 DISCRM

mf4 MF4 10/100 Mbps Speed Select PR0:13 SPSEL

The logic level of MF0-4 will determine the value that the affected bits will have upon reset of the STE100P. The operating functions of CFG0, CFG1, and FDE change depending on the state of MF0 (Auto-Negotiation enabled ordisabled). Table 2 shows the relationship between CFG0, CFG1and FDE .

When A/N is enabled, FDE determines full-duplex advertisement capability in combination with CFG0and CFG1. (SeeTable 2) When A/N is disabled, FDE directly affects full-duplex operation and determines the value of PR0 bit 8 (Full/Half Duplex Mode Select). When FDE is High, full-duplex is enabled and PR0:8 = 1. When FDE is Low, full-duplex is disabled and PR0:8 = 0.

Digital Power Pins

38, 45, 64 VCCE, VCCE/I 7, 25, 39, 50 GNDE, GNDE/I

Analog Power Pins

9, 13, 16, 17, 22 VCCA 8, 10, 14, 20, 24 GNDA

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STE100P

5.0 HARDWARE CONTROL INTERFACE

5.1 Operating Configurations

TheHardware Control Interfaceconsistsof the MF<4:0>,CFG <1:0> andFDE input pinsas wellas theLED/ PADpins. This interfaceis used toconfigureoperatingcharacteristicsof theSTE100P. The Hardware Control Interfaceprovides initialvalues for the MDIO registers,andthen passescontroltothe MDIO Interface. Individualchip addressing via the LED/PAD pins allowsmultipleSTE100P devicesto share the MII interface.Table 2 showshow to setup the desiredoperatingconfigurationsusing the Hardware ControlInterface.

Table 2. Operating Configurations / Auto-Negotiation Enabled

Desired

Configuration

Advertise All 1 1 1 1 1 1 1 Advertise 100 HD 1 0 0 0 1 0 0 Advertise 100 HD/FD 1 0 1 1 1 0 0 Advertise 10 HD 0 1 0 0 0 0 1 Advertise 10 HD/FD 0 1 1 0 0 1 1

CFG0 CFG1 FDE [8] TXF [7] TXH [6] 10F [5] 10H

Input Value PR4 Register Bits Affected

Advertise 10/100 HD 1 1 0 0 1 0 1

Note: If pin 5, MF0 = 0, or ANE (pinMF0 /PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated

in the table describing register PR4.

5.2 LED / PHY Address Interface

TheLED output pins can beusedto driveLED’s directly,or can be usedto providestatusinformationto a networkmanagementdevice. The activestate of each LED output driver is dependenton thelogic levelsampled by the corresponding PHYaddress inputupon power-up/reset.For example, if a given PADinput isresistively pulledlow thenthe corresponding LEDoutputwill be configured as an active highdriver. Conversely,if a given PADinputis resistivelypulledhighthenthecorrespondingLEDoutputwill be configuredasan activelow driver.

These outputs are standard CMOS drivers and not open-drain.

The STE100P PAD[4:0]inputs provide up to 32 unique PHY address options. An address selection of all

zeros(00000) willresultin aPHY isolation condition asa result of power-on/reset

, asdocumented forPR0

bit11. SeeSection 7 for more detaileddescriptions of deviceoperation.

6.0 REGISTERS AND DESCRIPTORS DESCRIPTION

Thereare 11 registerswith 16 bits each supportedforSTE100P. This includes7 basicregisterswhich are defined according to the clause 22 “Reconciliation Sub-layer and Media Independent Interface” and clause 28 “PhysicalLayer link signalingfor 10 Mb/s and 100Mb/s Auto-Negotiationon twisted pair” ofIEEE802.3ustandard.

Thereare 11 registerswith 16 bitseach supportedfor theSTE100P.Theseinclude 7 basicregisterswhichare defined accordingto the clause 22 “ReconciliationSublayer and Media Independent Interface” and clause28 “PhysicalLayer link signalingfor 10 Mb/s and 100Mb/s Auto-Negotiationon twisted pair” ofIEEE802.3ustandard.

In addition, there are4 specialregistersfor advancedchip controland statusinformation.

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STE100P

6.1 Register List

Table 3. Register List

Address Reg. Index Name Register Descriptions

0 PR0 XCR XCVR Control Register 1 PR1 XSR XCVR Status Register 2 PR2 PID1 PHY Identifier 1 3 PR3 PID2 PHY Identifier 2 4 PR4 ANA Auto-Negotiation Advertisement Register 5 PR5 ANLPA Auto-Negotiation Link Partner Ability Register

6 PR6 ANE Auto-Negotiation Expansion Register 17 PR17 XCIIS XCVR Configuration Information and InterruptStatus Register 18 PR18 XIE XCVR Interrupt Enable Register 19 PR19 100CTR 100BASE-TX PHY Control/Status Register 20 PR20 XMC XCVR Mode Control Register

6.2 Register Descriptions Table 4. Register Descriptions

Bit # Name Descriptions Default Val RW Type

PR0- XCR, XCVR Control Register. The default values on power-up/resetare as listed below.

15 XRST Reset control.

1: Device will be reset. This bit will be cleared by STE100P itself after the reset is completed.

14 XLBEN Loop-back mode select.

1: Loop-back mode is selected.

13 SPSEL Network Speed select. This bit’s selection will be ignored if

Auto-Negotiation is enabled(bit 12 of PR0 = 1). 1:100Mbps is selected. 0:10Mbps is selected.

12 ANEN Auto-Negotiation ability control.

1: Auto-Negotiation function is enabled. 0: Auto-Negotiation is disabled.

11 PDEN Power-down mode control.

1: Power-down mode is selected. Setting this bit puts the

STE100P into power-down mode. During the power-down mode, TXP/TXNand all LED outputs are 3-stated, and the MII interface is isolated.

0 R/W

1 R/W

0 R/W

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Table 4. Register Descriptions

Bit # Name Descriptions Default Val RW Type

STE100P

10 ISOEN 0 – Normal operation.

1 – IsolatePHY from MII. Setting this control bit isolates the STE100P from the MII,with the exception of the serialmanagement inter-face. When this bit is asserted, the STE100Pdoes not respond to TXD[3:0], TX-EN, and TX-ER inputs, and it presents a high impedance on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and CRS outputs. This bitis initialized to 0 unless the configuration pins for the PHY address are set to 00000h during power-up or reset.

9 RSAN Re-Start Auto-Negotiation process control.

1: Auto-Negotiation process will be re-started. This bit will be

cleared by STE100P itself afterthe Auto-negotiation restarted.

8 DPSEL Full/Half duplex mode select.

1: full duplex mode is selected. This bit will be ignored if Auto-

Negotiation is enabled (bit 12 of PR0 = 1).

7 COLEN Collision test control.

1: collision test is enabled. 0: normal operation This bit, when set, causes the COL signal to be asserted as a result of the assertion of TX _EN within 512 BT.De-assertion of TX_EN will cause the COL signal to be de-asserted within 4BT.

6~0 --- Reserved 0 RO

R/W = Read/Write able. RO = Read Only.

0 R/W

PR1- XSR, XCVR Status Register. All the bits of this register are read only.

15 T4 100BASE-T4 ability.

Always 0, since STE100P hasno T4ability.

14 TXFD 100BASE-TX full duplex ability.

0RO

1RO

Always1, sinceSTE100P has the100BASE-TX fullduplex ability.

13 TXHD 100BASE-TX half duplex ability.

Always1,since STE100Phas the 100BASE-TXhalfduplex ability.

12 10FD 10BASE-T full duplex ability.

Always 1, since STE100P has10Base-T full duplex ability.

11 10HD 10BASE-T half duplex ability.

Always 1, since STE100P has10Base-T half duplex ability.

10~7 --- Reserved 0 RO

6 MFPS MF Preamble Suppression

1 =Accepts management frames with pre-amble suppressed. 0 = Will not accept management frames with preamble

suppressed. Thevalue of thisbit iscontrolled by bit 1 of PR20. Its default of 1 indicates that the SFEPHY1 accepts management frame without preamble. A minimum of 32 preamble bits are required following power-on or hardware reset. One IDLE bit is required between any two management transactions as per IEEE 802.3u specification.

1RO

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