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PRELIMINARY DATA
July 2001
STD8NS25
N-CH A NNEL 250V - 0.38Ω - 8A DPAK
MESH OVERLAY™ MOSFET
■ TYPICAL R
DS
(on) = 0.38 Ω
■ EXTREMELY HIGH dv /d t C APABILITY
■ 100% AVALANCHE TESTED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for
lighting applications.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLI ES ( SMPS)
■ DC-DC CONVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
(•)Pu l se width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STD8NS25 250 V < 0.45 Ω 8 A
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
250 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
250 V
V
GS
Gate- source Voltage ± 20 V
I
D
Drain Current (continuos) at TC = 25°C
8A
I
D
Drain Current (continuos) at TC = 100°C
5A
I
DM
(●)
Drain Current (pulsed) 32 A
P
TOT
Total Dissipation at TC = 25°C
80 W
Derating Factor 0.64 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns
E
AS
(2)
Single Pulse Avalanche Energy 209 mJ
T
stg
Storage Temperature –65 to 150 °C
T
j
Max. Operating Junction Temperature 150 °C
(1) ISD≤ 8A, di/dt≤300 A/µs, VDD≤ V
(BR)DSS
, Tj≤ T
jMAX
(2) Start i ng Tj = 25°C, I
AR
= 50A, VDD=20 V
INTERNAL SCHEMATIC DIAGRAM
DPAK
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