STD7NS20
N - CHANNEL 200V - 0.35Ω - 7A - DPAK
MESH OVERLAY MOSFET
PRELIMINARY DATA
■
TYPICAL R
DS(on)
= 0.35
Ω
■
EXTREMELY HIGH dv/dt CAPABILITY
■
100% AVALANCHE TESTED
■
VERY LOW INTRINSIC CAPACITANCES
■
GATE CHARGE MINIMIZED
■
FOR TAPE & REEL AND OTHER
PACKAGING OPTIONS CONTACT SALES
OFFICES
DESCRIPTION
This power MOSFET is designed using the
company’s consolidated strip layout-based MESH
OVERLAY process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
■
HIGH CURRENT SWITCHING
■
UNINTERRUPTIBLE PO WER S UPPLY (UPS)
■
DC/DC COVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT.
®
INTERNAL SCHEMATIC DIAGRAM
November 1998
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0) 200 V
V
DGR
Drain- gate Voltage (RGS = 20 kΩ)
200 V
V
GS
Gate-source Voltage ± 20 V
I
D
Drain Current (continuous) at Tc = 25 oC7A
I
D
Drain Current (continuous) at Tc = 100 oC4.4A
I
DM
(•) Drain Current (pulsed) 28 A
P
tot
Total Dissipation at Tc = 25 oC45W
Derating Factor 0.37 W/
o
C
dv/dt(
1
) Peak Diode Recovery voltage slope 5 V/ns
T
stg
Storage Temperature -65 to 150
o
C
T
j
Max. Operating Junction Temperature 150
o
C
(•) Pulse width limited by safe operating area (1) ISD ≤ 7A, di/dt ≤ 300 A/µs, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX
First Digit of the Datecode Being Z or K Identifies Silicon Characterized in this Dat asheet
TYPE V
DSS
R
DS(on)
I
D
STD7NS20 200 V < 0.40 Ω 7 A
1
3
DPAK
TO-252
(Suffix "T4")
1/5