SGS Thomson Microelectronics STP5NK40ZFP, STD5NK40ZT4, STD5NK40Z-1, STD5NK40Z Datasheet
1/13February 2003
STP5NK40Z - STP5NK40ZFP
STD5NK40Z - STD5NK40Z-1
N-CHANNEL 400V - 1.47Ω - 3A TO-220/TO-220FP/DPAK/IPAK
Zener-Protected SuperMESH™Power MOSFET
■ TYPICAL R
DS
(on) = 1.47 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ GAT E CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VER Y GO OD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperME SH™ series is obtained through an
extreme optimization of S T’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special careis taken to ensure a very good dv/dt capability for the
most demanding applications. Such series com plements ST full range of high voltage MOSFETs including revolutionary MDm es h™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
■ LI GHTING
ORDERING INFORMATION
TYPE V
DSS
R
DS(on)
I
D
Pw
STP5NK40Z
STP5NK40ZFP
STD5NK40Z
STD5NK40Z-1
400 V
400 V
400 V
400 V
< 1.8 Ω
< 1.8 Ω
< 1.8 Ω
< 1.8 Ω
3A
3A
3A
3A
45 W
20 W
45 W
45 W
SALES TYPE MARKING PACKAGE PACKAGING
STP5NK40Z P5NK40Z TO-220 TUBE
STP5NK40ZFP P5NK40ZFP TO-220FP TUBE
STD5NK40ZT4 D5NK40Z DPAK TAPE & REEL
STD5NK40Z-1 D5NK40Z IPAK TUBE
TO-220 TO-220FP
1
2
3
1
3
DPAK
3
2
1
IPAK
INTERNAL SCHEMATIC DIAGRAM
STP5NK40Z - STP5NK40ZFP - STD5NK40Z - STD5NK40Z -1
2/13
ABSOLUTE MAXIMUM RATINGS
() Pulse width limited by safe operating area
(1) I
SD
≤3A, di/dt ≤200A/µs, VDD≤ V
(BR)DSS,Tj≤TJMAX.
(*) Limited only by maximum temperature allowed
THERMAL DATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’ s integrity. These integ rated Zener diodes thus avoid the
usage of external components.
Symbol Parameter Value Unit
STP5NK40Z STP5NK40ZFP
STD5NK40Z
STD5NK40Z-1
V
DS
Drain-source Voltage (VGS=0)
400 V
V
DGR
Drain-gate Voltage (RGS=20kΩ)
400 V
V
GS
Gate- source Voltage ± 30 V
I
D
Drain Current (continuous) at TC= 25°C
3 3 (*) 3 A
I
D
Drain Current (continuous) at TC= 100°C
1.9 1.9 (*) 1.9 A
I
DM
()
Drain Current (pulsed) 12 12 (*) 12 A
P
TOT
Total Dissipation at TC= 25°C
45 20 45 W
Derating Factor 0.36 0.16 0.36 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 2800 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
Insulation Withstand Voltage (DC) - 2500 - V
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55to150
-55to150
°C
°C
TO-220 TO-220FP DPAK
Rthj-case Thermal Resistance Junction-case Max 2.77 6.25 2.77 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 100 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
3A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, ID=IAR,VDD=50V)
130 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs=± 1mA (Open Drain) 30 V
3/13
STP5NK40Z - STP5NK 40Z FP - STD5NK40Z - STD5NK40Z-1
ELECTRICAL CHARACTERISTICS (T
CASE
=25°C UNLESS OTHERWISE SP ECIFIED)
ON/OFF
DYNAMIC
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when VDSincreases from 0 to 80%
V
DSS
.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
ID=1 mA, VGS= 0 400 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
=0)
V
DS
= Max Rating
VDS= Max Rating, TC= 125 °C
1
50
µA
µA
I
GSS
Gate-body Leakage
Current (V
DS
=0)
V
GS
= ± 20V ±10 µA
V
GS(th)
Gate Threshold Voltage
V
DS=VGS,ID
= 50µA
3 3.75 4.5 V
R
DS(on)
Static Drain-source On
Resistance
VGS=10V,ID= 1.5 A 1.47 1.8 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance VDS=15 V,ID= 1.5 A 2.2 S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
=25V,f=1MHz,VGS= 0 305
57
11.5
pF
pF
pF
C
oss eq.
(3) Equivalent Output
Capacitance
VGS=0V,VDS= 0V to 400V 44 pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
VDD=200V,ID= 1.5 A
RG= 4.7Ω VGS=10V
(Resistive Load see, Figure 3)
9.2
6
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=320V,ID=3A,
V
GS
=10V
11.7
2.8
5.8
17 nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
VDD= 200 V, ID= 1.5A
R
G
=4.7ΩVGS=10V
(Resistive Load see, Figure 3)
22.5
11
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 320V, ID=3A,
RG=4.7Ω, VGS= 10V
(Inductive Load see, Figure 5)
8.5
7.5
14.5
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
3
12
A
A
VSD(1)
Forward On Voltage
ISD= 3 A, VGS=0
1.6 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 3 A, di/dt = 100A/µs
VDD=40V,Tj= 150°C
(see test circuit, Figure 5)
145
464
6.4
ns
nC
A
STP5NK40Z - STP5NK40ZFP - STD5NK40Z - STD5NK40Z -1
4/13
Thermal Impedan ce For TO-220/DPAK/IPAK
Output Characteristics
Safe Operating Area For TO-220FPSafe Operating Area For TO-220/DPAK/IPAK
Thermal Impedance For TO-220F P
Transfer Characteristics
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