SGS Thomson Microelectronics STD3NM50-1, STD3NM50 Datasheet
STD3NM50
STD3NM50-1
N-CHANNEL 500V - 2.5Ω - 3A D PAK/IPAK
Zener-Protected MDmesh™Power MOSFET
TYPE V
STD3NM50
STD3NM50-1
■ TYPICAL R
■ HIGH dv/dt AND AVALANCHE CAPABILITIES
■ IMPROVED ESD CAPABIL ITY
■ LOW INPUT CAPACITANCE AND GATE
DS
DSS
500V
500V
(on) = 2.5 Ω
R
DS(on)
<3Ω
<3Ω
I
D
3A
3A
CHARGE
■ LOW GATE INPUT RESISTANCE
■ TIGHT PROCESS CONTROL AND HIGH
MANUFACTORING YIELDS
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal
layout. Theresulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar completition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increase
the power density of high voltage converters allowing system miniaturization and higher efficiencies.
3
DPAK
TO-252
1
IP AK
TO-251
1
INTERNAL SCHEMATIC DIAGRAM
3
2
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
IDM(●)
P
TOT
V
ESD(G-S)
dv/dt(1) Peak Diode Recovery voltage slope 15 V/ns
T
stg
T
j
(•)Pulse width limited by safe operating area
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
Gate- source Voltage ±30 V
Drain Current (continuous) at TC= 25°C
Drain Current (continuous) at TC= 100°C
Drain Current (pulsed) 12 A
T ot al Dissipation at TC= 25°C
Gate source ESD(HBM-C=100pF , R=15KΩ) 4KV
Derating Factor 0.37 W/°C
Storage Temperature –65 to 150 °C
Max. Operating Junction Temperature 150 °C
(1)ISD<3A, di/dt<400A/µs, VDD<V
500 V
500 V
3A
1.89 A
46 W
(BR)DSS,TJ<TJMAX
1/10April 2003
STD3NM50/STD3NM50-1
THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 2.73 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID=IAR,VDD=50V)
j
1A
130 mJ
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS O THERWISE SPECIFIED)
CASE
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID=1mA,VGS= 0 500 V
Breakdown Voltage
= Max Rating
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
=0)
=0)
V
DS
= Max Rating, TC= 125 °C
V
DS
V
= ± 20V ± 5 µA
GS
1µA
10 µA
ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
V
DS=VGS,ID
VGS=10V,ID= 1.5A
= 250µA
345V
2.5 3 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS>I
g
fs
ID=3A
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 40 pF
Reverse Transfer
V
Capacitance
R
G
Gate Input Resistance f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
D(on)xRDS(on)max,
=25V,f=1MHz,VGS=0
DS
0.7
140 pF
4pF
4 Ω
S
2/10
STD3NM50/STD3NM50-1
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Q
g
Q
gs
Q
gd
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge 2.5 nC
Gate-Drain Charge 2.4 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time 9 ns
Cross-over Time 15 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe o perating area.
Source-drain Current 3 A
(2)
Source-drain Current (pulsed) 12 A
(1)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 790 nC
Reverse Recovery Current 7.5 A
Reverse Recovery Time
Reverse Recovery Charge 1.1 µC
Reverse Recovery Current 7.7 A
=250V,ID= 1.5A
V
DD
RG= 4.7Ω VGS=10V
(see test circuit, Figure 3)
V
=400V,ID= 3A,
DD
V
=10V
GS
V
= 480V, ID=3A,
DD
RG=4.7Ω, VGS= 10V
(see test circuit, Figure 5)
ISD= 3A, VGS=0
I
= 3A, di/dt = 100A/µs,
SD
V
=100V,Tj=25°C
DD
(see test circuit, Figure 5)
I
= 3A, di/dt = 100A/µs,
SD
V
=100V,Tj=150°C
DD
(see test circuit, Figure 5)
7ns
10 ns
5.5 nC
8ns
1.5 V
210 ns
282 ns
GATE-SOURCE ZENER DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back -to-back Zener diodes have spec ifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective interven tio n to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
3/10
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