STD3NA50
N - CHANNEL ENHANCEMENT MODE
POWER MOS TRANSISTOR
■ TYPICAL R
DS(on)
= 2.4 Ω
■ AVALANCHE RUGGED TECHNOLOGY
■ 100% AVALANCHE TESTED
■ REPETITIVE AVALANCHE DATA AT 100
o
C
■ APPLICATION ORIENTED
CHARACTERIZATION
■ THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX ”-1”)
■ SURFACE-MOUNTINGDPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX ”T4”)
APPLICATIONS
■ HIGH SPEED SWITCHING
■ UNINTERRUPTIBLE POWER SUPPLY (UPS)
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ INDUSTRIALACTUATORS
■ DC-DC & DC-AC CONVERTERS FOR
TELECOM, INDUSTRIAL AND CONSUMER
ENVIRONMENT
■ PARTICULARLY SUITABLE FOR
ELECTRONIC FLUORESCENT LAMP
BALLASTS
INTERNAL SCHEMATIC DIAGRAM
TYPE V
DSS
R
DS(on)
I
D
STD 3NA50 500 V < 3 Ω 2.7 A
November 1996
ABSOLUTE MAXIMUM RATINGS
Symb o l Paramet er Val u e Unit
V
DS
Drain - s ource Voltage (VGS= 0) 500 V
V
DGR
Drain- gate Voltage (RGS=20kΩ) 500 V
V
GS
Gate-source Voltage ± 30 V
I
D
Drain Current (continuous) at Tc=25oC2.7A
I
D
Drain Current (continuous) at Tc=100oC1.7A
I
DM
(•) Drain Current (pulsed) 10.8 A
P
tot
Total Di ssipation a t Tc=25oC50W
Derat ing Factor 0.4 W/
o
C
T
stg
St or a ge Tem perature -65 t o 150
o
C
T
j
Max. Operating Jun ction T emperature 150
o
C
(•) Pulsewidth limited bysafe operating area
1
3
2
IPAK
TO-251
(Suffix ”-1”)
1
3
DPAK
TO-252
(Suffix ”T4”)
1/10