STD25NF10
N-CHANNEL 100V - 0.033Ω - 25A DPAK
LOW GATE CHARGE STripFET™ POWER MOSFET
TYPE V
DSS
R
DS(on)
I
D
STD25NF10 100 V < 0.038 Ω 25 A
■ TYPICAL R
■ EXCEPTIONA L dv/d t CAPABILITY
■ 100% AVALANCHE TESTED
■ APPLICATION ORIENTED
(on) = 0.033Ω
DS
CHARACTERIZATION
DESCRIPTION
This Power Mosfet series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated D C-DC
converters for T el ecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
3
1
DPAK
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
(*) Drain Current (continuos) at TC = 25°C
D
I
D
I
DM
P
TOT
dv/dt (1) Peak Diode Recovery voltage slope 13 V/ns
E
AS
T
stg
T
j
(●) Pulse width limited by safe operating area
(*) Curren t Lim i ted by Pack age
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
100 V
100 V
Gate- source Voltage ± 20 V
25 A
Drain Current (continuos) at TC = 100°C
(l)
Drain Current (pulsed) 100 A
Total Dissipation at TC = 25°C
21 A
100 W
Derating Factor 0.67 W/°C
(2)
Single Pulse Avalanche Energy 480 mJ
Storage Temperature
Operating Junction Temperature
(1) ISD ≤35A, di/dt ≤300A/µs, VDD ≤ V
(2) Starting Tj = 25°C, ID = 12.5A, VDD = 50V
–55 to 175 °C
(BR)DSS
, Tj ≤ T
JMAX.
1/9May 2002
STD25NF10
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 1.5 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W
T
l
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Maximum Lead Temperature For Soldering Purpose 300 °C
Drain-source
ID = 250 µA, VGS = 0 100 V
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±20V ±100 nA
GS
V
= VGS, ID = 250µA
DS
VGS = 10V, ID = 12.5 A
234V
0.033 0.038 Ω
1µA
10 µA
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS = 15 V, ID= 12.5 A 20 S
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 220 pF
Reverse Transfer
Capacitance
V
= 25V, f = 1 MHz, VGS = 0
DS
1550 pF
95 pF
2/9
STD25NF10
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 60 ns
Total Gate Charge VDD = 80V, ID =25A,VGS = 10V 55 nC
Gate-Source Charge 12 nC
Gate-Drain Charge 20 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off-Delay Time
Fall Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (2)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cyc l e 1.5 %.
2. Pulse width li mited by safe operating ar ea.
Source-drain Current 25 A
(1)
Source-drain Current (pulsed) 100 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
= 50V, ID = 12.5 A
DD
R
= 4.7Ω VGS = 10V
G
(see test circuit, Figure 3)
VDD = 50V, ID = 12.5 A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 3)
ISD = 25 A, VGS = 0
= 25 A, di/dt = 100A/µs,
I
SD
VDD = 50V, Tj = 150°C
(see test circuit, Figure 5)
17 ns
60
15
1.5 V
160 ns
ns
ns
nC
A
Thermal ImpedenceSafe Operating Area
3/9
STD25NF10
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
4/9
STD25NF10
Normalized Gate Thereshold Voltage vs Temp.
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
5/9
STD25NF10
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/9
TO-252 (DPAK) MECHANICAL DATA
STD25NF10
DIM.
A 2.20 2.40 0.087 0.094
A1 0.90 1.10 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.90 0.025 0.035
B2 5.20 5.40 0.204 0.213
C 0.45 0.60 0.018 0.024
C2 0.48 0.60 0.019 0.024
D 6.00 6.20 0.236 0.244
E 6.40 6.60 0.252 0.260
G 4.40 4.60 0.173 0.181
H 9.35 10.10 0.368 0.398
L2 0.8 0.031
L4 0.60 1.00 0.024 0.039
V2 0
MIN. TYP. MAX. MIN. TYP. MAX.
o
mm inch
o
8
o
0
o
0
P032P_B
7/9
STD25NF10
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT (suffix ”T4”)*
TUBE SHIPMENT (no suffix)*
All dimensions
are in millimeters
REEL MECHANICAL DATA
DIM.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0.795
G 16.4 18.4 0.645 0.724
N 50 1.968
T 22.4 0.881
mm inch
MIN. MAX. MIN. MAX.
TAPE MECHANICAL DATA
DIM.
A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476
D 1.5 1.6 0.059 0.063
D1 1.5 0.059
E 1.65 1.85 0.065 0.073
F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082
R 40 1.574
W 15.7 16.3 0.618 0.641
* on sales type
8/9
mm inch
MIN. MAX. MIN. MAX.
BASE QTY BULK QTY
2500 2500
STD25NF10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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