STD150NH02L
N-CHANNEL 24V - 0.003 Ω - 150A ClipPAK™/IPAK
STripFET™ III POWER MOSFET
PRELIMINARY DATA
TYPE
V
DSS
STD150NH02L 24 V < 0.0035
■ TYPICAL R
■ TYPICAL R
■ R
DS(ON)
■ CONDUCTION LOSSES REDUCED
■ SWITCHING LOSSES REDUCED
■ LOW THRESHOLD DEVICE
■ THROUGH-HOLE IPAK (TO-251) POWER
(on) = 0.003 Ω @ 10 V
DS
(on) = 0.005 Ω @ 5 V
DS
* Qg INDUSTRY’s BENCHMARK
R
DS(on)
I
D
150 A
Ω
PACKAGE IN TUBE (SUFFIX “- 1 ")
■ SURFACE-MOUNTING POWER PACKAGE
IN TAPE & REEL (SUFFIX “T4”)
DESCRIPTION
The STD150NH02L utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology. This
novel 0.6µ process utilizes also unique metallization
techniques that couple to a "bondless" assembly
technique result in outstanding performance with
standard DPAK outline. It is therefore ideal in high
performance DC-DC converter applications where
efficiency it to be achieved at very high out currents.
APPLICATIONS
■ SPECIFICALL Y D ESIGNED AND OP TIMISED
FOR HIGH EFFICIENCY DC/DC CONVERTES
3
2
1
ClipPak™
IPAK
(Suffix “T4”)
TO-251
(Suffix “-1”)
INTERNAL SCHEMATIC DIAGRAM
3
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
spike(1)
V
DS
V
DGR
V
GS
I
D
I
D
(2)
I
DM
P
tot
E
AS
T
stg
T
j
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Drain-source Voltage Rating 30 V
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
24 V
24 V
Gate- source Voltage ± 20 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
150 A
95 A
Drain Current (pulsed) 600 A
Total Dissipation at TC = 25°C
125 W
Derating Factor 0.83 W/°C
(3)
Single Pulse Avalanche Energy 900 mJ
Storage Temperature
Max. Operating Junction Temperature
-55 to 175 °C
1/9
STD150NH02L
THERMA L D ATA
Rthj-case
Rthj-amb
T
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
l
Max
Max
1.2
100
275
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 25 mA, VGS = 0
V
(BR)DSS
Drain-source
I
D
24 V
Breakdown Voltage
= 20 V
V
DS
V
= 20 V TC = 125°C
DS
V
= ± 20V
GS
1
10
±100 nA
ON
(4)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
= VGS I
DS
= 10 V ID = 75 A
V
GS
V
= 5 V ID = 75 A
GS
= 250 µA
D
1 1.8 V
0.003
0.005
0.0035
0.0065
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(4)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 10 V ID= 40 A
DS
= 15V f = 1 MHz VGS = 0
V
DS
52 S
4450
1126
141
µA
µA
Ω
Ω
pF
pF
pF
2/9
R
G
Gate Input Resistance f = 1 MHz Gate DC Bias = 0
1.6
Ω
Test Signal Level = 20 mV
Open Drain
STD150NH02L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 10 V ID = 75 A
t
d(on)
t
Turn-on Delay Time
r
Rise Time
V
DD
R
= 4.7 Ω VGS = 10 V
G
(Resistive Load, Figure 3)
Q
Q
gs
Q
gd
Q
oss
Q
gls
Total Gate Charge
g
Gate-Source Charge
Gate-Drain Charge
(5)
Output Charge
(6)
Third-quadrant Gate Charg e
= 16V ID= 150A VGS= 10 V
V
DD
V
= 16 V VGS= 0 V
DS
V
< 0 V VGS= 10 V
DS
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 10 V ID = 75 A
t
d(off)
t
Turn-off Delay Time
f
Fall Time
V
DD
R
= 4.7Ω, V
G
GS
= 10 V
(Resistive Load, Figure 3)
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(1)
Garanted wh en external Rg=4.7 Ω and tf < t
(2)
Pulse width limited by safe operating area
3
(
) Starting Tj = 25 oC, ID = 150A, VDD = 10V
.
.
Source-drain Current
Source-drain Current (pulsed)
(4)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
fmax
I
= 75 A VGS = 0
SD
= 150 A di/dt = 100A/µs
I
SD
V
= 15 V Tj = 150°C
DD
(see test circuit, Figure 5)
.
(4)
(5)
(6)
Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %.
Q
oss = Coss
Gate charge for synchronous operation
*∆ V
in , Coss = Cgd + Cds .
14
224
69
93 nC
13
9
27 nC
64 nC
69
40 54
150
600
1.3 V
47
58
2.5
See Appendix A
ns
ns
nC
nC
ns
ns
A
A
ns
nC
A
3/9
STD150NH02L
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
4/9
STD150NH02L
TO-251 (IPAK) MECHANI CAL DAT A
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039
A
C2
L2
E
B2
= =
= =
H
C
A3
A1
B6
L
B
B5
G
= =
D
B3
2
1 3
L1
0068771-E
5/9
STD150NH02L
TO-252 (DPAK) MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L2 0.8 0.031
L4 0.6 1 0.023 0.039
A
C2
L2
E
B2
==
H
DETAIL "A"
D
==
C
B
2
1 3
L4
A1
G
==
A2
DETAIL "A"
0068772-B
6/9
STD150NH02L
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (
The high side (
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
SW2
) device requires:
• Very low R
• Small Q
• Small C
• Small Q
• The C
gls
oss
rr
gd/Cgs
voltage to avoid the cross conduction phenomenon;
SW1)
• Small R
feedback on the gate
• Small Q
• Low R
g
DS(on)
to reduce conduction losses
DS(on)
to reduce the gate charge losses
to reduce losses due to output capacitance
to reduce losses on SW1 during its turn-on
ratio lower than Vth/Vgg ratio especially with low drain to source
device requires:
and Ls to allow higher gate current peak and to limit the voltage
g
to have a faster commutation and to reduce gate charge losses
to reduce the conduction losses.
7/9
STD150NH02L
High Side Switch (SW1) Low Side Switch (SW2)
conduction
P
P
P
P
P
switching
Recovery Not Applicable
diode
Conduction Not Applicable
)gate(Q
G
Qoss
Parameter Meaning
d Duty-cycle
Q
gsth
Q
gls
Pconduction
Pswitching
Pdiode
Pgate
Qoss
P
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
2
d*I *R
LDS(on)SW1
I
+
gd(SW1)gsth(SW1)in
f*V*Q
ggg(SW1)
f*Q*V
oss(SW1)in
2
L
*f*)Q(Q*V
I
g
Zero Voltage Switching
1
2
d−
f*Q*V
deadtimeLf(SW2)
f*V*Q
gggls(SW2)
f*Q*V
)1(*I *R
f*t*I*V
LDS(on)SW2
rr(SW2)in
oss(SW2)in
2
8/9
1
Dissipated by SW1 during turn - on
STD150NH02L
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.
The ST log o i s registered trademark of STMicroelectronics
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9/9
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