The STD100NH02L utilizes the latest advanced design
rules of ST’s proprieta ry STripFET™ technology. This is
suitable fot the most demanding DC-DC converter
application where high efficiency is to be achieved.
APPLICATIONS
■ SPECIFICALL Y D ESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC CONVERTES
3
2
1
IP AK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
INTERNAL SCHEMATIC DIAGRAM
3
1
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
spike(1)
V
V
V
I
D
I
D
I
DM
P
E
AS
T
DS
DGR
GS
(2)
(2)
(3)
tot
stg
T
j
Drain-source Voltage Rating30V
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
24V
24V
Gate- source Voltage± 20V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
60A
60A
Drain Current (pulsed)240A
Total Dissipation at TC = 25°C
100W
Derating Factor0.67W/°C
(4)
Single Pulse Avalanche Energy800mJ
Storage Temperature
Max. Operating Junction Temperature
-55 to 175°C
1/12September 2003
STD100NH02L
THERMA L D ATA
Rthj-case
Rthj-amb
T
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
l
Max
Max
1.5
100
275
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 25 mA, VGS = 0
V
(BR)DSS
Drain-source
I
D
24V
Breakdown Voltage
= 20 V
V
DS
V
= 20 V TC = 125°C
DS
V
= ± 20V
GS
1
10
±100nA
ON
(5)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
= VGS I
DS
= 10 V ID = 30 A
V
GS
V
= 5 V ID = 15 A
GS
= 250 µA
D
11.8V
0.0042
0.005
0.0048
0.009
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(5)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 10 V ID= 30 A
DS
= 15V f = 1 MHz VGS = 0
V
DS
50S
3940
1020
110
µA
µA
Ω
Ω
pF
pF
pF
2/12
R
G
Gate Input Resistancef = 1 MHz Gate DC Bias = 0
1.1
Ω
Test Signal Level = 20 mV
Open Drain
STD100NH02L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 10 V ID = 30 A
t
d(on)
t
Turn-on Delay Time
r
Rise Time
V
DD
R
= 4.7 Ω VGS = 10 V
G
(Resistive Load, Figure 3)
Q
Q
gs
Q
gd
Q
oss
Q
gls
Total Gate Charge
g
Gate-Source Charge
Gate-Drain Charge
(6)
Output Charge
(7)
Third-quadrant Gate Charg e
= 10 V ID= 60 A VGS= 10 V
V
DD
V
= 16 V VGS= 0 V
DS
V
< 0 V VGS= 10 V
DS
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 10 VID = 30 A
t
d(off)
t
Turn-off Delay Time
f
Fall Time
V
DD
R
= 4.7Ω, V
G
GS
= 10 V
(Resistive Load, Figure 3)
SOURCE DRAIN DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(1)
Garanted wh en external Rg=4.7 Ω and tf < t
2
(
) Value limited by wire bonding
(3)
Pulse width limited by safe operating area.
4
(
) Starting Tj = 25 oC, ID = 30A, VDD = 15V .
.
Source-drain Current
Source-drain Current (pulsed)
(5)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
= 30 A VGS = 0
SD
= 60 Adi/dt = 100A/µs
I
SD
V
= 15 VTj = 150°C
DD
(see test circuit, Figure 5)
.
fmax
(5)
Pulsed: P ul se duration = 300 µs, duty cycle 1.5 %.
(6)
Q
oss = Coss
(7)
Gate charge for synchronous operation
*∆ V
in , Coss = Cgd + Cds .
15
200
62
84nC
12
8
24nC
56.5nC
60
3547
60
240
1.3V
47
58
2.5
See Appendix A
ns
ns
nC
nC
ns
ns
A
A
ns
nC
A
Safe Operating AreaThermal Impedance
3/12
STD100NH02L
Output CharacteristicsTransfer Characteristics
TransconductanceStatic Drain-source On Resistance
Gate Charge vs Gate-source VoltageCapacitance Variations
4/12
STD100NH02L
Normalized Gate Threshold Voltage vs TemperatureNormalized on Resistance vs Temperature
Source-drain Diode Forward CharacteristicsNormalized Breakdown Voltage vs Temperature
..
5/12
STD100NH02L
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test CircuitFig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (
The high side (
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
SW2
) device requires:
• Very low R
• Small Q
• Small C
• Small Q
• The C
gls
oss
rr
gd/Cgs
voltage to avoid the cross conduction phenomenon;
SW1)
• Small R
feedback on the gate
• Small Q
• Low R
g
DS(on)
to reduce conduction losses
DS(on)
to reduce the gate charge losses
to reduce losses due to output capacitance
to reduce losses on SW1 during its turn-on
ratio lower than Vth/Vgg ratio especially with low drain to source
device requires:
and Ls to allow higher gate current peak and to limit the voltage
g
to have a faster commutation and to reduce gate charge losses
to reduce the conduction losses.
10/12
STD100NH02L
High Side Switch (SW1) Low Side Switch (SW2)
conduction
P
P
P
P
P
switching
Recovery Not Applicable
diode
Conduction Not Applicable
)gate(Q
G
Qoss
Parameter Meaning
d Duty-cycle
Q
gsth
Q
gls
Pconduction
Pswitching
Pdiode
Pgate
Qoss
P
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
2
d*I *R
LDS(on)SW1
I
+
gd(SW1)gsth(SW1)in
f*V*Q
ggg(SW1)
f*Q*V
oss(SW1)in
2
L
*f*)Q(Q*V
I
g
Zero Voltage Switching
1
2
d−
f*Q*V
deadtimeLf(SW2)
f*V*Q
gggls(SW2)
f*Q*V
)1(*I *R
f*t*I*V
LDS(on)SW2
rr(SW2)in
oss(SW2)in
2
1
Dissipated by SW1 during turn - on
11/12
STD100NH02L
Information furnished is believed to be accurate an d rel i able. However, STMicroelectro ni cs assumes no responsibility for the consequen ces
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent ri ghts of STM i croelectr onics. Sp ecifications mentioned in thi s publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approv al of STMicroel ectronics.
The ST log o i s registered trademark of STMicroelectronics
2002 STMi croelectronics - All Ri ghts Rese rved
All other names are the property of their respective ow ners.
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12/12
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