1/9March 2003
STB95NF03
N-CHANNEL 30V - 0.0065 Ω - 95A D²PAK
STripFET™ II POWER MOSFET
■ TYPICAL R
DS
(on) = 0.0065 Ω
■ STANDARD THRESHOLD DRIVE
■ 100% AVALANCHE TESTED
■ SURFACE-MOUNTING D
2
PAK (TO-263)
POWER PACKAG E IN TU BE (NO SU FFIX) OR
IN TAPE & REEL (SUFFIX “T4”)
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ DC-DC & DC-AC CONVERTERS
■ SOLENOID AND RELAY DRIVERS
TYPE
V
DSS
R
DS(on)
I
D
STB95NF03 30 V <0.007
Ω
80 A
1
3
D2PAK
TO-263
(Suffix “T4”)
ABSOLUTE MAXIMUM RATINGS
(
•)
Pulse width limited by safe operating area.
(*) Curren t Lim i ted by Pack age
(1) ISD ≤ 95A, di/dt ≤ 150A/µs, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX.
(2) Starting Tj = 25 oC, ID = 47.5A, VDD = 25V
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
30 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
30 V
V
GS
Gate- source Voltage ± 20 V
I
D
(
∗
)
Drain Current (continuous) at T
C
= 25°C
80 A
I
D
Drain Current (continuous) at TC = 100°C
80 A
I
DM
(
•)
Drain Current (pulsed) 320 A
P
tot
Total Dissipation at TC = 25°C
150 W
Derating Factor 1 W/°C
dv/dt
(1)
Peak Diode Recovery voltage slope 3.0 V/ns
E
AS
(2)
Single Pulse Avalanche Energy 720 mJ
T
stg
Storage Temperature
-55 to 175 °C
T
j
Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM