SGS Thomson Microelectronics ST75C520 Datasheet

HIGH SPEED FAX MODEM DATAPUMP

ITU-T V.17, V.29, V.27ter, V.21 WITH FAX SUPPORT

ITU-T V.23, V.21, BELL103

V.17,V.29 (T104), V.27ter SHORT TRAINS

V.33 HALF-DUPLEX

1800HzOR 1700HzCARRIER

SINGLECHIPCOMPLETEDATA PUMP

SINGLE5V POWER SUPPLY :

TYPICALACTIVE POWER CONSUMPTION: 375mW

LOW POWER MODE (typ. 5mW)

EXTENDED MODES OF OPERATIONS :

FULL IMPLEMENTATION OF THE V.17, V.33, V.29 AND V.27ter HANDSHAKES

AUTODIAL AND AUTOANSWER CAPABILITY

PROGRAMMABLETONE DETECTIONAND FSK V.21 FLAG PATTERN DETECTION DURING HIGH SPEED RECEPTION

PROGRAMMABLE CALL PROGRESS AND CALL WAITING TONE DETECTORS INCLUDINGDTMF

PROGRAMMABLE CLASS DETECTION CAPABILITY

WIDE DYNAMIC RANGE (>48dB)

A-LAWVOICEPCM MODE

ST75C520

PRELIMINARY DATA

DESCRIPTION

The SGS-THOMSONMicroelectronicsST75C520 chip is a highly integrated modem engine, which can operate with all currently used FAX group III standardsupto14400bps.FullV.21, V.23and Bell 103 full duplex modem standards are implemented.

PQFP64

(Plastic Quad Flat Pack)

ORDER CODE : ST75C520 PQFP

VERSATILEINTERFACES :

PARALLEL 64 x 8-BIT DUAL PORT RAM

SYNCHRONOUS/HDLC PARALLEL DATA HANDLING

HDLC FRAMING SUPPORT

V.24 INTERFACE

FULL OPERATING STATUS REAL TIME MONITORING

FULL DIAGNOSTIC CAPABILITY

DUAL 8-BIT DAC FOR CONSTELLATION DISPLAY

June 1995

This isadvance informationon a new productnow in developmentor undergoing evaluation. Detailsare subjectto change without notice.

1/45

ST75C520

CONTENTS Page

I PIN DESCRIPTION .................................................... 3

I.1 PIN CONNECTIONS. . . . . . . . . . . ......................................... 3

I.2 HOSTINTERFACE..................................................... 3

I.3 ANALOGINTERFACE . . . . . . . . .......................................... 4

I.4 V.24INTERFACE. . . ................................................... 4

I.5 MISCELLANOUS . . . ................................................... 4

I.6 BOUNDARYSCANINTERFACE . . . . . . . . . . . . . ............................. 4

I.7 POWER SUPPLY. . . . . . .. . ............................................. 5

II BLOCK DIAGRAMS.................................................... 5

III ELECTRICALSPECIFICATIONS ......................................... 6

III.1 MAXIMUMRATINGS . . . . . . . . . .......................................... 6

III.2 DC CHARACTERISTICS . . . . . . . . . ....................................... 6

III.3 AC CHARACTERISTICS . . . . . . . . . ....................................... 8

IV FUNCTIONAL DESCRIPTION............................................ 10

IV.1 SYSTEMARCHITECTURE . ............................................. 10

IV.2 OPERATION. . . . ...................................................... 10

IV.3 MODEMINTERFACE. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . .................... 11

V. USER INTERFACE..................................................... 11

V.1 DUALPORT RAM DESCRIPTION. . ....................................... 11

V.2 COMMANDSET. . . .. . . . . . . . . . . . ....................................... 14

V.3 COMMANDSET SHORT FORM . . . . . . . . . . . . . ............................. 16

V.4 STATUS- REPORTS. . . . . . ............................................. 17

V.5 DATA EXCHANGES. . . . . . . .. . .......................................... 17

VI COMMANDSETDESCRIPTION .......................................... 18

VII STATUSDESCRIPTION ................................................ 27

VII.1 COMMANDACKNOWLEDGEAND REPORT. . . ............................. 27

VII.2 MODEMSTATUS. . . ................................................... 28

VIII TONEDETECTORS.................................................... 34

VIII.1 OVERVIEW. .......................................................... 34

VIII.2 DESCRIPTION . ....................................................... 34

VIII.3 EXAMPLE. . . . . . . . . .. . .. . ............................................. 38

IX BUFFEROPERATIONS................................................. 38

IX.1 INTRODUCTION. . . . . . . . . . .. . . . . . . . .. . .. . . ............................. 38

IX.2 RECEIVEOPERATIONSOVERVIEW. . . . . . . . . .. . .......................... 39

IX.3 TRANSMIT OPERATIONSOVERVIEW. .................................... 39

IX.4 BUFFERSTATUS AND FORMAT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . ....... 40

IX.5 RECEIVEBUFFER. . . . . . . . . . . . ......................................... 40

IX.6 DATA BUFFERMANAGEMENT.. . . . . . .................................... 40

X DEFAULT CALL PROGRESS TONEDETECTORS........................... 42

XI DEFAULT ANSWER TONE DETECTORS .................................. 42

XII ELECTRICALSCHEMATICS............................................. 42

XIII PCB DESIGN GUIDELINES.............................................. 43

2/45

I - PIN DESCRIPTION I.1 - Pin Connections

ST75C520

SA0 SA1 SA2 SA3 SA4 SA5 SA6

GND

SD0 SD1 SD2 SD3 SD4 SD5 SD6

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

TXD

RXD

CLKCDCTS

38 39 40 41 42 43 44 45 46 47 4833 34 35 36 37

RTS

RING

GND

EYEX

EYEY

TEST2

EBS

TXA2

TEST1

TXA1

12345678910111213141516

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AGNDT V

RXA2 RXA1 AGNDR V

REFP

REFN

EXTAL XTAL CLKOUT HALT RESET SCOUT

BOS EOS

SD7

SDS (SRD)

SR/W (SWR)

SCS

SINTR

SDTACK

GND

INT/MOT

SCIN

MCI

SCCLK

RDYS

MC2

MC1

MC0

I.2 - Host Interface

The exchangeswith the control processor proceed through a 64 BytesDUALport RAM shared between the ST75C520 and the Host. The signalsassociatedwiththis interfaceare:

Pin Name Type Description

SD0..SD7 I/O System Data Bus. 8-bit data bus used forasynchronous exchanges between the ST75C520

SA0..SA6 I System Address Bus. 7-bit address bus for dual port RAM. SDS (SRD) I System Data Strobe. Active low. Synchronizes allthe exchanges. In Motorolamode initiates

SR/W (SWR) I System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel

SCS I System Chip Select. Active low. SDTACK OD System Bus Data Acknowledge. Active low. Open drain. SINTR OD System Interrupt Request.Active low. This signal is asserted by the ST75C520 and

RESET I Reset. Active low. RING I Ring Detect Signal. Active low. INT/MOT I Select Intel/Motorola Interface.

and the Host through the dualport RAM. High impedance when exchanges are not active.

the exchange, activelow. InIntelmode initiates a read exchange, activelow.

mode initiates awrite exchange, active low.

negated by thehost. Open drain.

75C52001.EPS

3/45

ST75C520

I.3 - AnalogInterface

Name

TXA1 O Transmit Analog Output 1 TXA2 O Transmit Analog Output2.OutputsTXA1andTXA2 provideanalogsignalswithmaximum peaktopeak

RXA1 I Receive AnalogInput 1 RXA2 I Receive AnalogInput 2. The analog differential input peak to peak signal must beless than 2 x V

V V V

I.4 - V.24 Interface

Pin Name Type Description

RTS I Request to Send. Active low. CLK O Data Bit Clock. Fallingedge coïncides with DATA change. CTS O Clear to Send. Active low. RxD O Receive Data TxD I Transmit Data sampled withrising edge of CLK CD O Carrier Detect. Active low.

Type Description

amplitude 2xV V

REF=VREFP-VREFN

, and must befollowedby an external continous-time twopole smoothingfilter (where

REF

must be preceded by an external continous-time single pole anti-aliasing filter. This filter must be as close as possibleto the RXA1 and RXA2 Pins (where V

CM REFN REFP

I/O Analog CommonVoltage (nominal +2.5V). This input must be decoupled with respect to AGND.

I Analog Negative Reference (nominal VCM- 1.25V). This input must be decoupled with respect to VCM. I Analog Positive Reference (nominalVCM+1.25V). This input must be decoupled with respect to VCM.

REF=VREFP-VREFN

REF

.It

I.5 - Miscellaneous

Pin Name Type Description

XTAL O Internal Oscillator Output. Left open if not used. EXTAL I InternalOscillator Input, or External Clock EYEX O Constellation X analog coordinate EYEY O Constellation Y analog coordinate TEST1 To be left open TEST2 To be left open

Note : The nominal external clock frequency of the ST75C520 is 29.4912MHz with a precision better than ± 5.10

-5

I.6 - BoundaryScanInterface

Aset of 13 signals arededicated for Testingthe ST75C520 Component. Thesesignals can be used in a developmentphase,associatedwith the SGS-THOMSONST18932 BoundaryScanDevelopment Tools, to Debug the applicationHardware and Software.If not used all input signals must be grounded and all output signals left open.

Pin Name Type Description

SCIN I Scan Data Input SCCLK I Scan Clock SCOUT O Scan Data Output BOS I Begin of Scan Control EOS I End of Scan MC0..MC2 I Mode Control HALT I Stop ST75C520 Execution MCI O Multicycle Instruction RDYS O Ready to Scan Flag EBS I Enable Boundary Scan. Active low (mustbe set low in normal mode). CLKOUT O InternalST75C520 Clock (XTAL frequency divided by 2)

4/45

ST75C520

I.7 - PowerSupply

Symbol Parameter

GND Digital Ground (Pin8, 24, 40). To be connected to AGNDT and AGNDR (see below). AV

AGNDT Analog Transmit Ground (Pin 64). To be connected to GND (see below). AGNDR Analog Receive Ground (Pin59). To be connected to GND (see below).

AGNDTand AGNDRmust be connectedtogetherascloseas possibleto the chip. GNDand AGNDRboardplansshould be separated,then connectedtogether as closeas possible to the chip, at a single point. Similarly V singlepoint.

II - BLOCK DIAGRAMS II.1 - Functional Block Diagram

Digital +5V (Pin 9, 25, 41). To be connected to AVDD(see below).

Analog +5V(Pin 62). To be connected to VDD(see below).

and AVDDmust ne connected as close as possible to the chip, at a

RXD

TXD

CLK

15 16 14

ST75C520

HDLC

MUX

V.17, V.29, V.27

FAX TRANSMITTER

ANALOG

TXA2

TXA1

SD [0..7]

(26 to 33)

SINTR

DUAL RAM

INTERFACE

HDLC

HANDSHAKE AND

STATUS REPORT

RTS

RING

DETECTOR

V.24

INTERFACE

13 1112 10

CTS

RING

V.17, V.29, V.27 FAX RECEIVER

TONE

DETECTOR

V.21 FLAG

DETECTOR

DPLL

ANALOG

RXA1 RXA2

75C52002.EPS

5/45

ST75C520

II.2 - HardwareBlockDiagram

XTAL

EXTAL

BOUNDARYSCAN

(42 to51 - 53-54)

EBS

RESET

SA [0..6]

(17 to 23)

SD [0..7]

(26 to 33)

SDS (SDR)

SR/W (SWR)

SCS

SDTACK

SINTR

34 35 36 37 38 39INT/MOT

11 12 13 14 10

DSPCORE

DUAL PORT

RAM

64 x8

V.24INTERFACE

CTS

RTS

ST18932

CLK

PROGRAM ROM 8Kx 32

RAM

2K x 16

S S

CROM

8K x16

16 15 7 6 5 4

TXD

RXD

RING

E Y E

EYEX

EYEY

P A G E

TEST1

TEST2

FIFO

8x16

FIFO

8x16

IIR FIR

DPLL AND CONTROL

FIR

8-24

IIR FIR

DGND

9-25

59 62 64

AGNDR

ST75C520

AGNDT

TXA2

TXA1

REFP

REFN

RXA1

RXA2

75C52003.EPS

III - ELECTRICALSPECIFICATIONS

Unless otherwisenoted,electrical characteristicsare specifiedovertheoperatingrange.Typicalvalue are given for V

= +5V andt

amb

=25°C.

III.1 - MaximumRatings (referencedto GND)

Symbol Parameter Value Unit

I,VIN

I,IIN

OUT

oper

stg

tot

Stresses above those hereby listed maycause damage to thedevice. The ratingsarestress related onlyand functional operation ofthe device at conditions beyond those indicated inthe operational sections of the specificationsis not implied. Exposure to maximumrating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the device.

DC Supply Voltage -0.3 to 7.0 V Digital or Analog Input Voltage -0.3 to(VDD+ 0.3) V Digital or Analog Input Current ± Digital Output Current ± Analog Output Current ±

1 20 10

mA mA

mA Operating Temperature 0, + 70 °C Storage Temperature (plastic) - 40, + 125 °C Maximum Power Dissipation 1000 mW

III.2 - DC Characteristics

= 5.0V ± 5%, GND=0V,T

=0 to 70°C(unlessotherwisespecified).

amb

III.2.1 - PowerSupply and Common Mode Voltage

Symbol Parameter Min. Typ. Max. Unit

DD-lp

SupplyVoltage 4.75 5 5.25 V SupplyCurrent (internal oscillator) 75 100 mA SupplyCurrent in Low Power Mode 1 mA Common Mode Voltage VDD/2 -5% VDD/2 VDD/2 + 5% V

6/45

ST75C520

III.2.2 - DigitalInterface

Alldigital pins except XTALPins.

Symbol Parameter Min. Typ. Max. Unit

Crystaloscillatorinterface(XTAL, EXTAL).

Symbol Parameter Min. Typ. Max. Unit

III.2.3 - AnalogInterface

Symbol Parameter Min. Typ. Max. Unit

REF

CMOin

DIFin

CMOout

DIFout

VOFFOut Differential Output DC Offset (TXA1 - TXA2) -100 100 mV Rin Input Resistance RXAx 100 Rout OutputResistance TXAx 20 Ω RL Load Resistance TXAx 10 CL Load Capacitance TXAx 50 pF

Low Level InputVoltage -0.3 0.8 V High Level InputVoltage 2.2 V Input Current VI=VDDor VI= GND -10 0 +10

High Level OutputVoltage (I Low Level Output Voltage (I

= 2mA) 2.4 V

load

= 2mA) 0.4 V

load

Three State Input Leakage Current (GND < VO<VDD) -50 0 50 µ Input Capacitance 5 pF

Low Level InputVoltage 1.5 V High Level InputVoltage 3.5 V Low Level InputCurrent GND < VI<V

High Level InputCurrent VIHmin< VI<V

Differential Reference VoltageInput = V Input Common Mode Offset,v = (RXA1+RXA2)/2 - V

ILmax

REFP-VREFN

Differential Input Voltage RXA1 - RXA2 2 x V Output Common Mode Voltage Offset = (TXA1+TXA2)/2 - V

Differential Output Voltage TXA1 - TXA2 2 x V

-15 µ 15 µ

2.40 2.50 2.60 V

-300 300 mV

REF

-200 200 mV

REF

kΩ

µA

A A

7/45

ST75C520

III.3 - AC ElectricalCharacteristics III.3.1 - Dual PortRAM Host Timing

NSCS

SA[0..6]

SR/NW

NSDS

Motorola modeIntel mode

SD[0..7]

NSDTACK

WRITE-CYCLE TIMING

Valid Address

174

3 5 10 5

Valid Data

26 26

READ-CYCLE TIMING

Valid Address

194

Valid Data

OUT

NSINTR

SR/NW (= NWRITE)

NSDS (= NREAD)

Number Description Min. Typ. Max. Unit

1 Address and Control Set-up Time 5 ns 2 SDTACK Acknowledge 20 ns 3 Data Set-up Time 10 ns 4 Address and Control Hold Time 0 ns 5 Data HoldTime 5 ns 6 SDTACK Hold Time 0 ns 7 Write Enable Low State 45 ns 8 Access Inhibition High State (see Note) 70 ns

9 Read Enable Low State 45 ns 10 Read Data Access 35 ns 11 SINTR Clear Delay 50 ns 12 Data Valid to Tristate 15 ns

Note : A minimum delay of70nsis required only fromthe rizing edge ofNWRITE tothefallingedge ofthe nextselected NREAD orNWRITE.

75C52004.EPS

8/45

III.3.2 - SerialV.24 Interface Timing

CLK

ST75C520

TXD

Valid Data In

RXD

Valid Data Out

Number Description Min. Typ. Max. Unit

1 TXD to CLK Set-up Time 30 ns

2 TXD to CLK Hold Time 10 ns

3 RXD Validto CLK Delay Time 100 ns

4 RXD Validto CLK HoldTime 0 ns

75C52005.EPS

9/45

ST75C520

IV - FUNCTIONALDESCRIPTION IV.1 - SystemArchitecture

The chip allows the design of a complete FAX data-pumpwithout any externalcomponent.Aversatiledual port RAM allows an easy interfacewith mostmicro-controllers.

IV.2 - Operation IV.2.1- Modes

Themodemimplementationisfullycompatiblewith FAX modulation recommendations. The modulation can be either TrellisCoded Modulation(TCM) as in V.17 14400, 12000, 9600, 7200bps rates, Quadrature Amplitude Modulation (QAM) as in V.29 9600, 7200, 4800 and V.27ter 4800 and 2400bps. Other modes of operation include tone and DTMF detection or generation, or speech mode.

IV.2.2- TransmitterDescription

The signalpulses are shaped in a dedicatedfilter further combined with a compromise transmit equalizersuitedfortransmissionoverstronglydistortedlines. 3 different compromise equalizersare availableand can be selectedby software.

IV.2.3- ReceiverDescription

The receiver section handlescomplex signals and usesa fractionally spaced complex equalizer. It is able to copewithdistantmodemtiming drifts up to

-4

asspecifiedinthe ITU-T recommendations.It

10 alsocompensateforfrequencydriftup to 10Hzand for phase jitter at multiple and simultaneous frequencies.

IV.2.4- ToneGeneratorDescription

Fourtonescanbesimultaneouslygeneratedbythe ST75C520. The tones are determined by their frequenciesandbytheoutputamplitudelevel.Aset of specific commandsare also available for DTMF generation(using two of the four generatorsavailable).

IV.2.5- ToneDetectorDescription

Sixteen tones can be simultaneouslydetected by the ST75C520.Eachofthe tonesto bedetectedis defined by the coefficientsof a 4th order programmableIIR. Detectionthresholds are also programmablefrom-45dBmupto-10dBm.DTMFdetection isalsoavailableand isperformedbya specificfilter section (that requires no programming).

IV.2.6- DTMF Detector Description

A DTMF Detector is included in the ST75C520, it allowsdetectionofvalidDTMFDigits.AvalidDTMF Digit is defined as a dual Tone with a total power higher than -35dBm,a durationhigher than 40ms and a differentialamplitudewithin 8dB(negativeor positive).

IV.2.7- VoiceMode

The ST75C520 voice mode allows the implementation of enhanced telephone functions like answering machines. The incoming samples (9600Hz), received from the line are PCM A-law coded and writen into the dual port RAM. The outpoing samples are decompressed using the same A-law and output to the telephoneline.

The voice mode is entered using a CONF command, it canbe either transmit voice from thedual RAM Tx bufferto the telephoneline,receivevoice from the telephone line to the dual RAM buffer,or both of these functions simultaneously. The format of thesignal isA-law codedwithout complementation of the even bits. The buffer mechanism, between thehostmicro-controler andtheST75C520, is identicaltothemechanismusedforparalleldata exchanges except that it starts immediately after CONF command, the size of the transmit and received buffer,are and must be 8 bytes, there is no needfor aXMITcommand, andifan overrunor underrunconditionoccursno error willbe reported to thehost processor.

IV.2.8- Analog Loop Back Test Mode

In any transmission standard and serial data format, the ST75C520can be configured for analog loop backtest.

IV.2.9- Low Power Mode

Sleepstatecan beattainedby a SLEEPcommand. Activating the reset signal will wake up the datapump. Whenin sleep mode, the dual port RAM is unavailableand theclocksare disabled.

Whenenteringthe lowpowermode,theST75C520 stops its oscillator, all the peripherals of the DSP core are stopped in order to reduce the power consumption.Thedual RAM is made inacessible.

The ST75C520 can be awakened by a hardware reset.

There is a maximum time of 20ms to restart the oscillator after waking up and an additional 5ms after the interrupt to be able to accept any command coming from the host.

10/45

ST75C520

IV.2.10- Reset

After a hardware reset, or an INIT command, the ST75C520 clears all its internal memories, clears thewhole dual RAMand startsto initialize thedelta sigma analog converters.As soon as theseinitializations are completed, the ST75C520 clears the dual RAM address 0 (COMSYS), generates an interrupt IT6 (command acknoledge) and is programmed to send and receive tones, the bit clock and the sample clock areprogrammedto 9600Hz. The total duration of the reset sequence is about 5ms. After that time the ST75C520 is ready to executecommands sentby the host micro-controller.Thedurationoftheresetsignalshouldbegreater than700ns.

IV.3 - Modem Interface IV.3.1- AnalogInterface

Themodemdesigner must provideaproperhybrid interface to the ST75C520. An example of hybrid design is given in paragraphs XII and XIII. The inputs and outputs of the MAFE are differential, achieving thus a better noise immunity. The D/A converter output amplifier includes a single pole low-passfilter, its cut-off frequencyis :

- 3dB # 19200Hz.

Continuous-timefiltering of the analog differential output is necessaryusingan off-chip amplifierand a fewexternalpassivecomponents.

IV.3.2- Host Interface

The host interface is seen by the micro as a 64x8 RAM, with additional registers accessiblethrough an 8-bit address space.Aselection Pin(INT/MOT) allowstoconfigurethehostbusfor eitherINTELor MOTOROLAtypecontrolsignals.

V.1.1- Mapping V.1.1.1- CommandArea

The command area is located from $00 to $04. Address $00 holds the commandbyte COMSYS, and the next four locations hold the parameters COMPAR[0..3]. The command parameters must be entered before the command word is issued. Once the command has been entered, the command byte is reset and an acknowledge report is issued. A new command should not be issued beforetheacknowledgecounterCOMACKisincremented.

V.1.1.2- ReportArea

The report area is located from address $05 to address $07.Location$05holdsthe acknowledge counter COMACK. Each time a command is acknowledged, the report bytes COMREP[0..1] (if any) are written by the ST75C520 into locations $06 and $07, and the content of COMACK is incremented.This counterallowsthe ST75C520to accurately monitor the command processing.

V.1.1.3- StatusArea

Thestatusareaislocatedfromaddress$08to$0A. The error status word SYSERR is located at address$08. Thiserror statusword isupdated each time anerrorconditionoccurs.Anoptionalinterruption IT0 may additionally be triggered in the case of an error condition. Locations$09 and $0A hold the generalstatusbytes STATUS[0..1]. The meaning of the bitsdepends on the mode of operation, and is described in Chapter VII. The third byte at address $0B holds the Quality Monitor byte STAQUA.

V - USER INTERFACE V.1 - Dual PortRam Description

ThedualportRAMisthestandardinterfacebetween the controller and the ST75C520, for either commandsordata.Thismemoryis addressedthrougha 7-bitaddressbus.Thelocationsfrom$00 to$3Fare RAMlocations,while locationsfrom $40 to$50 are controlregistersdedicatedtotheinterrupt handling.

Severalfunctionalareasaredefinedinthedualport RAM, namely :

- thecommand area,

- thereport area,

- thestatusarea,

- thedata bufferarea.

V.1.1.4- Optional StatusArea

The user can program (through the DOSR command) the three locations STAOPT[0..2] of the OptionalStatusArea ($0C to $0E) for the real time monitoring of threearbitrarymemorylocations.

V.1.1.5- DataBuffer Area

The data area is made of four 8-bytebuffers. Two are dedicated to transmission and the two others to reception.Eachof thefour buffers is attached to a status byte. the meaning of the status byte depends on the selected format of transmission. Within each buffer, D0 represents the first bit in time.

11/45

ST75C520

V.1.2- Interruptions

The ST75C520 can generate 5 interrupts for the controller.The interrupthandlingis made withaset of registers located from $40 to $50.

The interruptions generated by the ST75C520 come from several different sources. Once the ST75C520 raises an interrupt, a signal is sent to the controller. The controller has then to process the interrupt and clear it.The interrupt source can be examined in the Interrupt Source Register ITSRCR located at $50. According to this status byte,theinterruptsourcecanbedetermined.Then, writing azero at oneof thememorylocation$40to $46 (Reset Interrupt Registers ITREST[0..6]) will reset the corresponding interrupt (and thus acknowledgeit). These sources of interruptions can be masked globally or individually using the Interrupt Mask Register ITMASKlocatedat $4F.

The interrupt sources are :

- IT0 : Error/Warning This signifies that an error has occurredand the error code is available in the error status byte SYSERR.This byte can be selectivelycleared by the CSE command.

- IT2 : Tx Buffer Each time the ST75C520 frees a buffer, this interruptis generated.

- IT3 : Rx Buffer Each time the ST75C520 has filled a buffer, this interrupt is generated.

- IT4 : StatusByte This signifies that the status byte has changed and must be checked by the controller.

- IT6 : Command Acknowledge ThissignifiesthattheST75C520hasreadthelast command entered by the host, incrementedthe command counter COMACK, and is ready for a new command.

ITSRCR X D6 X D4 D3 D2 X D0

D0 =1 IT0 Pending D2 =1 IT2 Pending Dn =1 ITn Pending

ITMASK D7 D6 X D4 D3 D2 X D0

D7 andD0 = 1 IT0 EnableD D7 andD2 = 1 IT2 EnableD

...................... .....................

D7 andD6 = 1 IT6 EnableD

12/45

ST75C520

V.1.3- Host InterfaceSummary

Address (hex) Description Size (Byte) Mnemonic

COMMAND AREA

$00 Command 1 COMSYS $01-$04 Command Parameters 4 COMPAR[0..3]

REPORT AREA

$05 Acknowledge Counter 1 COMACK $06-$07 Report 2 COMREP[0..1]

STATUS AREA

$08 Error Status 1 SYSERR $09-$0A General Status 2 STATUS[0..1] $0B Quality Monitor 1 STAQUA $0C-$0E Optional Report 3 STAOPT[0..2]

DATA AREA

$1C Data Rx Buffer0 Status 1 DTRBS0 $1D-$24 Data Rx Buffer0 8 DTRBF0[0..7] $25 Data Rx Buffer 1 Status 1 DTRBS1 $26-$2D Data Rx Buffer1 8 DTRBF1[0..7] $2E Data Tx Buffer 0 Status 1 DTTBS0 $2F-$36 Data Tx Buffer0 8 DTTBF0[0..7] $37 Data Tx Buffer 1 Status 1 DTTBS1 $38-$3F Data Tx Buffer1 8 DTTBF1[0..7]

INTERRUPT AREA

$40-$46 Reset InterruptReg. 7 ITREST[0..6] $4F Interrupt Mask Reg. 1 ITMASK $50 Interrupt Source Reg. 1 ITSRCR

13/45

ST75C520

V.2 - Command Set

The Command Set has the following attractive features :

- userfriendlywitheasyto remembermnemonics,

- possibilityof straightforwardexpansionwithnew commands to suit specific customer requirements,

- easyupgradeofexisting software usingprevious modem based SGS-THOMSONproducts.

The command set has been designed to provide the necessaryfunctionalcontrolon theST75C520. Eachcommandisclassified accordingtoitssyntax and the presence/absenceof parameters. In the case of a parametriccommand,parameters must first be written into the dual port RAM before the commandisissued. Acknowledgeand errorreport isissued for eachcommand entered.

V.2.1- Command SetSummary V.2.1.1- OperationalControl Commands INIT Initialize. Initialize the modem engine.

Setallparameterstotheirdefault values and wait for commands of the control processor. Non parametriccommand.

IDT Identify. Returntheproductidentification

code.Non parametric command.

SLEEP Turntolow power mode, the ST75C520

entersthelowpowermode and stopsits crystal oscillator to reduce power consumption.In this mode allthe clocks are stopped and the du al RAM is unreachable.

HSHK Handshake. B egins the handshake

sequence. The modem engine generates all the sequences defined in the ITU-T recommendations. A status reportindicatesto thecontrol processor the state of the handshake. This commandonly applies to modes where a handshake sequence is defined. A CONFcommandmusthavebeenissued priortotheuseofHSHK. Nonparametric command.

STOP FAX Sto p. Stop FAX Half-duplex

transmitter. Nonparametriccommand.

SYNC FAX Synchronize. Start/Stop of FAX

Half-duplex receiver. Par ametric command.

CSE Clear StatusError. Selectivelyclearsthe

Error status byte SYSERR. Parametric command.

SETGN Set Gain. This command sets theglobal

gain factor,whichisused for thetransmit samples.Parametriccommand.

V.2.1.2- Data CommunicationCommands XMIT Transmit Data. Start/stop the

transmission of data in parallel mode. After a XMIT command, the ST75C520 sends the data containedin its dualport RAM.

SERIAL Select Serial or Parallel Mode. This

command selects the data source, i.e. either parallel or serial. The parallel mode uses a part of the dual port RAM as a doublebuffer.Theserialmodeuses the serial synchronous I/O. Parametric command.

FORM SelectstheTransmissionFormat(onlyin

parallel mode). This command configures the data interface for both receiverandtransmitteraccordingtothe selected data format. Parametric command (HDLC or synchronous). In serial mode, format is always synchronous.

V.2.1.3- MemoryHandling Commands MW Memory Write.This commandisusedto

write an arbitrary 16-bit value into the writa ble me mo r y locatio n curren t ly specified by a parameter. Parametric command.

MR MemoryRead.Thiscommandallowsthe

controller to read any of the ERAM or CROM (ST75C520 memory spaces) loca tion without int errupting t he processor. Parametriccommand.

CR Complex Read. This command allows

the controller to read at the same time the real and imaginarypartofacomplex value stored in a double ERAM or CROM location. This feature is very interesting for eye pattern software control and for equalization monitoring. This command insures that the real and imaginary parts are sampled in the memory at the same time (integrity). Parametric command.

14/45

+ 31 hidden pages