SGS Thomson Microelectronics ST75951 Datasheet

V .34/56K MODEM AN ALOG FRONT-END (AFE)

16 BIT S OVERSAM PLI NG SIG MA DELTA A/D AND D/A CO NV ER TER S

85dB DYNAMIC RANGE

PROGRAMMABLE SAMPLING FREQUENCY

AUXILIARY ANALOG INPUT

MODEM SIDE OF SILI CON DATA ACCESS ARRANGEMENT (DAA) INTEGRATED WITH AFE

KRYPTON ISOLATION INC. PATENTED TECHNOLOGY ELIMINATE TRANSFORMER OR LINEAR OPTO-COUPLERS

RING DETECT, LINE IN USE, CLID AND OVER LOOP CURRENT DETECT

4 GPIO ASSOCIATED WITH 1 GENERAL PURPOSE INTERRUP T O UTPUT

ANALOG AND DIGITAL LOOP-BACK MODE

SYNCHRONOUS SERIAL INTERFACE FOR PROCESSORS DAT A EXCHANGE

ON CHIP REFERENCE VOLT AGE

SINGLE POWER SUPPLY RANGE :

2.7V TO 5.25V

LOW POW ER C ONSUM PTIO N : 40mW @ 3. 3V

TQFP48 PACKAGE

0.5µM CMOS PRO CESS

DESCRIPTION

ST75951 is an analog front-end designed to implement modems application up to 56Kbps.

ST75951 interfaces between DSP or HSP signals and capacitive isolation barrier.

A c omplete D.A.A. is made with ST952 which interfaces between capacitive isolation barrier and the telephone line.

ST75951

V.34/56K ANALOG FRONT END

TQFP48 (7 x 7 x 1.4mm)

(Full Plastic Quad Flat Pack)

ORDER CODE : ST75951

Figure 1

Tip

Digital

ST75951 ST952

Digital

Ring

It integrates a high resolution A/D and D/A converter and incorporates Krypton Isolation Inc. patented silicon D.A. A. technol ogy.

February 1999

75951-30.EPS

1/21

ST75951

PIN CONNECTIONS

AGND2

AUXIN

RESET

TSTD1

DIN

DOUT

CMS

TSTA2

CMP

TSTA1

2526272829303132333435

37 38

39 40 41 42 43 44 45 46 47 48

24 23 22 21 20 19 18 17 16 15 14 13

NC AGND1 V

REFN

REFP

GPIO0 GPIO1 GPIO2 GPIO3 GPI RING M/S NC

1234567893610 11 12

SCLK

MCM

DGND

XTALOUT

HC1

HC0

PWRDWN

XTALIN (MCLK)

75951-01.EPS

2/21

PIN LIST

Pin Number Name Type Description

2 SCLK O Bit Shift Clock Output , SCLK = Coeff ⋅ FS 3 FS I/O Frame Synchronization Input (Slave)/Output (Master) 4 MCM I Master Clock Mode 5DV

6 DGND I Digital Ground (0V) (see Note1) 7 XTALOUT O Crystal Output 8 XTALIN I Crystal Input

9 HC1 I Hardware Control Input 10 HC0 I Hardware Control Input 11 14 M/

PWRDWN I Power Down Input

S I Master/slave Control Input 15 RING O Ring Detect Output 16 GPI O General Purpose Interrupt Output 17 GPIO3 I/O General Purpose Control Input/Output 18 GPIO2 I/O General Purpose Control Input/Output 19 GPIO1 I/O General Purpose Control Input/ Output 20 GPIO0 I/O General Purpose Control Input/Output 21 V 22 V

REFP REFN

23 AGND1 I Analog Ground (0V) (see Note1) 26 D6 O ST952 Control Output 27 D5 O ST952 Control Output 28 TSTA1 O Reserved for test 29 V

CMP

30 D4 I Receive Input 31 D3 I Receive Input 32 V

CMS

33 TSTA2 O Reserved for test 34 D2 O Transmit Output 35 D1 O Transmit Output 38 AGND2 I Analog Ground (0V) (see Note1) 39 V 40 AV

41 AUXIN I Receive Auxiliary Analog Input Amplifier 42 HM I Hardware Control Input for Clid/Off-hook 43

RESET I Reset Function to initialize the device 44 TS I Timeslot Control Input 45 TSTD1 I Reserved for Test (must be grounded in normal mode) 46 DIN I Serial Data Input 47 DOUT O Serial Data Output

Note 1 :

Digital and Analog ground must be connected externally together.

I Positive Digital Power Supply

O Positive Reference Voltage O Negative Reference Voltage

I Common Mode Voltage Input P

I Common Mode Voltage Input S

O Common Mode Voltage Output

I Positive Analog Power Supply

ST75951

75951-01.TBL

3/21

ST75951

PIN DESCRIPTION 1 - Power Supply

1.1 - Power Sup ply

These pins are the positive analog and digital power supply input (2.7 to 5.25V).

In any case, the AV or equal to the DV

(5 Pins)

, DVDD)

(AV

voltage must alw ays be higher

voltage (AVDD ≥ DVDD).

A software powerdow n with wake-up on ring detect is also provided with bit 4 in control register 3.

3.3 - Hardware Control

(HC0, HC1)

These pins are used for hardware/software control programmation of the device.

1.2 - Analog Ground

( AGND1, AG ND2)

These pins are the ground return of the DAC and ADC analog section.

1.3 - Digital gr ound

(DGND) This pin is the ground return of the digital circuitry. Note : In order to obtain publ ished performances,

the analog A V

and digital DVDD should be decou-

pled with respect to analog ground and digital ground, respectively. Decoupling capacitors should be as close as possible to the supplies pins. All ground must be tied together. In the following section the ground is referred as : GND.

2 - Serial Synchronous Interface

2.1 Data

(DIN, DOU T)

(4 Pins)

Digital data word input/output of the SSI (16 bits data).

2.2 - Frame Synchronization

(FS)

The frame synchronization is used to indicate that the device is ready to send and receive data.

The data transfer begins on the falling edge of frame-sync signal. The frame-SYNC can be generated internally or externally.

2.3 Serial Bit Clock

(SCLK)

Clocks the digital data into DIN and out of DOUT during the frame synchroniza tion interval. The serial bit clock is generated internally and equal to MCLK/R (R programmed value in r egister 3) . The serial bit clock is a multiple of FS.

RESET)

(

(10 Pins)

3 - Control Pins

3.1 - Reset

This pin initializes the internal counters and control registers to their default value. A minimum low pulse of 100ns is required to r eset the chip.

PWRDWN)

3.2 - Power-Down

(

This input powers down the entire c hip. In power down mode the existing internally programmed state is maintained. When power down is dr iven high, full operation resumes after 1ms.

3.4 - Hardware Control

(HM)

This pin is used for hardware/software control of CLID/OFFHOOK function.

(M/

3.5 - Master/Slave

When M/

S = " 1 " the device is in master mode and

FS is generated internally othe rwise the device is in slave mode and Fs must be provided externally and equal to SCLK*R / OVER.

3.6 - Timeslot Control

(TS)

When TS = " 0 " t he data are assig ned to the first timeslot (1st 16 bits after falling edge of FS) otherwise t he data are on the second tim eslot (bits 17 to 32).

3.7 - Control

(D5, D6)

These pins transmit the control signals tr ough isolation capacitors to ST952 which converts and outputs the appropriate control signals.

3.8 - Master Clock Mode

(MCM)

When MCM = " 1 " , we have FS = Master Clock/[M ⋅ Q ⋅ OVER] otherwise we have FS = Master Clock/OVER and the M, Q dividers are bypassed.

4 - General Purpose Input/Output Circuitry

4.1 - GPIO

(4 Pins)

ST75951 offers 4 general purpose Input/Output pins. The setting of the GPIO configuration is done through the control register 1 and the signal level of the GPIO are reflected in the feedback register 2.

At power on the GPIO are programmed as inputs. In order to take into account the evolution of ST952,

thanks to the control register we will be able to send a clock signal equal to F0/N (N programmed in register 2) on GPIO0 and F0 on GPIO3.

When in DAA control hardware mode HM = 1, the CLID and OFF-HOOK control is done by Pin GPIO1 (CLID) and GPIO2 (OFF- HOOK), otherwise when HM = 0 then the CLID/OFF-HOOK control is done by programming the adequate bit in the control register 3 (Bit 2 , Bit 3, see Table 7).

4/21

ST75951

PIN DESCRIPTION

4.2 - General Purpose Interrupt System

(continued)

(GPI)

The GPI will reflect any change of the GPIO’S inputs or RING output when non-masked, so the processor does not need to read the output control word continuously . G PI level change tells the processor, one of the non-masked input pins level has changed and he can read the control word. So GPIO could extend the number of interrupt pins of the processor.

5 - Ring

This pin is used for the Ring detect but also reports the Line status, current limit.

6 - Digital Test Pin

(TSTD1)

This pin is reserved for digital test purpose.

7 - Crystal

(XTALIN , XT ALOUT )

These pins must be tied to an external crystal or a master clock generator (MCLK).

8 - Analog Interface

(12 Pins)

8.1 - DAC and ADC Reference Voltage Output

REFP

, V

REFN

)

These pins provide the positive and negative reference Voltage used by the 16-bit converters. The reference voltage, V between the V

and V

REFP

with re s p e ct to V

and V

REFP

should be externally decoupled

REFN

8.2 - Common Mode V oltage Output

is the voltage difference

REF ,

outputs.

REFN

)

This output pin is the common mode voltage (AVDD - AGND)/2 . This output must be decoupled with re s p e ct to GND.

8.3 - Common Mode V oltage Input

CMP

, V

CMS

These input pins are the common mode voltage for internal circuitry. They have to be c onnected externally to V

8.4 - Analog Transmit Output

(D1 ,D2)

These pins are the output of the fully differential converted analog signal, modulated at F0 (1MHz < F0 < 1.7MHz).

The digital data IN signal is converted in analog signals (with (Sin X)/X compensation). Two ranges of signal amplitude have to be considered ; modem application with dynamic up to 2.5V

with maxi-

mum performances SNDR = 83dB, voice application with dynamic up to 3.2V

differential

(SNDR = 75dB). The transmit output stage can be programmed to

+2dB gain, 0db gain, 6dB or infinite attenuation.

8.5 - Analog Receive Inputs

(D3, D4)

These pins are the differential analog inputs. These analog inputs are presented to the F0 demodulator and the sigma-delta modulator. The analog input peak-to-peak differential signal range must be less than 2.5 V

. The gain of the receive stage is

programmable to 0dB or 6dB.

8.6. - Analog Test Pin

(TSTA1, TSTA2)

These pins are reserved for analog test purpose.

8.7 Analog Auxiliary Receive Inputs

(AUXIN)

This pin is the auxiliary analog input. This analog input is presented to the analog modulator. The analog input peak-to-peak signal range must be less than 1.25 V

. The gain of the rec eive stage

is 0dB.

)

5/21

ST75951

BLOCK DIAGRAM

CMSVCMP

AUXIN

D3 D4

RING

HIGH

PASS

FILTER

Bit DR

DETECTOR

MUX

DVDDDGND AVDDAGND1 AGND2 VCMV

40 435 6

2932

LOW

PASS

FILTER

GAIN GAIN ATTE ATTE

2dB 0dB 6dB

INFINITE

23 22 21

GAIN

DAC 1 BIT First Order Differential

Switched Capacitor

Filter

MUX

REFNVREFP

38 39 91011

REFERENCE

VOLTAGE

ANALOG

MODULATOR

2nd ORDER

MODULATOR

RESET PWRDWN

LOW-PASS

(0.425 x Sampling

Frequency)

LOW-PASS

(0.425 x Sampling

Frequency)

HC0 HC1

TSTD1

2 47 46

SERIAL PORTS

AND CONTROL REGISTER

SCLK

DOUT

DIN

CLOCK GENERATOR

STLC75951

33 42414 78

TSTA1 TSTA2 M/S MCM XTALIN

2627

D5 D6

(MCLK)

FUNCTIONAL DESCRIPTION

ST75951 is a modem AFE front-end integrating the modem side of Krypton K951 and fully com patible to work with ST952.

1 - Transmit Section

The functions included in the transmit section are :

- D/A converter,

- F0 modulator,

- Programmable stage +2dB gain, 0dB gain, 6dB attenuation or infinite attenuation,

- Transmit Filter including noise shaper and Sinx/x correction.

The digital bas e Band data (DIN) ar e converte d and modulate d at F 0 and send di ffere nt ial ly ( D1, D2 ) t o ST952 through capacitive connection.

2 - Receive Section

The functions included in the rec eive section are :

- Main and Aux inputs,

- Programmable gain 0/6dB,

DAA CONTROL + GPIO

20 19 18 17

XTALOUT HM

GPIO0 GPIO1 GPIO2 GPIO3

- A/D converter,

- F0 demodulator,

- Receive filter. The analog differential Main input signal (D3, D4)

coming from ST952 is demodulated at F0, goes to the multiplexer and gain receive block then is digitally converted and output on DOUT which is the base band data.

Thanks to the multiplexer, we can also process base band analog signal on AUXIN.

3 - Clock Generator

ST75951 generates all clocks from either a Master clock input on XTA LIN (MCLK) or a crystal oscillator connected between XTALIN and XTALOUT.

The bypass of the divider M and Q is selected by setting the MCM input pin to ’0’.

To be able to provide externally the sampling frequency (Slave mode), M/

S input pin must be set

to ’0’ (see Figure 2).

GPI

75951-02.EPS

6/21

ST75951

FUNCTIONAL DESCRIPTION

(continued)

Figure 2

XTALIN (MCLK) XTALOUT

% M % Q

GPIO1 or CLGPIO2 or OH

4 - Power Down Mode

Tw o PowerD own modes are available in ST 75951 thanks to bit 4 in control register 3.

4.1 - PowerDown Mode 0

If bit 4 is set to ’0’ then when

PWRDWN is set to ’0’

the entire chip is in powerdown mode 0.

Figure 3

MCM

SCLK

4 1478

% R

Sync

% OVER

% 2

Internal Sampling

Frequency

M/S

F0 or F0/2

tomer feature associated with a defined GPIO (programmed as input and non-masked).

4.2.1 - Ring Bit and GPIO Bit Masked

In this configuration the processor relies on the Ring output pin to process the wake-up of the system and does not need the S S I to be poweredon. The SSI will be put back in operative mode when

PWRDWN is set to ’1’ (see Figure 4).

75951-03.EPS

REG3 BIT4 = 0

Normal

PWRDWN

4.2 - PowerDown Mode 1

Power Down 0

(100µW)

When bit 4 i s set to ’1’ th en wh en

Normal

PWRDWN is set to ’0’ the ch ip is in powerd own ex cept th e Ring de tect circuitry (wake-up on Ring = powerdown mode 1).

The general purpose interrupt is also working in order to wake-up the system for dedicated cus-

4.2.2 - Ring Bit or GPIO Bit Non-Masked

In this configuration the processor relies on the SS I to process the wake-up of the system and needs the SSI to be powered-on.

75951-04.EPS

On an incoming Ring signal or an interrupt coming thanks to the GPIO, ST75951 will generate an interrupt on GPI output pin and power-up the SSI, the processor will be able to read the control register 2 and find out the origine of the interrupt.

After a reading of the register 2, if the processor does not set high

PWRDWN ST75951 puts b ack

the SSI off in order to save energy (see Figure 5).

7/21

+ 14 hidden pages