SGS Thomson Microelectronics ST72T633L1M1, ST72T633K1B1, ST72T632L2M1, ST72T631L4M1, ST72T631K4B1 Datasheet
...
Rev. 1.5
January 2000 1/107
This ispreliminary information on anew product. Details aresubject to change without notice.
ST7263
LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY,
up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI
&I2C
PRELIMINARY DATA
■ Up to 16Kbytes program memory
■ Data RAM: up to 512 bytes with 64 bytes stack
■ Run, Wait and Halt CPU modes
■ RAM retention mode
■ USB (Universal Serial Bus) Interface with DMA
for low speed applications compliant with USB
1.5 Mbs specification (version 1.1) and USB
HID specifications (version 1.0)
■ Integrated 3.3V voltage regulator and
transceivers
■ Suspend and Resume operations
■ 3 endpoints with programmable in/out
configuration
■ 19 programmable I/O lines with:
– 8 high current I/Os (10mA at 1.3V)
– 2 very high current pure Open Drain I/Os
(25mA at 1.5V)
– 8 lines individually programmable as interrupt
inputs
■ Low Voltage Reset (optional)
■ Programmable Watchdog for systemreliability
■ 16-bit Timer with:
– 2 Input Captures
– 2 Output Compares
– PWM Generation capabilities
– External Clock input
■ Asynchronous SerialCommunications Interface
(8K and 16K program memory versions only)
■ I
2
C Multi Master Interface up to 400 KHz
(16K program memory version only)
■ 8-bit A/D Converter (ADC) with 8 channels
■ Fully static operation
■ 63 basic instructions
■ 17 main addressing modes
■ 8x8 unsigned multiply instruction
■ True bit manipulation
■ Versatile Development Tools (under Windows)
including assembler, linker, C-compiler,
archiver, source level debugger, software
library, hardware emulator, programming
boards and gang programmers
Table 1. Device Summary
Note 1: EPROM version for development only
SO34 (Shrink)
PSDIP32
CSDIP32W
Features
ST72631
ST72632 ST72633
ROM - OTP (bytes) 16K 8K 4K
RAM (stack) - bytes 512 (64) 256 (64)
Peripherals
Watchdog, 16-bit timer, SCI, I
2
C, ADC,
USB
Watchdog, 16-bit timer,
SCI, ADC, USB
Watchdog, 16-bit timer,
ADC, USB
Operating Supply 4.0V to 5.5V
CPU frequency 8 Mhz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating temperature 0°Cto+70°C
Packages SO34/SDIP32
EPROM device ST72E631
1
(CSDIP32W)
1
Table of Contents
107
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ST7263 .............................................1
1 GENERAL DESCRIPTION . . . . . . ................................................ 5
1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 5
1.2 PIN DESCRIPTION . . ..................................................... 6
1.3 EXTERNAL CONNECTIONS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 9
1.4 REGISTER & MEMORYMAP . . . . . . ........................................10
1.5 EPROM/OTPPROGRAM MEMORY . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1 EPROM ERASURE . . . . . . . . . . . . . . . . ................................. 13
2 CENTRAL PROCESSING UNIT . . ............................................... 14
2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................14
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 14
2.3 CPU REGISTERS . . . .................................................... 14
3 CLOCKS AND RESET . . . . . . . . . ...............................................17
3.1 CLOCK SYSTEM . . . . . .. . . . . . ............................................17
3.1.1 General Description . . . . . ............................................ 17
3.1.2 External Clock . . . . . . . . . . . . . ........................................17
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 18
3.2.1 Low Voltage Reset . . ............................................... 18
3.2.2 Watchdog Reset . . . . . . . . . . . . . . . . . . ................................. 18
3.2.3 External Reset . . . . . . ...............................................18
4 INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . ...........20
4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 20
4.1.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ........ 23
4.2.1 Introduction . . . .................................................... 23
4.2.2 HALT mode . . . ....................................................23
4.2.3 WAIT mode ....................................................... 24
5 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 25
5.1 I/O PORTS . . . . . . . . . . . . . . . . . . ...........................................25
5.1.1 Introduction . . . .................................................... 25
5.1.2 Functional description . . . . . . . . . . . . . . . . . . . . ........................... 25
5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . ........................... 26
5.1.4 Port A . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 27
5.1.5 Port B . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 29
5.1.6 Port C . . . . . . ...................................................... 30
5.1.7 Register Description . . . . . . ...........................................31
5.2 MISCELLANEOUS REGISTER . . . . . . . . . . . .................................. 32
5.3 WATCHDOG TIMER (WDG) . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1 Introduction . . . .................................................... 33
5.3.2 Main Features . . . . . . ...............................................33
5.3.3 Functional Description . . . . ...........................................34
5.3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 34
5.3.5 Register Description . . . . . . ...........................................34
Table of Contents
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5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................ 36
5.4.1 Introduction . . . .................................................... 36
5.4.2 Main Features . . . . . . ...............................................36
5.4.3 Functional Description . . . . ...........................................36
5.4.4 Low Power Modes . . ............................................... 48
5.4.5 Interrupts . . . . . ....................................................48
5.4.6 Summary of Timer modes . . . . . . . . . . . . . . .............................. 48
5.4.7 Register Description . . . . . . ...........................................49
5.5 SERIAL COMMUNICATIONSINTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5.1 Introduction . . . .................................................... 54
5.5.2 Main Features . . . . . . ...............................................54
5.5.3 General Description . . . . . ............................................ 54
5.5.4 Functional Description . . . . ...........................................56
5.5.5 Low Power Modes . . . ............................................... 60
5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 60
5.5.7 Register Description . . . . . . ...........................................61
5.6 USB INTERFACE (USB) . . . . . . . . . . ........................................65
5.6.1 Introduction . . . .................................................... 65
5.6.2 Main Features . . . . . . ...............................................65
5.6.3 Functional Description . . . . ...........................................65
5.6.4 Register Description . . . . . . ...........................................66
5.6.5 Programming Considerations ......................................... 71
5.7 I2C BUS INTERFACE (I2C) . . . . . ...........................................73
5.7.1 Introduction . . . .................................................... 73
5.7.2 Main Features . . . . . . ...............................................73
5.7.3 General Description . . . . . ............................................ 73
5.7.4 Functional Description . . . . ...........................................75
5.7.5 Low Power Modes . . . ............................................... 78
5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 78
5.7.7 Register Description . . . . . . ...........................................79
5.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . ........................... 84
5.8.1 Introduction . . . .................................................... 84
5.8.2 Main Features . . . . . . ...............................................84
5.8.3 Functional Description . . . . ...........................................85
5.8.4 Low Power Modes . . . ............................................... 85
5.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 85
5.8.6 Register Description . . . . . . ...........................................86
6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . ........................................87
6.1 ST7 ADDRESSING MODES . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.1 Inherent . . . . .. . . . . . ...............................................88
6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1.3 Direct . ........................................................... 88
6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . ........................... 88
6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1.6 Indirect Indexed (Short,Long) . ........................................89
6.1.7 Relative mode (Direct,Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . .................................90
ST7263
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7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . ............................... 93
7.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................ 93
7.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3 POWER CONSUMPTION . . . . . . ........................................... 95
7.4 I/O PORT CHARACTERISTICS . ............................................ 96
7.5 LOW VOLTAGE RESET CHARACTERISTICS . . . . . . ........................... 97
7.6 CONTROL TIMING CHARACTERISTICS . . . . ................................. 97
7.7 COMMUNICATIONINTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.7.1 USB - Universal Bus Interface . . . . . . . . ................................. 98
7.7.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . .............. 100
7.8 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . .......................... 101
8 GENERAL INFORMATION . . . . . . . . . . ..........................................103
8.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . .......................... 103
8.2 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . .............. 105
8.2.1 Transfer of Customer Code . . . . . . . . . . ................................ 105
ST7263
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST7263 Microcontrollers form a sub family of
the ST7 dedicated to USB applications. The devices arebased on anindustry-standard 8-bit core
and feature an enhanced instructionset. They operate at a 24MHz or 12 MHz oscillator frequency.
Under softwarecontrol,theST7263MCUsmay be
placed in either Wait or Halt modes, thus reducing
power consumption. The enhanced instruction set
and addressing modes afford real programming
potential. In addition to standard 8-bit data management, the ST7263 MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect
addressing modes. The devices include an ST7
Core, upto 16K program memory, up to 512 bytes
RAM, 19 I/O lines and the following on-chip peripherals:
– USB low speed interface with 3 endpoints with
programmable in/out configuration using the
DMA architecture with embedded 3.3V voltage
regulator and transceivers (no external components are needed).
– 8-bit Analog-to-Digital converter (ADC) with 8
multiplexed analog inputs
– industry standard asynchronous SCIserial inter-
face (not on all products- see device summary
below)
– digital Watchdog
– 16-bit Timer featuring an External clock input, 2
Input Captures, 2 Output Compares with Pulse
Generator capabilities
– fast I2C Multi Master interface (not on all prod-
ucts - see device summary)
– Low voltage reset ensuring proper power-on or
power-off of the device
All ST7263 MCUs are available in ROM and OTP
versions.
The ST72E631 is the EPROM version of the
ST7263 in CSDIP32 windowed packages.
A specific mode is available to allow programming
of the EPROM user memory array. This is set bya
specific voltage source applied to the VPP/TEST
pin.
Figure 1. General BlockDiagram
8-BIT CORE
ALU
ADDRESS AND DATABUS
OSCIN
OSCOUT
RESET
PORT B
16-BIT TIMER
PORT A
PORT C
PB[7:0]
(8 bits)
PC[2:0]
(3 bits)
OSCILLATOR
Internal
CLOCK
CONTROL
RAM
(256/512 Bytes)
PA[7:0]
(8 bits)
V
SS
V
DD
POWER
SUPPLY
SCI*
PROGRAM
(4K/8K/16K Bytes)
I
2
C*
MEMORY
ADC
(UART)
USB SIE
OSC/3
LVD
WATCHDOG
V
SSA
V
DDA
VPP/TEST
USB DMA
USBDP
USBDM
USBVCC
OSC/4 or OSC/2
(for USB)
* not on all products (refer to Table 1: Device Summary)
ST7263
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1.2 PIN DESCRIPTION
Figure 2. 34-Pin SO Package Pinout
Figure 3. 32-Pin SDIP Package Pinout
18
19
20
21
22
23
31
30
29
28
27
26
25
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
DD
OSCOUT
AIN4/IT5/PB4
(10mA)
AIN5/IT6/PB5
(10mA)
VPP/TEST
AIN6/IT7/PB6
(10mA)
AIN7/IT8/PB7
(10mA)
NC
RESET
PC0/RDI
PC1/TDO
PC2/USBOE
V
SS
OSCIN
USBDP
V
SSA
PB0
(10mA)
/AIN0
PA7/OCMP2/IT4
PA6/OCMP1/IT3
PA5/ICAP2/IT2
PA4/ICAP1/IT1
PA3/EXTCLK
PA2
(25mA)
/SCL
NC
NC
NC
PA1
(25mA)
/SDA
PA0/MCO
15
16
17
AIN1/PB1
(10mA)
AIN2/PB2
(10mA)
AIN3/PB3
(10mA)
34
33
32
V
DDA
USBVCC
USBDM
*V
PP
on EPROM/OTPversions only
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
29
30
31
32
V
DD
OSCOUT
AIN1/PB1/
(10mA)
AIN2/PB2
(10mA)
AIN3/PB3
(10mA)
AIN4/IT5/PB4
(10mA)
AIN5/IT6/PB5
(10mA)
VPP/TEST*
AIN6/IT7/PB6
(10mA)
PC0/RDI
PC1/TDO
PC2/USBOE
V
SS
OSCIN
AIN7/IT8/PB7
(10mA)
RESET
V
DDA
USBVCC
PB0
(10mA)
/AIN0
PA7/COMP2/IT4
PA6/COMP1/IT3
PA5/ICAP2/IT2
PA4/ICAP1/IT1
PA3/EXTCLK
PA2
(25mA)
/SCL
PA1
(25mA)
/SDA
PA0/MCO
V
SSA
USBDP
USBDM
NC
NC
*V
PP
on EPROM/OTP versions only
ST7263
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PIN DESCRIPTION (Cont’d)
RESET (see Note 1): Bidirectional. This active low
signal forces the initialization of the MCU. This
event is the top priority non maskable interrupt.
This pin is switched low when the Watchdog has
triggered orVDDis low. It can be used to reset external peripherals.
OSCIN/OSCOUT: Input/Output Oscillator pin.
These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
VPP/TEST: EPROM programming input. This pin
must beheld low during normal operating modes.
VDD/VSS(see Note 2): Main power supply and
Ground voltages.
V
DDA/VSSA
(see Note 2): Power Supply and
Ground for analog peripherals.
Alternate Functions: Several pins of the I/O ports
assume software programmable alternate functions as shown in the pin description.
Note 1: Adding two 100nF decoupling capacitors
on Reset pin (respectively connected to VDDand
V
SS
) will significantly improve product electromag-
netic susceptibility performances.
Note 2: To enhance reliability of operation, it is
recommended to connect V
DDA
and VDDtogether
on the application board.The same recommendations apply to V
SSA
and VSS.
Table 2. Device Pin Description
Pin n°
Pin Name
Type
Level Port / Control
Main
Function
(after reset)
Alternate Function
SDIP32
SO34
Input
Output
Input Output
float
wpu
int
ana
OD
PP
11V
DD
S Power supply voltage (4V - 5.5V)
2 2 OSCOUT O Oscillator output
3 3 OSCIN I Oscillator input
44V
SS
S Digital ground
5 5 PC2/USBOE I/O C
T
X X Port C2 USB Output Enable
6 6 PC1/TDO I/O C
T
X X Port C1 SCI transmit data output
*)
7 7 PC0/RDI I/O C
T
X X Port C0 SCI Receive Data Input
*)
8 8 RESET I/O X X Reset
-- 9 NC -- Not connected
9 10 PB7/AIN7/IT8 I/O C
T
10mA X XX XPort B7 ADC analog input 7
10 11 PB6/AIN6/IT7 I/O C
T
10mA X XX XPort B6 ADC analog input 6
11 12 V
PP
/TEST S Supply for EPROM and test input
12 13 PB5/AIN5/IT6 I/O C
T
10mA X XX XPort B5 ADC analog input 5
13 14 PB4/AIN4/IT5 I/O C
T
10mA X XX XPort B4 ADC analog input 4
14 15 PB3/AIN3 I/O C
T
10mA X XXPort B3 ADC analog input 3
15 16 PB2/AIN2 I/O C
T
10mA X XXPort B2 ADC analog input 2
16 17 PB1/AIN1 I/O C
T
10mA X XXPort B1 ADC analog input 1
17 18 PB0/AIN0 I/O C
T
10mA X XXPort B0 ADC Analog Input 0
18 19 PA7/OCMP2/IT4 I/O C
T
X XXPort A7 Timer Output Compare 2
19 20 PA6/OCMP1/IT3 I/O C
T
X XXPort A6 Timer Output Compare 1
ST7263
8/107
*: if the peripheral is present on the device (see Table 1 Device Summary)
Legend / Abbreviations of Figure 2 and Table 2:
Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDDwith input trigger
Output level: 10mA = 10mA high sink (on N-buffer only)
25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, PP = push-pull
Refer to “I/O PORTS” on page 25 for more details on the software configuration of the I/O ports.
The RESET configuration of each pinis shown in bold. This configurationis kept as longas the device is
under reset state.
20 21 PA5/ICAP2/IT2 I/O C
T
X XXPort A5 Timer Input Capture 2
21 22 PA4/ICAP1/IT1 I/O C
T
X XXPort A4 Timer Input Capture 1
22 23 PA3/EXTCLK I/O C
T
X X Port A3 Timer External Clock
23 24 PA2/SCL I/O C
T
25mA X X Port A2 I2C serial clock
*)
-- 25 NC -- Not connected
24 26 NC -- Not connected
25 27 NC -- Not connected
26 28 PA1/SDA I/O C
T
25mA X X Port A1 I2C serial data
*)
27 29 PA0/MCO I/O C
T
XXPort A0 Main Clock Output
28 30 V
SSA
S Analog ground
29 31 USBDP I/O USB bidirectional data (data +)
30 32 USBDM I/O USB bidirectional data (data -)
31 33 USBVCC O USB power supply
32 34 V
DDA
S Analog supply voltage
Pin n°
Pin Name
Type
Level Port / Control
Main
Function
(after reset)
Alternate Function
SDIP32
SO34
Input
Output
Input Output
float
wpu
int
ana
OD
PP
ST7263
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1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended external connections for the device.
The VPPpin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC performance/cost tradeoff.
The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
Figure 4. Recommended External Connections
V
PP
V
DD
V
SS
OSCIN
OSCOUT
RESET
V
DD
0.1µF
+
See
Clocks
Section
V
DD
0.1µF
0.1µF
EXTERNAL RESET CIRCUIT
Or configure unused I/O ports
Unused I/O
10nF
4.7K
10K
by software as input with pull-up
V
DD
Detector (LVD) isused
Optional if Low Voltage
ST7263
10/107
1.4 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 192
bytes of register location, up to 512 bytes of RAM
and up to 16K bytes of user program memory. The
RAM space includes up to 64 bytes for the stack
from 0100h to 013Fh.
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations noted “Re-
served” must never be accessed. Accessing a reserved area can have unpredictable effects on the
device
Figure 5. Memory Map
* Program memory and RAM sizes are product dependent (see Table 1 Device Summary)
Table 3. Interrupt Vector Map
* If the peripheral is present on the device (see Table 1 Device Summary)
Vector Address Description Masked by Remarks Exit from Halt Mode
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
USB Interrupt Vector
SCI Interrupt Vector*
I
2
C Interrupt Vector*
TIMER Interrupt Vector
IT1 to IT8 Interrupt Vector
USB End Suspend Mode Interrupt Vector
TRAP (software) Interrupt Vector
RESET Vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
none
none
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
External Interrupts
Internal Interrupt
CPU Interrupt
No
No
No
No
Yes
Yes
No
Yes
0000h
Interrupt & Reset Vectors
HW Registers
0040h
003Fh
(see Table 4
FFEFh
FFF0h
FFFFh
(see Table 3 on page 10)
C000h
BFFFh
F000h
Program Memory*
512 Bytes RAM*
8K Bytes
4K Bytes
E000h
Short Addressing
Stack (64 Bytes)
0100h
0040h
00FFh
013Fh
Reserved
0240h
023Fh
RAM (192 Bytes)
16K Bytes
256 Bytes RAM*
Short Addressing
Stack (64 Bytes)
0100h
0140h
023Fh
0040h
00FFh
013Fh
16-bit Addressing RAM
RAM (192 Bytes)
(256 Bytes)
ST7263
11/107
Table 4. Hardware Register Memory Map
Address Block Register Label Register name Reset Status Remarks
0000h
0001h
PADR
PADDR
Port A Data Register
Port A Data Direction Register
00h
00h
R/W
R/W
0002h
0003h
PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
00h
00h
R/W
R/W
0004h
0005h
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
1111 x000b
1111 x000b
R/W
R/W
0006h
0007h
Reserved (2 Bytes)
0008h ITIFRE Interrupt Register 00h R/W
0009h MISCR Miscellaneous Register F0h R/W
000Ah
000Bh
ADC
DR
CSR
ADC Data Register
ADC control Status register
00h
00h
Read only
R/W
000Ch WDG CR Watchdog Control Register 7Fh R/W
000Dh
0010h
Reserved (4 Bytes)
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
TIM
CR2
CR1
SR
IC1HR
IC1LR
OC1HR
OC1LR
CHR
CLR
ACHR
ACLR
IC2HR
IC2LR
OC2HR
OC2LR
Timer Control Register 2
Timer Control Register 1
Timer Status Register
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read only
Read only
Read only
R/W
R/W
Read only
R/W
Read only
R/W
Read only
Read only
R/W
R/W
0020h
0021h
0022h
0023h
0024h
SCI
1)
SR
DR
BRR
CR1
CR2
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
C0h
xxh
00xx xxxxb
xxh
00h
Read only
R/W
R/W
R/W
R/W
ST7263
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Note 1. If the peripheralis present on the device (see Table 1 Device Summary)
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
USB
PIDR
DMAR
IDR
ISTR
IMR
CTLR
DADDR
EP0RA
EP0RB
EP1RA
EP1RB
EP2RA
EP2RB
USB PID Register
USB DMA address Register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
xxh
xxh
xxh
00h
00h
xxxx 0110b
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0032h
0038h
Reserved (7 Bytes)
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
I
2C1)
DR
OAR
CCR
SR2
SR1
CR
I
2
C Data Register
Reserved
I2C (7 Bits) Slave Address Register
I
2
C Clock Control Register
I
2
C 2nd Status Register
I
2
C 1st Status Register
I
2
C Control Register
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
Read only
Read only
R/W
Address Block Register Label Register name Reset Status Remarks
ST7263
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1.5 EPROM/OTP PROGRAM MEMORY
The program memory ofthe ST72T63 may be programmed using the EPROM programming boards
available from STMicroelectronics (see Table 26).
1.5.1 EPROM ERASURE
ST72Exxx EPROM devices are erased by exposure to high intensity UV light admitted through the
transparent window. This exposuredischarges the
floating gate to its initial state through induced
photo current.
It is recommended that the ST72Exxx devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under theselighting conditions. Covering the window also reduces IDDin
power-saving modes due to photo-diode leakage
currents.
An Ultraviolet source of wave length 2537 Å yielding a total integrated dosage of 15 Watt-sec/cm2is
required to erase the ST72Exxx. The device will
be erased in 15 to 30 minutes if such a UV lamp
with a 12mW/cm2power rating is placed 1 inch
from the device window without any interposed filters.
ST7263
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
2.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bitregisters
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y registeris not affectedby the interrupt automatic procedures (notpushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) andPCH
(Program CounterHigh which is the MSB).
Figure 6. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C11HI NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH
PCL
15
87 0
RESET VALUE = STACKHIGHER ADDRESS
RESET VALUE =
1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE= XXh
X = Undefined Value
ST7263
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CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result ofthe instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H
Half carry
.
This bit is set by hardware whena carryoccursbetween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I
Interrupt mask
.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlledby the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
th
bit of the result.
0:Theresultof the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit isaccessed bythe JRMI andJRPL instructions.
Bit 1 = Z
Zero
.
This bit is set and cleared by hardware. Thisbit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow hasoccurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
70
111HINZC
ST7263
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CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 3Fh
The Stack Pointer is a 16-bit register which is always pointingto the next free location in the stack.
It isthen decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an
MCU Reset, orafter a Reset Stack Pointer instruction (RSP),the Stack Pointer contains its resetvalue (SP5 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wrapsin case of anunderflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by meansof the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from thestack.
A subroutine call occupies twolocations and an interrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
15 8
00000001
70
0 0 SP5 SP4 SP3 SP2 SP1
SP0
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
Subroutine
Interrupt
Event
PUSH Y POP Y IRET
RET
or RSP
@ 013Fh
@ 0100h
Stack Higher Address = 013Fh
Stack Lower Address =
0100h
ST7263
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3 CLOCKS AND RESET
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts eithera Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f
CPU
) is de-
rived from the external oscillator frequency (f
OSC
),
which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used).
By setting the CLKDIV bit in the Miscellaneous
Register, a 12 MHz external clock can be used giving an internal frequency of 4 MHz whilemaintaining a 6 MHz for USB (refer to Figure 10).
The internal clock signal (f
CPU
) is also routed to
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartzor ceramic resonator in the frequency range specified for f
osc
.
The circuit shown in Figure 9 is recommended
when using a crystal, and Table 5 Recommended
Values for 24 MHz Crystal Resonator lists the recommended capacitance.The crystal andassociated components should be mounted as close as
possible to the input pins in order to minimize output distortion and start-up stabilisation time.
Table 5. Recommended Values for 24 MHz
Crystal Resonator
Note: R
SMAX
is the equivalent serial resistor of the
crystal (see crystal specification).
3.1.2 External Clock
An externalclock may be applied to the OSCIN input with the OSCOUT pin not connected, as
shown on Figure 8. The t
OXOV
specifications does
not apply when using an external clock input. The
equivalent specification of the external clock
source should be used instead of t
OXOV
(see Sec-
tion 6.5CONTROL TIMING).
Figure 8. External ClockSource Connections
Figure 9. Crystal/Ceramic Resonator
Figure 10. Clock block diagram
R
SMAX
20 Ω 25 Ω 70 Ω
C
OSCIN
56pF 47pF 22pF
C
OSCOUT
56pF 47pF 22pF
R
P
1-10 MΩ 1-10 MΩ 1-10 MΩ
OSCIN OSCOUT
EXTERNAL
CLOCK
NC
OSCIN OSCOUT
C
OSCIN
C
OSCOUT
R
P
%3
CPU and
8 or 4 MHz
6 MHz (USB)
24 or
peripherals)
%2
1
0
CLKDIV
%2
12 MHz
Crystal
%2
ST7263
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3.2 RESET
The Resetprocedure is used toprovide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: alow voltage reset, a watchdog reset and an external reset at the
RESET pin.
A resetcauses the reset vectorto be fetched from
addresses FFFEh andFFFFhin order to be loaded
into the PC and with program execution starting
from this point.
An internalcircuitry provides a 4096 CPU clock cycle delayfrom the time that the oscillator becomes
active.
3.2.1 Low Voltage Reset
Low voltageresetcircuitry generates a reset when
VDDis:
■ below V
TRH
when VDDis rising,
■ below V
TRL
when VDDis falling.
Duringlowvoltagereset, theRESETpinisheldlow,
thus permitting the MCU to reset other devices.
The LowVoltage Detector can be disabled by setting the LVD bit of the Miscellaneous Register.
3.2.2 WatchdogReset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devices as when low voltage reset (Figure 11).
3.2.3 External Reset
The externalreset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 14, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger atthe RESET pinisprovided to improve noise immunity.
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)
Section RESET WAIT HALT
CPU clock running at 8 MHz X
Timer Prescaler reset to zero X
Timer Counter set to FFFCh X
All Timer enable bit set to 0 (disable) X
Data Direction Registers set to 0 (as Inputs) X
Set Stack Pointer to 013Fh X
Force Internal Address Bus to restart vector FFFEh,FFFFh X
Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable) X
Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable) X X
Reset HALT latch X
Reset WAIT latch X
Disable Oscillator (for 4096 cycles) X X
Set Timer Clock to 0 X X
Watchdog counter reset X
Watchdog register reset X
Port data registers reset X
Other on-chip peripherals: registers reset X
ST7263
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Figure 11. Low Voltage Reset functional Diagram
Figure 12. Low Voltage Reset Signal Output
Note: Typical hysteresis (V
TRH-VTRL
) of 250mV is
expected
Figure 13. Temporization timing diagram after an internal Reset
Figure 14. Reset Timing Diagram
Note: Refer to Electrical Characteristics for values of t
DDR
,t
OXOV
,V
TRH,VTRL
and V
TRM
LOW VOLTAGE
V
DD
FROM
WATCHDOG
RESET
RESET
INTERNAL
RESET
RESET
RESET
V
DD
V
TRH
V
TRL
V
DD
Addresses
$FFFE
temporization (4096 CPUclock cycles)
V
TRH
V
DD
OSCIN
f
CPU
FFFF
FFFE
PC
RESET
WATCHDOG RESET
t
DDR
t
OXOV
4096 CPU
CLOCK
CYCLES
DELAY
ST7263
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4 INTERRUPTS AND POWER SAVING MODES
4.1 INTERRUPTS
The ST7 core may be interruptedby one oftwo different methods: maskable hardware interrupts as
listed in Table 7 Interrupt Mapping and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 15.
The maskableinterrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsection).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit ofthe CC register is set to prevent addi-
tional interrupts.
– ThePC is then loaded withtheinterruptvector of
the interruptto service and the first instruction of
the interrupt service routine is fetched (refer to
Table 7 Interrupt Mapping forvectoraddresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from thestack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt can not be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case several interrupts are simultaneously
pending, a hardware priority defines which one will
be serviced first (see Table 7 Interrupt Mapping).
Non maskable software interrupts
This interrupt is entered when the TRAP instruction is executed regardless of the stateof theI bit.
It will be serviced according to the flowchart on
Figure 15.
Interrupts and Low power mode
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific mentioned interrupts allow the processor to leave the
Halt low power mode (refer to the “Exit from HALT“
column in Table 7 Interrupt Mapping).
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)
can generate an interrupt when a rising edge occurs on this pin. Conversely, pins ITl/PAnandITm/
PBn (l=3,4; m= 7,8; n=6,7) can generate an interrupt whena falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with
the ITiE bit (i=1 to 8) in the ITRFRE register and if
the I bit of the CCR is reset.
Peripheral interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both.
– The I bit of the CC register is cleared.
– Thecorresponding enable bit is setin thecontrol
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– writing “0” to the corresponding bit in the status
register or
– an access to the status registerwhile the flag is
set followed by a read or write of an associated
register.
Notes:
1. The clearing sequence resets the internal latch.
A pending interrupt (i.e. waiting for being enabled)
will therefore be lost if the clear sequence is executed.
2. All interrupts allow the processor to leave the
Wait low power mode.
3. Exit from Halt mode mayonly be triggered by an
External Interrupton one of theITiports (PA4-PA7
and PB4-PB7), an end suspend mode Interrupt
coming from USB peripheral, or a reset.
ST7263
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INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
Table 7. Interrupt Mapping
BIT I SET
Y
N
IRET
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTEINSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC,X, A,CC FROM STACK
INTERRUPT
Y
N
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Vector
Address
RESET Reset
N/A
Highest
Priority
Lowest
Priority
yes FFFEh-FFFFh
TRAP Software Interrupt no FFFCh-FFFDh
USB End Suspend Mode ISTR
yes
FFFAh-FFFBh
1 ITi External Interrupts ITRFRE FFF8h-FFF9h
2 TIMER Timer Peripheral Interrupts TIMSR
no
FFF6h-FFF7h
3I
2
CI
2
C Peripheral Interrupts
I2CSR1
FFF4h-FFF5h
I2CSR2
4 SCI SCI Peripheral Interrupts SCISR FFF2h-FFF3h
5 USB USB Peripheral Interrupts ISTR FFF0h-FFF1h
ST7263
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INTERRUPTS (Cont’d)
4.1.1 Interrupt Register
INTERRUPTS REGISTER (ITRFRE)
Address: 0008h — Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = ITiE (i=1 to 8).
Interrupt Enable Control
Bits
.
If an ITiE bit is set, the corresponding interrupt is
generated when
– a rising edge occurs on the pin PA4/IT1 orPA5/
IT2 or PB4/IT5 or PB5/IT6
or
– a falling edgeoccurs on the pin PA6/IT3 or PA7/
IT4 or PB6/IT7 or PB7/IT8
No interrupt is generated elsewhere.
Note: Analog input must be disabled for interrupts
coming from port B.
70
IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E
ST7263
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4.2 POWER SAVING MODES
4.2.1 Introduction
To give a large measure of flexibilitytotheapplication interms of power consumption, two mainpower saving modesare implemented in the ST7.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (f
CPU
).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
4.2.2 HALT mode
The HALT mode is the MCU lowest power consumption mode.The HALT modeis entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the
on-chip peripherals.
When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.
The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillatoris then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 16. HALT Mode Flow Chart
N
N
EXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
4096 CPU CLOCK
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
OFF
CLEARED
OFF
Y
Y
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
ST7263
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POWER SAVING MODES (Cont’d)
4.2.3 WAIT mode
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selectedby calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of theCC register is forced to 0, to enable
all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting
address of the interrupt or Reset serviceroutine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure17.
Figure 17. WAIT Mode Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
CLEARED
OFF
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
SET
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CLOCK
CYCLES DELAY
IF RESET
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
ST7263
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5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The I/O ports offer different functional modes:
– transferof datathrough digital inputsandoutputs
and for specific pins:
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital output.
5.1.2 Functional description
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/Opin may be programmed using thecorre-
sponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.
Table 8. I/O Pin Functions
Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Note 1: All the inputs are triggered by a Schmitt
trigger.
Note 2: When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port isconfigured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
Output Mode
The pin is configured inoutput mode by setting the
corresponding DDR register bit (see Table 7).
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note: In this mode, the interrupt function is disabled.
Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in outputmode (push-pull
or open drain according to the peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input.
2. When the on-chip peripheral uses a pin asinput
and output, this pinmust beconfigured as an input
(DDR = 0).
Warning
: The alternate function must not beacti-
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
DDR MODE
0 Input
1 Output
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I/O PORTS (Cont’d)
Analog Alternate Function
When the pin is used as an ADC input theI/O must
be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
Warning
: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
5.1.3 I/O Port Implementation
The hardware implementation on each I/O port depends on the settings in the DDRregister and specific feature of the I/O port such as ADC Input or
true open drain.
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I/O PORTS (Cont’d)
5.1.4 Port A
Table 9. Port A0, A3, A4, A5, A6, A7 Description
Figure 18. PA0, PA3, PA4, PA5, PA6, PA7 Configuration
PORT A
I / O Alternate Function
Input* Output Signal Condition
PA0 with pull-up push-pull MCO (Main Clock Output) MCO = 1 (MISCR)
PA3 with pull-up push-pull Timer EXTCLK
CC1 =1
CC0 = 1 (Timer CR2)
PA4 with pull-up
push-pull
Timer ICAP1
IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
PA5 with pull-up
push-pull
Timer ICAP2
IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
PA6 with pull-up
push-pull
Timer OCMP1 OC1E = 1
IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
PA7 with pull-up
push-pull
Timer OCMP2 OC2E = 1
IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
*Reset State
DR
DDR
LATCH
LATCH
DR SEL
DDR SEL
V
DD
PAD
ALTERNATE ENABLE
ALTERNATEENABLE
ALTERNATE ENABLE
ALTERNATE
ALTERNATE INPUT
PULL-UP
OUTPUT
P-BUFFER
N-BUFFER
1
0
1
0
CMOS SCHMITTTRIGGER
V
SS
V
DD
DIODES
DATA BUS
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I/O PORTS (Cont’d)
Table 10. PA1, PA2 Description
Figure 19. PA1, PA2 Configuration
PORT A
I / O Alternate Function
Input* Output Signal Condition
PA1 without pull-up Very High Current open drain SDA (I2C data) I2C enable
PA2 without pull-up Very High Current open drain SCL (I2C clock) I2C enable
*Reset State
DR
DDR
LATCH
LATCH
DRSEL
DDR SEL
PAD
ALTERNATE ENABLE
ALTERNATEENABLE
ALTERNATE
OUTPUT
N-BUFFER
1
0
1
0
CMOSSCHMITT TRIGGER
V
SS
DATA BUS
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I/O PORTS (Cont’d)
5.1.5 Port B
Table 11. Port B Description
Figure 20. Port B Configuration
PORT B I/O Alternate Function
Input* Output Signal Condition
PB0 without pull-up push-pull Analog input (ADC) CH[2:0] = 000 (ADCCSR)
PB1 without pull-up push-pull Analog input (ADC) CH[2:0] = 001 (ADCCSR)
PB2 without pull-up push-pull Analog input (ADC) CH[2:0]= 010 (ADCCSR)
PB3 without pull-up push-pull Analog input (ADC) CH[2:0]= 011 (ADCCSR)
PB4 without pull-up push-pull
Analog input (ADC) CH[2:0]= 100 (ADCCSR)
IT5 Schmitt triggered input IT4E = 1 (ITIFRE)
PB5 without pull-up push-pull
Analog input (ADC) CH[2:0]= 101 (ADCCSR)
IT6 Schmitt triggered input IT5E = 1 (ITIFRE)
PB6 without pull-up push-pull
Analog input (ADC) CH[2:0]= 110 (ADCCSR)
IT7 Schmitt triggered input IT6E = 1 (ITIFRE)
PB7 without pull-up push-pull
Analog input (ADC) CH[2:0]= 111 (ADCCSR)
IT8 Schmitt triggered input IT7E = 1 (ITIFRE)
*Reset State
DR
DDR
LATCH
LATCH
DR SEL
DDR SEL
V
DD
PAD
ANALOG
SWITCH
ANALOG ENABLE
(ADC)
ALTERNATE ENABLE
ALTERNATE ENABLE
DIGITALENABLE
ALTERNATE ENABLE
ALTERNATE
ALTERNATE INPUT
OUTPUT
P-BUFFER
N-BUFFER
1
0
1
0
V
SS
DATA BUS
COMMON ANALOG RAIL
V
DD
DIODES
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I/O PORTS (Cont’d)
5.1.6 Port C
Table 12. Port C Description
Figure 21. Port C Configuration
PORT C
I / O Alternate Function
Input* Output Signal Condition
PC0 with pull-up push-pull RDI (SCI input)
PC1 with pull-up push-pull TDO (SCI output) SCI enable
PC2 with pull-up push-pull
USBOE (USB output enable)
USBOE =1
(MISCR)
*Reset State
DR
DDR
LATCH
LATCH
DR SEL
DDR SEL
V
DD
PAD
ALTERNATE ENABLE
ALTERNATE ENABLE
ALTERNATE ENABLE
ALTERNATE
ALTERNATE INPUT
PULL-UP
OUTPUT
P-BUFFER
N-BUFFER
1
0
1
0
CMOS SCHMITT TRIGGER
V
SS
V
DD
DATA BUS
DIODES
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