Datasheet ST72F652R4T1, ST72F652, ST72F651R6T1, ST72F651AR6T1, ST72F651 Datasheet (SGS Thomson Microelectronics)

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June 2003 1/166

This is preliminary information on a new product. Details are subject to change without notice.

Rev. 2.3

ST7265x

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K

FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC,

I2C, SPI

DATASHEET

■ Memorie s

– Up to 32K of ROM or High Density Flash (HD-

Flash) program memory wi th read/ write protect ion

– For HDFlash devices, In-Application Pro-

gramming (IAP) via USB and In-Circuit programming (ICP)

– Up to 5 Kbytes of RAM with up to 256 bytes

stack

■ Clock, Re set and Supply Manag e m ent

– PLL for generating 48 MHz USB clock using a

12 MHz crystal

– Low Voltage Reset (except on E suffix devic-

es)

– Dual supply management: analog voltage de-

tector on the USB power line to enabl e s ma rt power switching from USB power to battery (on E suffix devices).

– Programmable Internal Voltage Regul ator for

Memory cards (2.8V to 3.5V) supplying:

Flash Card I/O lines (voltage shifting) Up to 50 mA for Flash card supply

– Clock-out capability

■ 47 pro grammable I/O li ne s

– 15 high sink I/Os (8mA @0.6V / 20mA@1.3V) – 5 true open drain outputs – 24 lines programmable as interrupt inputs

■ USB (Universal Serial Bus) Interface

– with DMA for full speed bulk applications com-

pliant with USB 12 Mbs spec ification (version

2.0 compliant)

– On-Chip 3.3V USB voltage regulator and

transceivers with software power-down

– 5 USB endpoints:

1 control endpoint 2 IN endpoints supporting interrupt and bulk 2 OUT endpoints supporting interrupt and bulk

– Hardware conversion between USB bulk

packets and 512-byte blocks

■ Mass Storage Interface

– DTC (Data Transfer Coprocessor): Universal

Serial/Parallel communications in terface, with software plug-ins for current and f uture prot ocol standards:

Compact Flash - Multimedia Card -

Secure Digital Card - SmartMediaCard Sony Memory Stick - NAND Flash ATA Peripherals

■ 2 Timers

– Configurabl e Watchdog for syst em reli ability – 16-bit Timer with 2 output compare functions.

■ 2 Communication Interfaces

– SPI synchronous serial interface –I

C Single Master Interface up to 400 KHz

■ D/A and A/D Peripherals

– PWM/BRM Generator (with 2 10-bit PWM/

BRM outputs)

– 8-bit A/D Converter (ADC) with 8 channels

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

TQFP64 10x10

TQFP48

SO34 shrink

Features ST72651 ST72F651 ST72652 Program memory 32K ROM 32K FLASH 16K ROM

User RAM (stack) - bytes 5K (256) 512 (256) Peripherals USB, DTC, Timer, ADC, SPI, I

C, PWM, WDT USB, DTC, WDT

Operating Supply

Dual 2.7V to 5.5V or

4.0V to 5.5V (for USB)

Dual 3.0V to 5.5V or

4.0V to 5.5V (for USB)

Single 4.0V to 5.5V

Package TQFP64 (10 x10) TQFP64 (10 x10) / TQFP48 (7x7) / SO34 Operating Temperature 0°C to +70°C

Table of Cont ents

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.1WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.2DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

11.3USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.416-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table of Cont ents

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11.5PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.6SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

11.7I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.88-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.1CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.2INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.1PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.2ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

13.3OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.4SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

13.5CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.6MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13.7EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

13.8I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.9CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149

13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

14.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 159

15.1OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.2DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 160

15.3DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

15.4ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

ST7265x

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1 INTRODUCTION

The ST7265x MCU supports volume data exchange with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of handling various transfer protocols, with a particular emphasis on mass storage applications.

ST7265x is compliant with the USB Mass Storage Class specifications, and supports related protocols such as BOT (Bulk Only Transfer) and CBI (Con tr o l, Bu lk, Interru pt).

It is based on the ST7 standard 8-bit core, with specific peripherals for managing USB f ull speed data transfer between the host and most types of FLASH media card:

– A full speed USB interface with Serial Interface

Engine, and on-chip 3.3V regulator and transceivers.

– A dedicated 24 MHz Data Buffer Manager state

machine for handling 512-byte data blocks (this size corresponds to a sector both on computers and FLASH media cards).

– A Data Transfer Coprocessor (DTC), able to

handle fast data transfer with external devices. This DTC also computes the CRC or ECC required to handle Mass storage media.

– An Arbitration block gives the ST7 core priority

over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC.

– A FLASH Supply Block able to provide program-

mable supply voltage and I/O electrical levels to the FLASH media.

Figure 1. USB Data Transfer Block Diagram

512-byte RAM

Buffer

512-byte RAM

Buffer

DATA

COPROCESSOR

DATA TRANSFER

BUFFER

LEVEL

SHIFTERS

MASS

DEVICE

USB

SIE

ST7 CORE

STORAGE

TRANSFER

(DTC)

ARBITRATIO N

USB DATA

TRANSFER

BUFFER ACCESS

ST7265x

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INTRODUCTION (Cont’d) In addition to the peripherals for USB full speed

data transfer, the ST7265x include s all the neces sary features for stand-alone applications with FLASH mass storage.

– Low voltage reset ensuring proper power-on or

power-off of the device (not on all products) – Digital Watchdog – 16-bit Timer with 2 output compare functions (not

on all products - see device summary). – Two 10-bit PWM out puts (not on all products -

see device summary)

– Serial Peripheral interface (not on all products -

see device summary)

– Fast I

C Single Master interface (not on all prod-

ucts - see device summary)

– 8-bit Analog-to-Digital converter (ADC) with 8

multiplexed analog inputs (not on all products see device summary)

The ST72F65x are the Flash versions of the ST7265x in a TQFP64 package.

The ST7265x are the ROM versions in a TQ FP64 package.

Figure 2. Digital Audio Player Application Example in Play Mode

512-byte RAM

Buffer

512-byte RAM

Buffer

DATA

COPROCESSOR

DATA TRANSFER

BUFFER

LEVEL SHIFTERS

MASS

DEVICE

ST7 CORE

STORAGE

TRANSFER

(DTC)

ARBITRATION

BUFFER ACCESS

DIGITAL

AUDIO DEVICE

I2C

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INTRODUCTION (Cont’d) Figure 3. ST7265x Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSCIN

OSCOUT

RESET

DATA

PD[7:0] (8 bits)

12MHz

CPU

CONTROL

RAM

(0.5/5 KBytes)

PROGRAM

(16/3 2 Kbytes)

MEMORY

16-BIT TIMER*

LVD*

WATCHDOG

DDA

USBDP USBDM USBVCC

* not on all pr oducts (refer to Tabl e 1: Devic e S ummary )

TRANSF ER

COPROCESSOR

PORT C

PORT E

PORT D

PE[7:0]

(8 bits)

PC[7:0]

(8 bits)

PB[7:0]

(8 bits)

PA[7:0]

(8 bits)

PORT F

PF[6:0]

(7 bits)

8-BIT ADC*

FLASH SUPPLY

DDF

SSA

POWER SUPPLY

DUAL SUPPLY

USBVSS

MANAGER *

BLOCK

48MHz

PLL

CLOCK

DIVIDER

OSC

USB

SSF

USBVDD

SS1, VSS2

DD1,VDD2

PWM*

PORT B

PORT A

DATA

TRANSFER

BUFFER

(1280 by tes)

DTC S/W RAM

(256 Bytes)

REGULATOR

ARBITRATION

SPI *

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2 PIN DESCRIPTION

Figure 4. 34-Pin SO Package Pinout

28 27 26 25 24 23 22 21 20 19 18

DDA

DD2

PC3 (HS) / DTC

DD1

SS1

PD0

PD1

PD2

PD3

PD5

PD6

/ICCSEL

RESET

PF6 (HS) / ICCDATA

PD4

PF5 (HS) / ICCCLK

1 2 3 4 5 6 7 8

9 10 11 12 13 14

SSA

SS2

MCO / (HS) PC0

DTC / PA3

DTC / PA2

DTC / PA1

DTC / PA0

SSF

DDF

USBVCC

USBDM

USBV

OSCOUT

OSCIN

USBV

PC2 (HS) / DTC

DTC / (HS) PC1

USBDP

(HS) high sink capability ei

associated external interrupt vector

I/O pi n supplie d by V

DDF

/ V

SSF

ei1

ei0

ei2

ST7265x

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PIN DESCRIPTION (Cont’d) Figure 5. 48-Pin TQFP Package Pinout

44 43 42 41 40 39 38 37

36 35

33 32 31 30 29 28 27 26 25

13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

DDAVDD2

PF6 (HS) / ICCDATA

PF5 (HS)/ICCCLK

RESET

PP/

ICCSEL

PE4

OSCOUT

OSCIN

SS2VSSA

USBV

DDF

SSF

DTC/PB0 DTC/PB1

DTC/PB3

USBV

USBDM

USBDP

USBVCC

DTC / PA0

DTC / PA1

DTC / PA2

DTC / PA3

DTC / PA4

DTC / PA5

DTC / PA6

DTC / PA7

DTC/PB5

DTC/PB6

DTC/PB7

PE2 (HS) / DTC PE1 (HS) / DTC PE0 (HS) / DTC PD7

SS1

DD1

PD0

PD1

PD2

PD3

PD5

PD6

PD4

PE3/DTC

DTC/PB2

DTC/PB4

(HS) high sink capability ei

associated external interrupt vector

I/O pi n supplie d by V

DDF

/ V

SSF

ei1

ei0

ST7265x

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PIN DESCRIPTION (Cont’d) Figure 6. 64-Pin TQFP Package Pinout

DTC / PA2

DTC / PA3

DTC / PA4

DTC / PA5

DTC / PA6

DTC / PA7

/ MCO / (HS) PC0

MISO / DTC / (HS) PC1

MOSI / DTC / (HS) PC2

SCK / DTC / (HS) PC3

DD1

SS1

DTC / PB6

DTC / PB7

DTC / PA0

DTC / PA1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

47 46 45 44 43

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei1

ei0

USBV

DDF

SSF

DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS)

DTC / PB0 DTC / PB1 DTC / PB2 DTC / PB3 DTC / PB4 DTC / PB5

USBV

USBDM

USBDP

USBVCC

PD7 / AIN3 PD6 / AIN2 PD5/OCMP2 PD4/OCMP1 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4

PE3 / PWM0 / AIN7 / DTC PE2 (HS) / AIN6 / DTC PE1 (HS) / AIN5 / DTC PE0 (HS) / AIN4 / DTC

DDAVDD2

PF6 (HS)/ICCDATA

PF5 (HS)/ICCCLK

PF4 (HS) / USBEN

PF3 / AIN1

PF2 / AIN0

PF1 (HS) / SDA

PF0 (HS) / SCL

RESET

/ICCSEL

PE4 / PWM1

OSCOUT

OSCIN

SS2VSSA

(HS) high sink capability ei

associated externalinterruptvector

I/O pi n supplie d by V

DDF

/ V

SSF

ei2

ST7265x

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PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type: I = input, O = output, S = supply V

DDF

powered: I/O powered by the alternate sup-

ply rail, supplied by V

DDF

and V

SSF

In/Output level: C

= CMOS 0.3VDD/0.7VDD with

input trigger Output level: HS = High Sink (on N-buffer only)

Port and control configuration: – Input:float = floatin g, wpu = weak pull -up, int = i n-

terrupt

– Output: OD = open drain, T = true open drain, PP

= push-pull, OP = pull-up enabled by option byte.

Refer to “I/O PORTS” on page 49 for more details on the software configuration of the I/O ports.

The RESET conf iguration of eac h pin is shown in bold.

Table 1. Device Pin Description

Pin Name

Type

DDF

Powered

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO34

TQFP48

TQFP64

Input

Output

Input Output

float

wpu

int

511USBV

S USB Digital ground 6 2 2 USBDM I/O USB bidirectional data (data -) 7 3 3 USBDP I/O USB bidirectional data (data +)

8 4 4 USBVCC O

USB power supply, output by the on-chip USB

3.3V linear regulator. Note: An external decoupling capacitor (typ. 100nF, min 47nF) must be connected between this pin and USBV

955USBV

USB Power supply voltage (4V - 5.5V) Note: External decoupling capacitors (typ.

4.7µF+100nF, min 2.2µF+100nFmust be connected between this pin and USBV

10 6 6 V

DDF

Power Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator). Note: An external decoupling capacitor (min. 20nF) must be connected to this pin to stabilize the regulator.

11 7 7 V

SSF

Ground Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator)

- - 8 PE5/DTC I/O X C

HS X

X2X Port E5

DTC I/O with serial capability (MMC_CMD)

- - 9 PE6/DTC I/O X C

HS X X X Port E6

DTC I/O with serial capability (MMC_DAT)

- - 10 PE7/DTC I/O X C

HS X X X Port E7

DTC I/O with serial capability (MMC_CLK)

- 8 11 PB0/DTC I/O X

X X Port B0 DTC

- 9 12 PB1/DTC I/O X

X X Port B1 DTC

- 10 13 PB2/DTC I/O X

X X Port B2 DTC

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-1114PB3/DTC I/O X

X X Port B3 DTC

- 12 15 PB4/DTC I/O X

X X Port B4 DTC

- 13 16 PB5/DTC I/O X

X X Port B5 DTC

- 14 17 PB6/DTC I/O X

X X Port B6 DTC

- 15 18 PB7/DTC I/O X

X X Port B7 DTC

12 16 19 PA0/DTC I/O X

X X Port A0 DTC

13 17 20 PA1/DTC I/O X

X X X Port A1 DTC

14 18 21 PA2/DTC I/O X

X X X Port A2 DTC

15 19 22 PA3/DTC I/O X

X X X Port A3 DTC

- 20 23 PA4/DTC I/O X

X X X Port A4 DTC

- 21 24 PA5/DTC I/O X

X X X Port A5 DTC

- 22 25 PA6/DTC I/O X

X X X Port A6 DTC

- 23 26 PA7/DTC I/O X

X X X Port A7 DTC

16 - 27 PC0/MCO/SS

I/O X

HS X

X Port C0

Main Clock Output / SPI Slave Select

17 - 28 PC1/DTC/MIS0 I/O X CTHS X X Port C1

DTC I/O with serial capability (DATARQ) / SPI Master In Slave Out

18 - 29 PC2/DTC/MOSI I/O X CTHS X X Port C2

DTC I/O with serial capability (SDAT) / SPI Master Out Slave In

19 - 30 PC3/DTC/SCK I/O X CTHS X X Port C3

DTC I/O with serial capability (SCLK) / SPI Serial Clock

20 24 31 V

DD1

S Power supply voltage (2.7V - 5.5V)

21 25 32 V

SS1

S Digital ground

- - 33 PC4/DTC I/O C

X Port C4 DTC

- - 34 PC5/DTC I/O C

X X Port C5 DTC

- - 35 PC6/DTC I/O C

X X Port C6 DTC

- - 36 PC7/DTC I/O C

X X Port C7 DTC

Pin Name

Type

DDF

Powered

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO34

TQFP48

TQFP64

Input

Output

Input Output

float

wpu

int

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22 26 37 PD0 I/O

X X Port D0

23 27 38 PD1 I/O

X X X Port D1

24 28 39 PD2 I/O

X X X Port D2

25 29 40 PD3 I/O

X X X Port D3

26 30 41 PD4/OCMP1 I/O

X X X Port D4 Timer Output Compare 1

27 31 42 PD5/OCMP2 I/O

X X X Port D5 Timer Output Compare 2

28 32 43 PD6/AIN2 I/O

X X X Port D6 Analog Input 2

- 33 44 PD7/AIN3 I/O

X X X Port D7 Analog Input 3

- 34 45 PE0/DTC/AIN4 I/O

HS X X X Port E0 Analog Input 4

/ DTC

- 35 46 PE1/DTC/AIN5 I/O C

HS X X X Port E1 Analog Input 5

/ DTC

- 36 47 PE2/DTC/AIN6 I/O C

HS X X X Port E2 Analog Input 6

/ DTC

-3748

PE3/AIN7/DTC/ PWM0

I/O C

X X X Port E3

Analog Input 7

/ DTC / PWM

Output 0

- 38 49 PE4/PWM1 I/O C

X X X Port E4 PWM Output 1

29 39 50 VPP /ICCSEL S

Flash programming voltage. Must be held low in normal operating mode.

30 40 51 RESET

I/O X X

Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or V

is low. It can be used to reset ex-

ternal peripherals.

- - 52 PF0 / SCL I/O C

HS X T Port F0 I2C Serial Clock

- - 53 PF1 / SDA I/O CTHS X T Port F1 I2C Serial Data

- - 54 PF2 / AIN0 I/O C

X X Port F2 Analog Input 0

- - 55 PF3 / AIN1 I/O C

X X Port F3 Analog Input 1

- - 56 PF4 / USBEN I/O CTHS X T Port F4

USB Power Management USB Enable (alternate function selected by option bit)

31 41 57 PF5 / ICCCLK I/O C

HS X T Port F5 ICC Clock Output

32 42 58 PF6 / ICCDATA I/O C

HS X T Port F6 ICC Data Input

33 43 59 V

DD2

Main Power supply voltage (2.7V - 5.5V on devices without LVD, otherwise 4V - 5.5V).

34 44 60 V

DDA

S Analog supply voltage

Pin Name

Type

DDF

Powered

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO34

TQFP48

TQFP64

Input

Output

Input Output

float

wpu

int

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If the peripheral is present on the device (see Device Summary on page 1)

A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register

and depending on the PE5PU bit in the option byte.

14561V

SSA

S Analog ground 24662V

SS2

S Digital ground 3 47 63 OSCIN I

Input/Output Oscillator pins. These pins connect a 12 MHz parallel-resonant crystal, or an external source to the on-chip oscillator.

4 48 64 OSCOUT O

Pin Name

Type

DDF

Powered

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO34

TQFP48

TQFP64

Input

Output

Input Output

float

wpu

int

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Figure 7. Multimedia Card Or Secure Digital Card Writer Application Example

(1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

(2) As this is a single power s upply applicatio n, the USBEN function in not needed. Thus PF4/USBEN pin can be

used as a normal I/O by con figurin g it as suc h by the option byte.

MultiMedia Card Pin CMD DAT CLK

ST72F65 pin PE5 PE6 PE7 ST7 / DTC

(1)

DTC DTC DTC

VCC

USB

USBV

DTC

USB Port

FLASH

DDF

VPP

GND

USB

4.7µF

USBVDD

POWER

USB

MANAGEMENT

GND

100nF

12V for

LED2

level translator

Flash prog.

REGULATOR

I/O

LOGIC

=4.0-5.5V

UP TO 5

MULTIMEDIA

OR SD CARD S

CLK DAT CMD

PE7 PE6

PE5

(2)

100nF

1.5KΩ

LED1

(connec t t o GND if not used)

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Figure 8. Smartmedia Card Writer Or Flash Drive Application Example

Table 2. SmartMedia Interface Pin Assignment

(1): This line shows if the ST72F65 pin is controlled by the ST7 core or the DTC.

(2): These line s are not cont rolled by the D TC but b y the user software running on the ST7 core. The ST72F65 pin choice is at customer discretion. The pins shown here are only shown as an example.

(3): When a sin gle card is to be ha ndled, PA7 is free fo r other functions. When 2 Smar tmedia are to b e handled, pins from both cards should be tie d together (i.e. CLE1

with CLE2...) exc ept for the CE pin s. CE pin from ca rd 1 should be connected to PA6 and CE pin from card 2 should be connect to PA7. Selection of the operating card is done by ST7 software.

(4) As this is a single power supply applica tion, the U SBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by con figurin g it as suc h by the option byte.

DTC

FLASH

DDF

VPP

POWER

MANAGEMENT

100nF

12V for

level translator

Flash prog.

REGULAT O R

I/O

LOGIC

UP TO 2

SMARTMEDIA

CARDS

PAPB

I/O

0~7

CTRL

(4)

VCC

USB

USBV

USB Port

GND

USB

4.7µF

USBVDD

USB

GND

=4.0-5.5V

100nF

1.5K

Ω

LED2

LED1

(connec t t o GND if not used)

SmartMedia Pin I/O0~7 CLE WE ALE RE R/B WP

(2)

CE1

(2)

CE2

(2)(3)

ST72F65 pin PB0-7 PA0 PA1 PA2 PA3 PA4 PA7 PE1 PE0

ST7 / DTC

(1)

DTC DTC DTC DTC DTC DTC ST7 ST7 ST7

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Figure 9. Compact Flash Card Writer Application Example

Table 3. Compact Flash Card Writer Pin Assignment

(1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

(2) These lines are not co ntrolled b y the DTC but by the user software running on the ST7 core. The choice of ST72F65 pin is at the customer’s discretion. The pins shown here are given only as an example.

(3) As this is a single power supply applica tion, the U SBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by con figurin g it as suc h by the option byte.

Compact Flash

Card Pin

D0-7 D8-15

VS1

, VS2, WAIT,

CS1

, INPAC K ,

BVD1

, BVD2

IORD,

IOWR

, REG,

CE2

, V

CSEL,

RESET,

GND,

A3-10

A0-2 CE1

RE WE CD1

CD2,

RDY/BSY,

ST72F65 pin PB0-7 NC NC V

DDF

SSF

PA0-2

PE2

+pull-up

4.7kΩ

PA3 PA5

PA6

+pull-up

100kΩ

ST7 / DTC

(1)

DTC - - Power Power DTC ST7 DTC DTC ST7 -

DTC

FLASH

DDF

VPP

POWER

MANAGEMENT

100nF

level

REGULATOR

I/O

LOGIC

8-BIT MEMORY

MODE

6 8

(3)

PE [2]

translator

LED1

VCC

USB

USBV

USB Port

GND

USB

4.7µF

USBVDD

USB

GND

=4.0-5.5V

100nF

1.5K

Ω

4.7µF

LED2

12V for Flash prog.

(connect to GND if not used)

4.7K

Ω

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Figure 10. Sony Memory Stick Writer Application Example

(1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

(2) As this is a single power s upply applicatio n, the USBEN function in not needed. Thus PF4/USBEN pin can be

used as a normal I/O by con figurin g it as suc h by the option byte.

MultiMedia Card Pin CMD DAT CLK

ST72F65 pin PE5 PE6 PE7 ST7 / DTC

(1)

DTC DTC DTC

VCC

USB

USBV

DTC

USB Port

FLASH

DDF

VPP

GND

USB

4.7µF

USBVDD

POWER

USB

MANAGEMENT

GND

100nF

12V for

LED2

level translator

Flash prog.

REGULATOR

I/O

LOGIC

=4.0-5.5V

SONY

MEMORY STICK

PC3 PC1

PC2

(2)

100nF

1.5KΩ

LED1

(connec t t o GND if not used)

PC0

CD CLK BS DAT

4.7µF

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3 REGISTER & MEMORY MAP

As shown in Figure 11, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 80 bytes of register locations, up to 5 Kby tes of RA M and up to 32 Kbytes of user program memory. The RAM space includes u p to 256 by t es fo r the stack from 0100h to 01FFh.

The highest address bytes contain the user re set and interrupt vectors.

IMPORTANT: Memory locations noted “Reserved” must ne ver be accessed. Ac cessing a reserved area can have unpredictable effects on the device.

Figure 11. Memory Map

* Program memory and RAM sizes are product dependent (see Table –) ** The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in stan-

dalone mode.

0000h

Interrupt & Reset Vectors

HW Registers

0050h

004Fh

(see Table 4)

FFDFh FFE0h

FFFFh

(see Table 10)

8000h

7FFFh

Program Memory*

5 KBytes RAM*

16 Kbytes

C000h

Reserved

1450h

144Fh

32 Kbytes

512 Bytes RAM*

Short Addressing

Stack (256 Bytes)

0100h

0200h

144Fh

0050h

00FFh

01FFh

16-bit Addressing RAM

RAM (176 Bytes)

(4688 Bytes)

Short Addressing

Stack (256 Bytes)

0100h

0200h

024Fh

0050h

00FFh

01FFh

16-bit Addressing RAM

RAM (176 Bytes)

(80 Bytes)

154Fh

1A4Fh

256 Bytes

1280 Bytes

USB Data Buffer**

DTC RAM (Write protected)

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Table 4. Hardware Register Memory Map

Address Block Register Label Register name Reset Status Remarks

0000h 0001h 0002h

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

00h 00h 00h

R/W R/W R/W

0003h 0004h

PBDR PBDDR

Port B Data Register Port B Data Direction Register

00h 00h

R/W

R/W 0005h Reserved Area (1 byte) 0006h

0007h 0008h

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register Port C Option Register

00h 00h 00h

R/W

R/W 0009h

000Ah 000Bh

PDDR PDDDR PDOR

Port D Data Register Port D Data Direction Register Port D Option Register

00h 00h 00h

R/W

R/W 000Ch

000Dh 000Eh

PEDR PEDDR PEOR

Port E Data Register Port E Data Direction Register Port E Option Register

00h 00h 00h

R/W

R/W 000Fh

0010h

PFDR PFDDR

Port F Data Register Port F Data Direction Register

00h 00h

R/W

R/W 0011h Reserved Area (1 byte) 0012h

0013h

ADC

ADCDR ADCCSR

ADC Data Register ADC Control Status Register

00h 00h

Read only

R/W 0014h WDG WDGCR Watchdog Control Register 7Fh R/W 0015h

to 0017h

Reserved Area (3 bytes)

0018h DSM PCR Power Control Register 00h R/W

0019h 001Ah 001Bh

SPI

SPIDR SPICR SPICSR

SPI Data I/O Register SPI Control Register SPI Control/Status Register

xxh 0xh 00h

R/W

R/W 001Ch

001Dh 001Eh 001Fh

DTC

DTCCR DTCSR Reserved DTCPR

DTC Control Register DTC Status Register

DTC Pointer Register

00h 00h

00h

R/W

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0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah

TIM

TCR1 TCR2 TSR CHR CLR ACHR ACLR OC1HR OC1LR OC2HR OC2LR

Timer Control Register 1 Timer Control Register 2 Timer Status Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register

00h 00h 00h FFh FCh FFh FCh 80h 00h 80h 00h

R/W

Read Only

R/W

R/W 002Bh Flash Flash Control Status Register 00h R/W 002Ch

002Dh 002Eh 002Fh

ITC

ITSPR0 ITSPR1 ITSPR2 ITSPR3

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

FFh FFh FFh FFh

R/W

R/W 0030h

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

USB

USBISTR USBIMR USBCTLR DADDR USBSR EP0R CNT0RXR CNT0TXR EP1RXR CNT1RXR EP1TXR CNT1TXR EP2RXR CNT2RXR EP2TXR CNT2TXR

USB Interrupt Status Register USB Interrupt Mask Register USB Control Register Device Address Registe r USB Status Register Endpoint 0 Register EP 0 Reception Counter Register EP 0 Transmission Counter Register Endpoint 1 Register EP 1 Reception Counter Register Endpoint 1 Register EP 1 Transmission Counter Register Endpoint 2 Register EP 2 Reception Counter Register Endpoint 2 Register EP 2 Transmission Counter Register

00h 00h 06h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

R/W

R/W 0040h

0041h 0042h 0043h 0044h 0045h 0046h

2C 1

I2CCR I2CSR1 I2CSR2 I2CCCR Not used Not used I2CDR

C Control Register

C Status Register 1

C Status Register 2

C Clock Control Register

C Data Register

00h 00h 00h 00h

00h

R/W

Read only

R/W

R/W 0047h USB BUFCSR Buffer Control/Status Register 00h R/W 0048h Reserved Area (1 Byte) 0049h MISCR1 Miscellaneous Register 1 00h R/W 004Ah MISCR2 Miscellaneous Register 2 00h R/W 004Bh Reserved Area (1 Byte)

Address Block Register Label Register name Reset Status Remarks

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Note 1. If the peripheral is present on the device (see Device Summary on page 1)

004Ch MISCR3 Miscellaneous Register 3 00h R/W 004Dh

004Eh 004Fh

PWM

PWM0 BRM10 PWM1

10-bit PWM/BRM registers

80h 00h 80h

R/W

Address Block Register Label Register name Reset Status Remarks

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4 FLASH PROGRAM MEMORY

4.1 Introduc t ion

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugge d in a programm ing tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organ isation allows each sector to be erased and reprogramm ed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes:

– Insertion in a programming tool. In this m ode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board a nd wh ile the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection against piracy

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flas h memory when only a partial erasing is required.

The first two sectors have a fixed siz e of 4 Kby tes (see Figure 12). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 5. Sectors available in Flash devices

4.4 Program Memo ry Read-out Protecti on

The read-out protection is enabled through an option bit.

When this option is selected, the programs and data stored in the program memory (Flash or ROM) are protected against read-out piracy (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, th e entire program memory is first automatically erased and the device can be reprogrammed.

Refer to the Option By te description for more details.

Figure 12. Memory Map and Sector Address

Flash Memory Size

(bytes)

Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4 Kbytes

2Kbytes

SECTOR 1 SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K DV FLASH

FFFFh

EFFFh

DFFFh

3FFFh 7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes

52 Kbytes

9FFFh BFFFh D7FFh

4K 10K 24K 48K

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code dow nloaded in RAM, Flash memory programming can be fully customized (number of bytes to prog ram, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supp orts ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 13). For more details on the pin locations, refer to the device pinout description.

ICP needs six pins to be connected to the programming tool. These pins are:

– RESET

: device reset

–V

: device power supply ground – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin

– ICCSEL/V

: programming voltage

–V

: application board power supply

CAUTIONS:

1. If RESET

, ICCCLK or ICCDATA pins are used for other purposes in the application, a serial resistor has to be implemented to avoid a conflict in case one of the other devices forces the signal level. If these pins are used as outputs in the application, the serial resistors are not necessary. As soon as the external controller is plugged to the board, even if an ICC sess ion is not in progress, the ICCCLK and ICC DATA pins are not available for the application.

2. The use of Pin 7 of the ICC con nector de pends on the Programming Tool architecture. Please refer to the documentatio n of the tool. This pi n m ust be connected when using ST Prog ramming Tools (it is used to monitor the application power supply).

Note: To develop a custom program ming t ool, refer to the ST7 Flash Programming and ICC Reference Manual which gives full details on the ICC protocol hardware and software.

Figure 13. Ty pi c al IC P Int erf ace

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTORTYPE

>4.7kΩ

APPLICATION POWER SUPPLY

OPTIONAL (SEE CAUTION 1)

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPL ICATION BOAR D

ICC C a ble

OPTIONAL (SEE CA UTION 2)

10kΩ

VSS

ICCSEL/VPP

ST7

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FLASH PROGRAM MEMORY (Cont’d)

4.6 IA P ( I n-Applicatio n P rogramm i ng)

This mode uses a BootLoader program previously stored in Sector 0 by the us er (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of comm unications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Fl ash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash program ming and I CC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.8 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Table 6. FLASH Register Map and Reset Values

00000000

Address

(Hex.)

Label

76543210

002Bh

FCSR

Reset Value

00000000

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5 CENTRAL PRO CESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in Figu re 14 are not present in the memory mapping and are accessed by spec ifi c ins t ru c tio n s .

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the res ults of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as tempo rary storage areas f or data manipulation. (The Cross -Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 14. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

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CENTRAL PROC ESSING UNIT (Cont’d) Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

The 8-bit Condition Code regist er contains the i nterrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instructions. It is reset by hardware during the same instructio n s.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutine s .

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. I t’s a copy of the result 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accesse d by the JRMI and JRPL instructions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions. Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an un derflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It i s also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Managem ent B i ts

Bit 5,3 = I1, I0

Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

11I1HI0NZ

Interrupt Software Priorit y I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

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CENTRAL PROC ESSING UNIT (Cont’d) Stack Poi nter (SP)

Read/Write Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 15).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hard ware. Following a n MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to sav e the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location po inted t o by t he SP. Th en t he other registers are stored in the next locations as shown in Figure 15.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ion s i n the stack ar ea.

Figure 15. Stack Manipulation Examp le

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

PCH

PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

PCL

PCH

PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

6.1 CLOCK SYSTEM

6.1.1 General Description

The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock (f

CPU

) is derived from the inter-

nal oscillator frequency (f

OSC

), which is 12 Mhz in

Stand-alone mode and 48M hz in USB mode. The internal clock (f

CPU

) is software selectable using the CP[1:0] and CPEN bits in the MISCR1 register.

In USBV

power supply mode, the PLL is active, generating a 48MHz clock to the USB. In this mode, f

CPU

can be configured to be up to 8 MHz. In V

mode the PLL and the USB clock are disa-

bled, and the maximum frequency of f

CPU

is 6

MHz. The internal clock signal (f

CPU

) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.

The internal oscillat or is designed to operate with an AT-cut parallel resonant quartz in the frequency range specified for f

osc

. The circuit shown in Fig-

ure 17 is recommended when using a crystal, and Table 7 lists the recommen ded capacitance. The

crystal and associated components should be mounted as close as p ossible to the input pins i n order to minimize output distortion and start-up stabilisation time.

Table 7. Recom m ended Values for 12-MHz Crystal Resonator

Note: R

SMAX

is the equivalent serial resistor of the

crystal (see crystal specification).

6.1.2 External Clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 16. The t

OXOV

specifications does not apply when using an external clock input. The equivalent spe cification of the external c lock source should be used instead of t

OXOV

(see Sec-

tion 6.5 CONTROL TIMING).

Figure 16. External Clock Source Connections

Figure 17. Crystal Resonator

SMAX

20 Ω 25 Ω 70 Ω

OSCIN

56pF 47pF 22pF

OSCOUT

56pF 47pF 22pF

OSCIN OSCO UT

EXTERNAL

CLOCK

OSCIN OSCOUT

OSCIN

OSCOUT

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6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introd uc tion

The reset sequence manager in cludes three RESET sources as shown in F igure 6.2.2:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 18:

■ Active Phase depending on the RESET source

■ Min 512 CPU clock cycle delay (see Figure 20

and Figure 21

■ RESET vector fet ch

Figure 18. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

w(RSTL)out

RUN

h(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN RUN

RESET

RESET SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET(min 512T

CPU

)

VECTOR FETCH

w(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

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RESET SEQUENCE MANAGER (Cont’d)

6.2.2 Asynchronous External RES ET

The RESET

pin is both an input and an open-drain

output with integrated R

weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the elect rical characteristics section.

If the external RESET

pulse is shorter than

w(RSTL)out

(see short ext. Reset in Figure 18), the

signal on the RESET

pin will be stretch ed. Other wise the delay will not be applied (see long ext. Reset in Figure 18).

Starting from the external RE SET pulse recognition, the device RESET

pin acts as an output that

is pulled low during at least t

w(RSTL)out

6.2.3 Int e r na l Lo w Volta ge Detection RESET

Two differe nt RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET

pin acts as an output that is

pulled low when V

DD<VIT+

(rising edge) or

DD<VIT-

(falling edge) as shown in Figure 18.

The LVD filters spikes on V

shorter than t

g(VDD)

to avoid parasitic resets.

6.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 18.

Starting from the Watchdog counter underflow, the device RESET

pin acts as an output that is pulled

low during at least t

w(RSTL)out

Figure 19. Reset Block Diagram

CPU

COUNTE R

RESET

WATCHDOG RESET

LVD RESET

INTERNAL RESET

PULSE

GENERATO R

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RESET SEQUENCE MANAGER (Cont’d) In stand-alone mode, the 512 CPU clock cycle de-

lay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state.

In USB mode the dela y is 25 6 clock cycles counted from when the PLL LOCK signal goes high.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 20. Reset Delay in Stand-alone Mode

Figure 21. Reset Delay in USB Mode

Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.

512 x t

CPU(STAND-ALONE)

RESET

FETCH VECTOR

DELAY

FETCH VECTOR

256 x t

CPU(STAND-ALONE)

256 x t

CPU(USB)

PLL Startup

RESET

time (undefined)

DELAY

400 µs typ.

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6.3 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V

supply voltage is below a V

IT-

reference value. This means that it secures the power-up as well as the power-down, keeping the ST7 in reset.

The V

IT-

reference value for a voltage drop is lower

than the V

IT+

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry gene rates a reset when V

is below:

–V

IT+

when VDD is rising

–V

IT-

when VDD is falling

The LVD function is illustrated in Fi gure 22. During a Low Voltage Detector Reset, the RESET

pin is held low, thus p ermitting the MCU to reset other devices.

Figure 22. Low Voltage Detector vs Reset

IT+(LVD)

RESET

IT-(LVD)

hyst

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6.4 POWER SUPPLY MANAGEMENT

6.4.1 Single Power Supply Management

In applications operating only when connected to the USB (Flash writers, Backup systems), the microcontroller must operate from a single power supply (i.e. USB bus power supply or the local power source in the case of self-powered devices). Devices with LVD (no E suffix) or without LVD (E suffix) can support this configuration.

In order to enable the Sing le Power Supply Management, the PLGIE bit in the PCR register should kept cleared by software (reset default value).

In this case, pin V

and USBVDD of the microcontroller must be connected together and supplied by a 4.0 to 5.5V voltage supply, either from the USB cable or from the local power source. See

Figure 23.

Figure 23. Sin gl e Po wer S up pl y Mo de

In this mode: – The PLL is running at 48 MHz

– The on-chip USB interface is enabled – The core can run at up to 8MHz internal frequen-

– The microcontroller can be either USB bus pow-

ered or supplied by the local power source (self powered)

– The USBEN

function is not used. The PF4 pin can be configured to work as a normal I/O by programming the Option Byte.

6.4.2 Dual Power Supply Management

In case of a dev ice that can be used both when powered by the USB or from a battery (Digital Audio Player, Digital Camera, PDA), the microcon-

troller can operate in two power supply modes:

Stand-alone

Mode and

USB

Mode. This configuration is only available on devices without LVD (E suffix). Devices with LVD are kept under reset when the power supply drops below the LVD threshold voltage and thus Stand-Alone mode can not be ente red.

In order to enable Dual Power Supply Management:

– the USBEN

pin function must be selected by pro-

gramming the option byte.

– the user software must set the PLGIE bit in the

PCR register in the initialization routine.

Stand-Alone Mode

This mode is t o be us ed when no USB com munication is needed. The microcontroller in this mode can run at very l ow voltage, mak ing the de sign of low power / battery supplied s ystem s easy . In this mode:

– The USB cable is unplugged (no voltage input on

USBV

pin) – The PLL is off – The on-chip USB interface is disabled – The core can run at up to 6 MHz internal frequen-

– USBEN

is kept flo a ting b y H /W.

– The microcon troller is supplied through the V

USB Mode

When connected to t he USB, the microcontroller can run at full speed, still saving battery power by using USB power or self power source. To go into USB mode, a voltage from 4.0 V to 5.5V must be provided to the USBV

pin. In this mode: – The USB cable is plugged in – USBV

pin is supplied by a 4.0 to 5.5V supply voltage, either from the USB cable or from the self powering source

– The PLL is running at 48 MHz – The on-chip USB interface is enabled – The core can run at up to 8 MHz internal frequen-

– USBEN

is set to output low level by hardwa re. This signal can be used to control an external transistor (USB SWITCH) to change the power supply configuration (see Figure 24).

– The microcontroller can be USB bus powered

DD1

DD2

DDA

USBV

ST7

4.0 - 5.5 V Note: Ground lines not shown

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POWER SUPPLY MANAGEMENT (Cont’d)

6.4.2.1 Switching from Stand-Alone Mode to USB Mode

In Stand-Alone Mode, when the user plugs in the USB cable, 4V min. is input to USBV

. The onchip power Supply Manager generates an internal interrupt when USBV

reaches USBV

IT+

(if the PLGIE bit in the PCR register is set). The user program then can f inish the current proces sing, and MUST generate a software RESET

afterwards.

This puts the microcontroller into reset state an d all I/O ports go into input high impedance mode.

During and after this (software induced) reset phase, the USBEN

pin is set to output low level by hardware. This causes the USB SWITCH to be turned ON. Co nsequently, V

pin is powered by

USBV

supply. See Figure 24.

Once in USB mode, no power is drawn from the step-up converter output.

For more details, refer to Figure 25.

Figure 24. External Power Supply Switch

DD1

USB SWITCH

DD2

DDA

USBV

USBEN

ST7

(True OD, H/W crtl)

Step-up converter

4V min. from USB

Note 1: Ground lines not shown

PCR REGISTER

PLG

General Purpose I/O (I/O port DR, DDR)

Option bit

USBEN

H/W

CONTROL

USBV

IT-

USBV

IT+

USBV

IT-

PLG bit

USBV

Alternate Function (USBEN)

PMOS

VITPF

USBV

IT+

VITMF Bit VITPF Bit

PLGIE

VITMF

Interrupt Request

RESET

LOGIC

S/W RESET

EDGE DETECTOR

USB VOLTAGE DETECTOR

WITH LATCH

DETEN

(Note 2)

Note 2: Suggest ed device: IRLML 6302 (Internat iona l rectifier) or Si230DS (Siliconix)

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POWER SUPPLY MANAGEMENT (Cont’d)

6.4.2.2 Switching from USB Mode to StandAlone Mode

In USB Mode, when the user unplugs the USB cable, the voltage level drops on the USBV

line. The on-chip Power Supply Manager generates a PLG interrupt when USBV

reaches USBV

IT-

. The user program then can finish the current processing, and MUST generate a software RESET.

Caution: Care should be taken as during this period the microcontroller clock is provided from the PLL output. Functional ity in this m ode is not guaranteed for voltages below V

PLLmin

Software must ensure that the software RESET

generated before V

. drops below V

PLLmin

. Fail ing to do this will cause the clock circuitry to s top, freezing the microcontroller operations.

Once the user program has executed the software reset, the microcontroller goes into reset state and all I/O ports go into floating input mode.

During and after this (software induced) reset phase, the USBEN

pin is put in high impedance by hardware. It causes the USB SWITCH to be turned OFF, so USBV

is disconnected from

. The PLL is automatically stopped and the internal frequency is provided by a division of the crystal frequency. Refer to F i gure 25.

The microcontroller is still powered by the residual USBV

voltage (higher than step-up converter

set output le v el) . Th is V

voltage decreases during the reset phase until it reaches the step-up converter set output voltage. At that time, step-up converter resumes operation, and p owers the application.

Caution: In order to avoid applying excessive voltage to the Storage Media , a minimu m delay must be ensured during (and after if needed) the reset phase, prior to switching O N the external STORAGE switch. See Figure 26 and Figure 27.

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POWER SUPPLY MANAGEMENT (Cont’d) Figure 25. Power Supp ly M ana g em e n t: Dual Power Su ppl y

USB MODE

STAND-ALONE STAND-ALONE

RESET

S/W

STAND-ALONE

USBV

PLL

48 MHz

CLOCK

CRYSTAL (12MHz)

PLL

CRYSTAL (12MHz)

S/W Reset

PLG INTERRUPT

SUPPLY

USBV

IT+

REQUEST

USBV

IT-

STATUS

PROCESSING

1. Interrupt processing

2. Finish current processing

PROCESS.

STAND-ALONE

S/W Reset

PROCESSING

STAND-ALONE MODE

USBEN

HI-Z HI-Z

voltage

SUPPLY VOLTAGES

SOURCE

PLL OFF PLL ON PLL OFF

STABLE 48 MHz

UNDE

SIGNAL

ON/OFF

FINED

NO CLOCK

PLL start -up time (automat i cally cont rolled by hardware followin g a software reset)

USB MODE

NO CLOCK

PLLmin48

RESET

IT+(LVD)

IT-(LVD)

RST

4. PLL runni ng with frequency in th e range of 48 to 24 MH z (see section 13.3.3 on page 131)

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POWER SUPPLY MANAGEMENT (Cont’d)

6.4.3 Storage Media Interface I/Os

The microcontroller is able to drive Storage Media through an interface operating at a different voltage from the rest of the circuit.

This is achieved by poweri ng the Storage Media interface I/O circuitry through a specific supply rail connected to V

DDF

pin. The V

DDF

pin can be used

either as an input or output. If the on-chip voltage regulator is off, power to the

interface I/Os should be provided ext ernally to th e V

DDF

pin. This should be the case whe n in Sta ndAlone Mode, or in USB mode when the current required to power the Storage Media is above the current capacity of the on-chip regulator.

If the on-chip voltage regulator is on, it powers the interface I/Os, and V

DDF

pin can supply t he Storage Media. This is recommended in USB Mode, when the current required to power the Storage Media is within the capacity of the on-chip regulator.

Application Example: Stand-Alone Mode

– The Storage Media interface supp ly is powered

by V

enabled by an external switch (see Fig-

ure 26) which connects V

to V

DDF

. This switch can be driven by any True Open Drain I/O pin and controlled by user software.

– The on-chip voltage regulator must be disabled

to avoid any conflict and to decrease consumption (reset the REGEN bit in the PCR register).

USB Mode

– In this case the core of the microcontroller is run-

ning from the USB bus power or the self power supply. V

and USBVDD pins are supplied with

a voltage from 4.0 to 5.5V.

– The Sto rage Media Interface can be powered

through the on-chip regulator (providing power to the I/O pins and output on pin V

DDF

) if the current requirement is within the output capacity of the on chip regulator.

– The regul ator output voltage can be pro-

grammed to 2.8V, 3.3V, 3.4V or 3.5 Volts, depending on the Storage Media specifications. (see VSET[1:0] bits in PCR register description)

– Should the current requirement for the Storage

Media be higher than the current capacity of the on chip regulator, an external regulator should be used (See Figure 27). Thus the on-chip voltage regulator must be disabled to avoid any conflict (reset the REGEN bit in the PCR register).

Caution: The user should ensure that V

does not exceed the ma ximum rating specified for the Storage Media V

DDF

max when switching STOR-

AGE switch on.

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POWER SUPPLY MANAGEMENT (Cont’d) Figure 26. Storage Media Interface Supply Swi tch (for low current Med ia)

Figure 27. S tora g e Media Interface Suppl y S w i tc h (fo r hi gh current Me di a)

DD1

STORAGE SWITCH

DD2

DDA

DDF

I/O pin

ST7

(True OD)

Note: Ground lines not shown

STORAGE MEDIA I/Os

VOLTAGE REGULATOR

I/O LOGIC

2.8V, 3.3V, 3.4V or 3.5V

(2.7V - 5.5V)

STORAGE MEDIA

This Switch is turned ON to

The on-chip Regul ator

I/F in USB mode

power Storage Media I/F in Stand-Alone Mode

supplies the Storage Media

PMOS

LEVEL TRANSLAT OR

DD1

STORAGE SWITCH

DD2

DDA

DDF

I/O pin

ST7

(True OD)

Note: Ground lines not shown

STORAGE MEDIA I/Os

VOLTAGE REGULATOR

I/O LOGIC

2.8V, 3.3V, 3.4V or 3.5V

(2.7V - 5.5V)

STORAGE MEDIA

This supply is not used

REGUL

This Switch is turned ON to power S torage Media I/F in Stand -Alone Mode

This Regulator suppli es the Storage Media I/F in USB Mode

and MUST be di sabled

PMOS

LEVEL TRANSLAT OR

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POWER SUPPLY MANAGEMENT (Cont’d)

6.4.4 Power Management Appli cation Exam ple

In the example shown in Figure 28, the V

supply

is provided by a step up. In this case the step up

must be capable of tolerating voltages up to 5.5V on its Vout pin.

Figure 28. Dual Power Supply Application Example (low current Storage Media)

MPEG

DAC

Decoder

Step Up

1.2V

I2S

VCC

USB

KEYBOARD

USBV

DTC

I2C

MP3

1.5Mbit/s Max

USB port

2M - 128MByte

FLASH

DDF

STORAGE

VPP

GND

USB

10µF

Cbus= 40pF max

LCD DISPLAY

LIGHT

Audio

AMP

TDA7474

STA013

4.7µF

50µH

USBVDD

POWER

USB

MANAGEMENT

GND

100nF

Vdd in Stand-Alon e m ode

Regulator output (2.8 - 3. 5V) in USB mode

12V for

STORAGE Switch

USBV

Switch

DEC Switch

LED

level translator

Flash prog.

REGULATOR

I/O

LOGIC

I2C

=4.0-5.5V

MEDIA

THRESH

USBEN

4.7µF

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POWER SUPPLY MANAGEMENT (Cont’d)

6.4.5 Register Description POWER CONTROL REGISTER (PCR)

Reset Value: 0000 0000 (00h)

Bit 7 = ITPF

Voltage Input Threshold Plus Flag

This bit is set by hardware when USBV

rises

over USBV

IT+

and cleared by hardware when US-

drops below USBV

IT+

0: USBV

< USBV

IT+

1:USBVDD > USBV

IT+

Bit 6 = ITMF

Voltage Input Threshold Minus Flag

This bit is set by hardware when USBV

rises

over USBV

IT-

and cleared by hardware when US-

drops below USBV

IT-

0: USBV

< USBV

IT-

1:USBVDD > USBV

IT-

Bit 5 = PL G

USB Plug/Unplug detection.

This bit is set by hardware when it detects that the USB cable has been plugged in. It is cleared by hardware when the USB c abl e is u nplugg ed. (Detection happens when USBV

rises over USB-

IT+

or when USBV

drops below USBV

IT-

). If the PLGIE bit is set, the rising edge of the PLG bit also generates an interrupt request. 0: USB cable unplugged 1: USB cable plugged in

Bit 4 = PL GIE

USB Plug/Unplug Interrupt Enable.

This bit is set and cleared by software. 0: Single supply mode: PLG interrupt disabled. 1: Dual supply mode: PLG interrupt enabled (gen-

erates an interrupt on the rising edge of PLG).

Bit 3:2 = VSET[1:0]

Voltage Regulator Output

Voltage.

These bits are set and cleared by software to select the output voltage of the on-chip voltage regulator (for the V

DDF

output).

Bit 1 = DETEN

USB Voltage Det e cto r En abl e .

This bit is set and cleared by software. It is used to power-off the USB voltage detector in Stand-alone mode. 0: The USB voltage detector is enabled. 1: The USB voltage detector disabled (ITPF, ITMF

and PLG bits are forced high)

Bit 0 = REGEN

Voltage Regulator Enable.

This bit is set and cleared by software. 0: The regulator is completely shutdown and no

current is drawn from the power supply by the voltage reference.

1: The on-chip voltage regulator is powered-on.

ITPF

ITM

PLG

PLG IEVSET1VSET0DETENREG

VSET1VSE

Voltage output of the regulator

00 3.5V 01 3.4V 1 0 3.3V 11 2.8V

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7 INTERRUPTS

7.1 INTRODUCTION

The CPU enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 3 non maskable events: RESET, TRAP, TLI

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses locat ed at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt cont roller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller.

7.2 MASKI N G AND PRO C ESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 8 ). The processing flow is shown in Figure 29.

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which c auses the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be rest ored from the stack and the program in the previous level will resume.

Table 8. Interrupt Software Priority Levels

Figure 29. Int errupt Processing Flow c hart

Interrupt software priority Level I1 I0

Level 0 (main) Low

High

10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERR UPT SW REG .

FETCH NEX T

RESET

TLI

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT STAYS PENDING

than c u rrent one

Interrupt has a higher

softwarepriority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

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INTERRUPTS (Cont’d) Servicing Pending In te rrup t s

As several interrupts can b e pen ding at the s ame time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 30 describes this decision process.

Figure 30. Priority Decision Process

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one i s not. This allows the prev ious process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest softwa re priority in the d ecision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TRAP, TLI) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 29). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC register and t he I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service rou t ine.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 29 as a TLI. Caution: TRAP can be interrupted by a TLI.

■ RESET

The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrup t vector sourc es can be servi ced if the corresponding in terrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two co nditions is false, the interrupt is la tched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the ISx bits in the MISCR1 and MISCR3 registers. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these w ill be log i cally NANDed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associ ated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupt s allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present whi le exiting HALT mode, the first one serviced can only be an interrupt with e xit from HALT mode c apability and it is selected through the same decision proc ess shown in Figure 30.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 31 and Figure 32 show two different interrupt management modes. The first is called concurrent mode and do es not allow an interrupt to be interrupted, unlike the nested mode in

Figure 32. The interrupt hardware priority is given

in this order from the l owes t to the hi ghest: M A IN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Figure 31. Concurrent Interrupt Managem ent

Figure 32. Nested Interrupt Management

MAIN

IT4

IT2

IT1

TLI

IT1

MAIN

IT0

HARDWARE PRIORITY

SOFTWARE

3 3 3 3 3 3/0

11 11 11 11 11

11 / 10

RIM

IT2

IT1

IT4

TLI

IT3

IT0

IT3

PRIORITY LEVEL

USED STACK = 10 BYTES

MAIN

IT2

TLI

MAIN

IT0

IT2

IT1

IT4

TLI

IT3

IT0

HARDWARE PRIORITY

3 2 1 3 3 3/0

11 00 01 11 11

RIM

IT1

IT4 IT4

IT1

IT2

IT3

I1 I0

11 / 10

SOFTWARE PRIORITY LEVEL

USED STACK = 20 BYTES

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INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0

Soft w a re In te r r u p t Priority

These two bits indicate the current interrupt software priority.

These two bits are set/cle ared by hardware whe n entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also s et/cleared by s oft ware wi th the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TLI, TRAP and RESET events ca n i nterr upt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, TRAP a nd TLI vectors have no s oftware priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is execu ted the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is highe r than the previous one, the interrupt x is re-ent ered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

11I1 H I0 NZC

Interrupt Software Priority Level I1 I0

Level 0 (main) Low

High

10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

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INTERRUPTS (Cont’d) Table 9. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM an d WFI instructions

change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine.

Table 10. Interrupt Mapping

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

N°

Source

Block

Description

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET Reset

N/A

Highest

Priority

Lowest Priority

yes FFFEh-FFFFh

TRAP Software Interrupt no FFFCh-FFFDh 0 ICP Flash Start Programming NMI Interrupt yes FFFAh-FFFBh 1 PLG Power Management USB Plug/Unplug PCR yes FFF8h-FFF9h 2 EI0 External Interrupt Port A N/A yes FFF6h-FFF7h 3 DTC DTC Peripheral Interrupt DTCSR no FFF4h-FFF5h 4 USB USB Peripheral Interrupt USBISTR no FFF2h-FFF3h 5 ESUSP USB End Suspend Interrupt USBISTR yes FFF0h-FFF1h 6 EI1 External Interrupt Port D N/A yes FFEEh-FFEFh 7I

C Interrupt I2CSRx no FFECh-FFEDh 8 TIM Timer interrupt TSR no FFEAh-FFEBh 9 EI2 External Interrupt Port C N/A yes FFE8h-FFE9h

10 SPI SPI interrupt SPICS R yes FFE6h-FFE7h

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INTERRUPTS (Cont’d) Table 11. Nested Interrupts Reg ister Map an d Reset Values

Address

(Hex.)

Label

76543210

002Ch

ISPR0

Reset Value

DTC EI0 PLG ISP

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

111

002Dh

ISPR1

Reset Value

C EI1 ESUSP USB

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

002Eh

ISPR2

Reset Value

Not used SPI EI2 TIM

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

002Fh

ISPR3

Reset Value 1 1 1 1

Not used Not used

I1_13

I0_13

I1_12

I0_12

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8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7.

After a RESET the normal operating mode is s elected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f

CPU

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

The user can also switch of f any unused on-chip peripherals individually by programming the MISCR2 register.

8.2 WAIT MODE

WAIT mode places the MCU in a low power c onsumption mode by stopping the CPU.

This pow e r s a v ing mo de is selected by calling the “WFI” ST7 software instruction.

All peripherals remain active. During WAIT mode, the

I1:0] bits in the CC register are forced to 0, to

enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Res et oc curs, where upon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU w ill re mai n in W AIT mo de unt il a Res et or an Interrupt occurs, causing it to wake up.

Refer to Figure 33.

Figure 33. WAIT Mode Flow Chart

WFI INSTRUCTION

RESET

INTERRUPT

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I1:0] BITS

CLEARED

OFF

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I1:0] BITS

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

DELAY

IF RESET

Note: Before servicing an interrupt, the CC register is pushed on the stack. The

I1:0] bits are

set during the interrupt routine and cleared when the CC register is popped.

(Refer to Figure 20 and

Figure 21)

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POWER SAVING MODES (Cont’d)

8.3 HALT MODE

The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals.

When entering HALT mode, the

I[1:0] bits in the

Condition Code Register are cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and i f an interrupt occurs, the CPU clock becomes active.

The MCU can e xit HAL T mode on reception of either an external interrupt on ITi, an end suspen d mode interrupt coming from USB peripheral, an SPI interrupt or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 512 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.

Figure 34. HALT Mod e Flo w C hart

EXTERNAL

INTERRUPT*

RESET

HALT INSTRUCTION

FETCH RESET VECTOR

OR SERVICE INTERRUPT

DELAY

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I1:0] BITS

SET

CPU CLOCK

OSCILLATOR PERIPH. CLOCK

I1:0] BITS

OFF

CLEARED

OFF

Note: Before servicing an interrupt, the CC register is pushed on the stack. The

I1:0] bits are

set during the interrupt routine and cleared when the CC register is popped.

(Refer to Figure 20 and

Figure 21)

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9 I/O PORTS

9.1 INTRODUCTION Impo rtant note:

Please note that the I /O port configurations of this device differ from those of the other ST7 devices.

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs

and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Im plement ation section). The generic I/O block diagram is shown in Figure 35

9.2.1 Input Modes

The input configuration is s ele cted by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies t he latch v alu e but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

External inte rru pt function

When an I/O is configured as I nput with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independen tly generat e an interrupt request. The interrupt sensitivity is independent ly programmable using the sensitivity bits in the Miscellaneous register.

Each external interrupt vecto r is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several inpu t pins are selected simultaneously as interrupt source, these are logically NANDed and inverted. For this reason if one of the interrupt pins is tied low, it masks the other ones.

In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 36).

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified.

9.2.2 Output Modes

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

The output configuration is selecte d by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to t he I/O pin through the latch. Readin g th e DR regi ster returns the digital value present on the external I/O pin. Consequently even in output mode a value written to an open drain port may differ from the value read from t he port . For example, if software writes a ‘1’ in the latch, this value will be applied to the pin, but the pin may st ay at ‘0’ depending on the state of the external circuitry. For this reason, bit manipulation even using instructions like BRES and BSET must not be used on open drain ports as they work by reading a byte, changing a bit and writing back a byte. A workaround for applications requiring bit manipulation on Open Drain I/Os is given in Secti on 9.2.4.

DR Push-pull Op en-drain

Vss

Floating

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I/O PORTS (Cont’d)

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is autom atically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is goin g to an on -chip peripheral, the I/O pin must be c onfigured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pi n has t o be configured in in-

put floating mode. CAUTION: The alternate func tion m ust n ot be ac-

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The ana log multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located c lose to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

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I/O PORTS (Cont’d) Figure 35. I/O Port General B loc k D iag ram

Table 12. I/O Port Mode Options

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

Note: The diode to V

is not implemented in the true open drain pads. A local protection between the

pad and V

is implemented to protect the device against positive stress.

Configuration Mode Pull-Up P- Buffe r

Diodes

to V

Input

Floating with/without Interrupt Off

Off

Pull-up with/withou t Interrupt On

Output

Push-pull

Off

On Open Drain (logic level) Off True Open Drain NI NI NI (see note)

DDR

DATA BUS

PAD

ALTERNATE ENABLE

ALTERNATE OUTPUT

OR SEL

DDR SEL

DR SEL

PULL-UP CONFIGURATION

P-BUFFER (see table below)

N-BUFFER

PULL-UP (see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

DIODES (see table below)

FROM OTHER BITS

EXTERNAL

SOURCE (eix)

INTERRUPT

POLARITY SELECTION

CMOS SCHMITT TRIGGER

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I/O PORTS (Cont’d) Table 13. I/O Port Configurations

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate func tion outp ut status.

2. When the I/O port is in output configuration and t he associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

Hardware Configuration

INPUT

OPEN-DRAIN OUTPUT

PUSH-PULL OUTPUT

CONFIGURATION

PAD

EXTERNAL INTERRUPT

POLARITY

DAT A BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

FROM

OTHER

PINS

SOURCE (ei

)

SELECTION

CONF IGURATION

ALTERNATE INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

ANALOG INPUT

PAD

DATA BUS

DR REGISTER ACCESS

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OP E N DRAIN I/O PORTS

PAD

DATA BUS

DR REGISTER ACCESS

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

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I/O PORTS (Cont’d)

9.2.4 Bit manipulation on Open Drain Outputs

As mentioned in Section 9.2.2, software should avoid using bit manipulation instructions on the DR register in open d rain output mode, but must always access it using byte instructions. If bit manipulation is needed, the solution is to use a copy of the DR register in RAM, change the bits (using BRES or BCLR instructions for example) and copy the whole byte into the DR register each time the value has to b e output o n a port . This way, no bit manipulation is performe d on the DR reg ister but each bit of the DR register can be controlled separately.

9.3 I/O PORT IMPL EMENTATION

The hardware implementation on each I/O port depends on the settings in t he DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one s tate to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 36. Interrupt I/O Port State Transitions

The I/O port register configurations are summarized as follows.

Port B (witho ut Opt i on Re gi s te r) PB[7:0]

Table 14. P ort Confi gu ra tio n ( wi t h Option Regi st er )

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

MODE DDR

floating input 0 push-pull output 1

Port Pin name

Input Output

OR = 0 OR = 1 OR = 0 OR = 1 High-Sink

Port A PA7:0 floating

floating

with interrupt

open drain push-pull No

Port C

PC7:4 floating

floating

with interrupt

push-pull No

PC3:0 floating

floating

with interrupt

push-pull Yes

Port D PD7:0 floating

floating

with interrupt

open drain push-pull No

Port E

PE7:6 floating open drain push-pull Yes

PE5 floating

with pull-up, if se-

lected by option

byte see Section

15.1)

open drain (with

pull-up, if select-

ed by option byte

see Section 15.1)

push-pull Yes

PE4:3 floating open drain push-pull No PE2:0 floating open drain push-pull Yes

Port F

PF6:4 floating True open drain Yes PF3:2 floating push-pull No PF1:0 floating True open drain Yes

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I/O P O R TS (Cont’d)

9. 4 Register Des cription

DATA REGISTER (DR)

Port x Data Register PxDR with x = A, B, C, D, E or F.

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register always returns the dig ital value applied to t he I/O pin (pin configured as input).

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register PxDDR with x = A, B, C, D, E or F.

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software.

0: Input mode 1: Output mode

OPTION REGISTER (OR)

Port x Option Register PxOR with x = A, C, D, or E

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.

The OR register allows to distinguish: in input mode if the interrupt capability or the basic configuration is selected, in output mode if the push-pull or open drain configuration is selected.

Each bit is set and cleared by software. Input mode: 0: Floating input 1: Floating input with interrupt (ports A, C and D).

For port E configuration, refer to Table 14.

Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull

D7 D6 D5 D4 D3 D2 D1 D0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

O7 O6 O5 O4 O3 O2 O1 O0

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I/O PORTS (Cont’d) Table 15. I/O Port Register Map and Reset Values

Address

(Hex.)

Label

76543210

Reset Value of all I/O port registers

00000000

0000h PADR

MSB LSB0001h PADDR 0002h PAOR 0003h PBDR

MSB LSB 0004h PBDDR

0005h Unused 0006h PCDR

MSB LSB0007h PCDDR 0008h PCOR 0009h PDDR

MSB LSB000Ah PDDDR 000Bh PDOR

000Ch PEDR

MSB LSB000Dh PEDDR 000Eh PEOR 000Fh PFDR

MSB LSB 0010h PFDDR

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10 MISCELLANEOUS REGISTERS

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:6 = IS1[1:0]

ei0 Interrupt sensitivity

Interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei0 interrupts (Port A):

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = MCO

Main clock out selectio n

This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

CPU

output on

I/O port)

Bits 4:3 = IS2[1:0]

ei1 Interrupt sensitivity

Interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the ei1 external interrupts (Port D):

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bits 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the CPEN bit. These two bits are set and cleared by software

Caution:

– The ST7 core is not able to read or write in the

USB data buffer if the ST7265x is configured at 6 MHz in standalone mode.

– In USB mode, with f

CPU

≤ 2 MHz, if the ST7 core accesses the USB data buffer, this may prevent the USB interface from accessing the buffer, resulting in a USB buffer overrun error. This is because an access to memory lasts one cycl e and the USB has to send/receive at a fixed baud rate.

Bit 0 = CPEN

Clock Prescaler Enable

This bit is set and cleared by software. It is used with the CP[1:0] bits to configure the internal clock frequency. 0: Default f

CPU

used (3 or 6 MHz)

1: f

CPU

determined by CP[1:0] bits

IS11 IS10 MCO IS21 IS20 CP1 CP0 CPEN

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensit ivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

Operating Mode f

CPU

CP1 CP0 CPEN

Stand-alone mode (f

OSC

= 12 MHz)

3 MHz x x 0 6 MHz* 0 0 1

1.5 MHz 1 0 1 750 KHz 0 1 1 375 KHz 1 1 1

USB mode (48 MHz PLL)

6 MHz x x 0 8 MHz 0 0 1 2 MHz 1 0 1 1 MHz 0 1 1 250 KHz 1 1 1

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MISCELL ANE OUS REG ISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2)

Reset Value: 0000 0000 (00h)

Bits 7:5 = Reserved. Bits 4:0 = P[4:0]

Power Management Bits

These bits are set and cleared by software. They can be used to sw itch the on-chip peripherals of the microcontroller ON or OFF. The registers are not changed by switching the perip heral OFF and then ON (contents are frozen while OFF). 0: Peripheral ON (running) 1: Peripheral OFF

MISCELLANEOUS REGISTER 3 (MISCR3)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = W DGHALT

Watchdog and HALT Mode

This bit is set and cleared by software. It determines if a RESET is generated when entering Halt mode while the W atchd og is active (WDGA bit = 1 in t he WDGCR register) .

In either case, the Watchdog will not reset the MCU if a HALT instruction is executed while the USB is in Suspend mode. 0: If the Watchdog is active, it will reset the MCU if

a HALT instruction is executed (unless the USB is in Suspend mode)

1: When a HALT instruction is executed, the MCU

will enter Halt mode (without generating a reset) even if the Watchdog is active.

Bits 6:4 = Reserved, forced by hardware to 0.

Bits 3:2= IS3[1:0]

ei2 Interrupt sensitivity

Interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei2 interrupts (Port C):

These 2 bits must be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 1 = PWM1

PWM1 Output Control

0: PWM1 Output alternate function disabled (I/O

pin free for general purpose I/O).

1: PWM1 Output alternate function enabled

Bit 0 = PWM0

PWM0 Output Control

0: Output alternate function disabled (I/O pin free

for general purpose I/O).

1: PWM0 Output alternate function enabled

Table 16. Miscellaneo us Register M ap and Reset Value s

0 0 0 P4P3P2P1P0

Bit Peripheral

P0 PWM P1 Timer P2 I2C P3 USB P4 DTC

WDG HALT

0 0 0 IS31 IS30 PWM1 PWM0

IS31 IS30 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

Address

(Hex.)

Label

7 6543210

MISCR1 Reset Value

IS11

IS10

MCO

IS21

IS20

CP1

CP0

CPEN

MISCR2 Reset Value

0 0

MISCR3 Reset Value

WDGHALT

0 0

IS31

IS30

PWM1

PWM0

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11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

The Watchdog t imer is used to d etect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset on ex piry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

11.1.2 Main Features

■ Programmable free-running downcounter (64

increments of 65536 CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Hardware Watchdog selectable by option byte

11.1.3 Functional Description

The counter value stored in the CR register (bits T[6:0]), is decremented every 65,536 mach ine cycles, and the length of the timeout period can b e programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becom es cleared ), it initiates a reset cycle pulling low the reset pin for typically 500ns.

The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 17):

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset.

Table 17.Watchdog Timing (f

CPU

= 8 MHz)

Figure 37. Watchdog Bl ock Diagram

CR Register

initial value

WDG timeout period

(ms)

Max FFh 524.288

Min C0h 8.192

RESET

WDGA

7-BIT DOWNCOUNTER

CPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷65536

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WATCH DOG TI MER (Cont’d)

11.1.4 Software Watchdog Option

If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. O nce activated it cannot be disabled, except by a reset.

The T6 bit can be used t o generate a s of tw are reset (the WDGA bit is set and the T6 bit is cleared).

11.1.5 Hardw are Watch do g Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.

11.1.6 Low Power Modes

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

– When using an external interrupt to wake up t he

microcontroller, reinitialize the corresponding I/O as Input before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the I bits in the

CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

11.1.7 Interrupts

None.

Mode Description

WAIT

No effect on Watchdog.

HALT

If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog is enabled. When the oscillator is sto pped, the WDG s tops counting and i s no longer able to generate a reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state). Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode

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WATCH DOG TI MER (Cont’d)

11.1.8 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA

Activation bit

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bits 6:0 = T[6:0]

7-bit timer (MSB to L SB) .

These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

Table 18. Watchdog Time r Register Map and Rese t Values

WDGAT6T5T4T3T2T1T0

Address

(Hex.)

Label

7654 3210

WDGCR Reset Value

WDGA

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11.2 DATA TRANSFER COPROCESSOR (DTC)

11.2.1 Introduction

The Data Transfer Coprocessor is a Universal Serial/Parallel Communications Interface. By means of software plug-ins provided by STM icroelect ronics, the user can configure the ST7 to handle a wide range of protocols and physical interfaces such as:

– 8 or 16-bit IDE mode Compact Flash – Multimedia Card (MMC protocol) – SmartMediaCard – Secure Digital Card

Support for different devices or future protocol standards does not require changing the microcontroller hardware, but on ly installing a different software plug-in.

Once the plug-in (up to 256 bytes) stored in the ROM or FLASH memory of the ST7 device is loaded in the DTC RAM, and that the DTC operation is

started, the I/O ports mapped to the DTC assume specific alternate functions.

Main Features

■ Full-Speed data transfer from USB to I/O p orts

without ST7 core intervention

■ Protocol-independency

■ Support for serial and parallel devices

■ Maskable Interrupts

11.2.2 Functional D escripti on

The block diagram is shown in Figure 38. The main function of the DTC is to quickly transfer data between :

■ USB and ST7 I/O ports

■ in between ST7 I/O ports

The protocol used to read or write from the I/O port is defined by the S/W plug-in in the DTC RAM.

Figure 38. DTC Block Diagram

I/O PORTS

DATA

TRANSFER

COPROCESSOR

LOAD INIT

STOP

0 0 0

RUN

DTCCR

ERR

MSB LSB

DTCPR

0 0 0 0 0 0

ERRORSTOP

DTCSR

INTERRUPT REQUEST

TO USB

DATA

BUFFER

DTC RAM

ST7 DATA/ADDR ESS BUS

INTERFACE

TRANSFER

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Data Transfer Coprocessor (Cont’d) When the USB interfac e is used, data transfer is

typically controlled by a host computer. The ST7 core can also read from and write t o the

data buffer of the DTC. Typically, the ST7 controls the application when the USB not used (autonomous mode). The buffer can potentially be accessed by any one of three requestors, the ST7, the DTC and the USB. Mast ership of the buffer is not time limited. W hile a master is accessing the buffer, other requests will not be acknowleged until the buffer is freed by the master. If several requests are pending, when the buffer is free it is granted to the source with the highest priority in the daisy-chain (fixed by hardwa re), first the ST7, secondly the USB and finally the DTC.

Note: Any access by the ST7 to the buffer requires more cycles t han either a DTC or USB access. For performance reasons, when the USB interface is exchanging data with the DTC, ST7 accesses should be avoided if possible.

11.2.3 Loading the Protocol Software

The DTC must first be initialized by loading the protocol-specific software plug-in (provided by STMicroelectronics) into the DTC RAM. To do this:

1. Stop the DTC by clearing the RUN bit in the DTCCR register

2. Remove the write protection by setting the LOAD bit in the DTCCR register

3. Load the (null-terminated) software plug-in in the DTC RAM.

4. Restore the write protection by clearing the LOAD bit in the DTCCR register

The DTC is then ready for operation.

11.2.4 Executing the Protocol Functions

To execute any of the software plug-in func tions follow the procedure below:

1. Clear the RUN bit to stop the DTC

2. Select the func tion by writing its address in the DTCPR register (refer to the separate document for address information).

3. Set the INIT bit in the DTCCR register to copy the DTCPR pointer to the DTC.

4. Clear the INIT bit to return to idle state.

5. Set the RUN bit to start the DTC.

11.2.5 Changing the DTCPR pointer on the fly

As shown in Figure 39, the pointer can be changed by writing INIT=1 while the DTC is running (RUN=1), however if the DTC is executing an internal interrupt routine, there will be a delay until interrupt handling is completed.

11.2.6 Low Pow er Mo de s

Figure 39. State Diagram of DTC Operations

Mode Description

WAIT No effect on DTC HALT DTC halted.

DTC IDLE

POINTER

DTC

RUNNING

LOAD

DTC RAM

CHANGE

POINTER

CHANGE

ON-THE-FLY

INIT=0

INIT=1

LOAD=1

LOAD=0

RUN=1

RUN=0

INIT=1

INIT=0

RUN=0

INIT=1

LOAD=0

RUN=0

INIT=0

LOAD=1

RUN=1

INIT=1

LOAD=0

RUN=1

INIT=0

LOAD=0

RUN=0

INIT=0

LOAD=0

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Data Transfer Coprocessor (Cont’d)

11.2.7 Interrupts

Note: The DTC interrupt events a re connected to

the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).

11.2.8 Register Description DTC CONTROL REGISTER (DTCCR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:5 = Reserved. Must be left at reset value.

Bit 4 = ERREN

Error Interrupt Enable

This bit is set and cleared by software. 0: Error interrupt disabled 1: Error interrupt enabled

Bit 3 = STOPEN

Stop Interrupt Enable

This bit is set and cleared by software. 0: Stop interrupt disabled 1: Stop interrupt enabled

Bit 2 = LOAD

Load Enable

This bit is set and cleared by software. It can only be set while RUN=0. 0: Write access to DTC RAM disabled 1: Write access DTC RAM enabled

Bit 1 = INIT

Initializ at ion

This bit is set and cleared by software. 0: Do not copy DTCPR to DTC 1: Copy the DTCPR pointer to DTC

Bit 0 = RUN

STAR T / STOP C o n t r o l

This bit is set an d c le ared b y software. I t c an only be set while LOAD=0. It is also cleared by hardware when STOP=1 0: Stop DTC 1: Start DTC

DTC STATUS REGISTER (DTCSR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1 = ERROR

Error Flag

This bit is set by hardware and cleared by software reading this register. 0: No Error event occurred 1: Error event occurred (DTC is running)

Bit 0 = STOP

Stop Flag

This bit is set by hardware and cleared by software reading this register. 0: No Stop event oc curr ed 1: Stop event occurred (DTC terminated execution

at the current intruction)

DTC POINTER REGISTER (DTCPR)

Write Only Reset Value: 0000 0000 (00h)

Bit 7:0 = PC[7:0]

Pointer Regi ster.

This register is written by software. It gives the address of an entry point in the protocol software that has previously been loaded in the DTC RAM.

Note: To start exec uting t he func tion, afte r writing this address, set the INIT bit.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

Error ERROR ERREN Yes No Stop STOP STOPEN Yes No

000

ERRENSTOP

LOAD INIT RUN

000000ERRORSTOP

MSB LSB

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11.2.8.1 Data Transfer Coprocessor (Cont’d) Table 19. DTC Register Map and Reset Values

Address

(Hex.)

Label

76543210

1C DTCCR

0 0

ERREN0STOPEN0LOAD

INIT

RUN

1D DTCSR

0 0

ERROR0STOP

1F DTCPR

MSB

0000000

LSB

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11.3 USB INTERFACE (USB)

11.3.1 Introduction

The USB Interface implements a full-speed function interface between the US B and t he ST7 microcontroller. It is a highly integrated circuit whi ch includes the transceiver, 3.3 voltage regulator, SIE and USB Data Buffer interface. No ex ternal components are needed apart from the external pullup on USBDP for full speed recognition by the USB host.

11.3.2 Main Features

■ USB Specification Version 2.0 Compliant

■ Supports Full-Speed USB Protocol

■ Five Endpoints (including default endpoint)

■ CRC generation/checking, NRZI encoding/

decoding and bit-stuffing

■ USB Suspend/Resume operations

■ Special Data transfer mode with USB Data

Buffer Memory (2 x 512 bytes for upload or download) to DTC

■ On-Chip 3.3V Regulator

■ On-Chip USB Transceiver

11.3.3 Functional Description

The block diagram in Figure 40, gives an overview of the USB interface hardware.

For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org.

Serial Interface Engine

The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver.

The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It al so performs frame formatting, including CRC generation and checking.

Endpoints

The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted.

Data Transfer to/from USB Data Buffer Memory

When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place to/from the USB data buffe r. In normal configuration (MOD[1:0] bits=00 in the CTLR register), at the end of the transaction, an interrupt is generated.

Interrupts

By reading the Interrupt Status register, application software can know which USB eve nt has occurred.

Figure 40. USB Block Diagram

CPU

Transceiver

3.3V Voltage Regulator

SIE

ENDPOINT

BUFFER

USB

Address,

and interrupts

USBDM

USBDP

USBVCC

48 MHz

REGISTERS

data busses

USBGND

BUFFER

USB

DATA

INTERFACE

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USB INTERFACE (Cont’d) USB Endpoint RAM Buffers

There are five bidirectional Endpoints including one control Endpoint 0. Endpoint 1 and Endpoint 2 are counted as 4 bulk o r interrupt Endpoints (two IN and two OUT).

Endpoint 0 and Endpoint 1 are both 2 x 16 bytes in size. Endpoint 2 is 2 x 64 bytes in size and can be configured to physically target different USB Data Buffer areas depending on the MOD[1:0] bits in

the CTLR register (see Fi gure 41, Figure 42 and

Figure 43).

The USB Data Buffer operates as a double buffer; while one 512-by te block is being read/written by the DTC, the USB interface reads/writes the other 512-byte block.

The management of the data transfer is performed in upload and download mode (2 x 512 byte buffers for Endpoint 2) by the USB Data Buffer Manager.

Figure 41. Endpoint 2 Normal Mode selected by (MOD[1:0] Bits = 00h)

Figure 42. Endpoint 2 Download Mode selected by MOD[1:0] Bits = 10b

Endpoint 2 Buffer OUT

Endpoint 1 Buffer IN

Endpoint 1 Buffer OUT

Endpoint 0 Buffer IN

Endpoint 0 Buffer OUT

Endpoint 2 Buffer IN

16 Bytes 16 Bytes 16 Bytes 16 Bytes

64 Bytes

1550h 155Fh

156Fh 157Fh

158Fh

15CFh

160Fh

USB DATA USB DATA

USB DATA

512-byte buffer as 64-byte slices

64-byte buffer

1650h

1A4Fh

15CFh

Endpoint 2 Buffer IN

Endpoint 2 Buffer OUT

158Fh

1550h

Endpoint 1 Buffer OUT

Endpoint 1 Buffer IN

Endpoint 0 Buffer OUT

Endpoint 0 Buffer IN

1590h

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USB INTERFACE (Cont’d) Figure 43. Endpoint 2 Upload Mode selected by MOD[1:0] Bits = 01b

USB DATA USB DATA

USB DATA

512-byte buffer as 64-byte slices

64-byte buffer

1650h

1A4Fh

15CFh

Endpoint 2 Buffer OUT

Endpoint 2 Buffer IN

158Fh

1550h

Endpoint 1 Buffer OUT

Endpoint 1 Buffer IN

Endpoint 0 Buffer OUT

Endpoint 0 Buffer IN

1590h

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USB INTERFACE (Cont’d)

11.3.4 USB Data Buffer Manager

The USB Data Buffer Mana ger performs the dat a transfer between the USB interface and the two 512 Bytes RAM areas used for Endpoint 2 in bot h Upload and Download m odes. It also c ontrols the status of Endpoint 2, by setting the endpoint as NAK when the current buffer is not yet available for either transmission (Upload) or reception (Download).

It is based on a stand-alone hardware state-machine that runs in parallel to the ST7 processin g flow . H ow ev er , a t a ny t im e , th e ST7 s oft w are ca n initialize the USB Data Buffer Manager state-machine in order to synchronize operations by writing a ‘1’ to the CLR bit in the BUFCSR register.

Dedicated buffer status flags are defined to synchronize the USB Data Buffer Manager with the Data Transfer Coprocessor (DTC). These flags are used by the software plug-ins provided by STMicroelectronics) running on the DTC.

11.3.4.1 Data Transfer Modes

In USB normal mode (MO D[1:0]=00b), t he maximum memory size of Endpoint 2 is 64 bytes, and therefore reception of 512 bytes packet s requires ST7 software intervention every 64 bytes. This means that after a CTR interrupt the hardware puts the Endpoint 2 status bits for the current direction (transmit or receive) in NAK status. The

ST7 software must then write the status bits to VALID when it is ready to t ransm it or receive new data.

On the contrary, in Upload or Download mode, the physical address of Endpoint 2 is automatically incremented every 64 bytes until a 512-byte buffer is full.

Toggling between the tw o buffers is aut omatically managed as soon as 512 b ytes h ave been transmitted to USB (Upload mode) or received from USB (Download), if the next buffer is available: Otherwise, the endpoint is set to invalid until a buffer has been released by the DTC.

11.3.4.2 Switching back to Normal Mode

The USB interface is reset by hardware in Normal mode on reception of a packet with a length below the maximum packet size. In this case, the few bytes are received into one of the two 512-byte buffers and the ST7 must process by software the data received. For this purpose, the information indicating which 512-byte buffer was last addressed is given to the ST7 by the USB Data Buffer Manager (BUFNUM bit in the BUFCSR register), and the number of received by tes is obtained by reading the USB interface registers. With these two items of information, the ST7 can determine what kind of data has been received, and what action has to be taken.

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USB INTERFACE (Cont’d) Figure 44. Overview of USB, DTC and ST7 Interconnections

1650h

1850h

1A4Fh

0 0 0 0

STAT

CLR

STAT

BUF

NUM

512-byte RAM

Buffer

512-byte RAM

Buffer

DATA

COPROCESSOR

DAT A T RANS FER

BUFFER

(1280 bytes)

USB

SIE

TRANSFER

(DTC)

ARBITRATION

USB DATA

BUFFER

BUFFER ACCESS

Parameters

USB EP0 USB EP1

USB EP2

BUFCSR Register (19h)

1550h

MANAGER

DTC I/Os (EXTERNAL DEVICES)

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USB INTERFACE (Cont’d)

11.3.5 Low Power modes

11.3.6 Interrupts

Note: The USB end of suspend interrupt event is connected to a single interrupt vector (USB ESUSP) with

the exit from halt capability (wake-up). All the other interrupt events are connected to another interrupt vector: USB interrupt (USB). They generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits (I0, I1) in CC register are reset (RIM instruction).

Mode Description

WAIT

No effect on USB. USB interrupt events cause the device to exit from WAIT mode.

HALT

USB registers are frozen. In halt mode, the USB is inactive. USB operations resume when the MCU is woken up by an interrupt with

“exit from halt capability” or by an event on the USB line in case of suspend. This event will generate an ESUSP interrupt which will wake-up from halt mode.

Interrupt Event Event Flag

Enable Con-

trol Bit

Exit From

Wait

Exit

From

Halt

Correct TRansfer CTR CTRM Yes No

Setup OVeRrun SOVR SOVRM Yes No

ERROR ERR ERRM Yes No

Suspend Mode Request SUSP SUSPM Yes No

End of SUSPend mode. ESUSP ESUSPM Yes Yes

USB RESET RESET RESETM Yes No

Start Of Frame SOF SOFM Yes No

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USB INTERFACE (Cont’d)

11.3.7 Register Description BUFFER CONTROL/STATUS REGISTER

(BUFCSR)

Read Only (except bit 0, read/write) Reset Value: 0000 0000 (00h)

Bits 7:4 = Reserved, forced by hardware to 0.

Bit 3 = B UFNUM

Current USB Buffer Number

This bit is set and cleared by hardware. When data are received by Endpo int 2 in normal mode (refer to the description of the MOD[1:0] bits in the EP2RXR register) it indicates which buffer contains the data. 0: Current buffer is Buffer 0 1: Current buffer is Buffer 1

Bits 2:1 = STATB[1:0]

Buffer Status Bits

These bits are set and cleared by hardware. When data are transmitted or received by Endpoint 2 i n upload or download mode (refer to the description of the MOD[1:0] bits in the EP2RXR register) the STATB[1:0] bits indicate the status as follows:

Bit 0 = CLR

Clear Buffer Status

This bit is written by software to clear the BUFNUM and STATB[1:0] bits (it also resets the packet counter of the Buffer Manager state machine). It can be used to re-initialize the upload/download flow (refer to t he description of t he MOD[1:0] bits in the EP2RXR register). 0: No effect 1: Clear BUFNUM and STATB[1:0] bits

INTERRUPT STATUS REGISTER (ISTR)

Read/Write Reset Value: 0000 0000 (00h)

These bits cannot be set by software. When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: The CTR bit (which is an OR of all the endpoint CTR flags) cannot be cleared directly, only by clearing the CTR flags in the Endpoint registers.

Bit 7 = CTR

Correct Transfer

. This bit is set by hardware when a correct transfer operation is performed. This bit is an OR of all CTR flags (CTR0 in the EP0R register and CTR_RX and CTR_TX in the EPnR registers). By looking in the USBSR register, the type of trans fe r can be determined from t he PID[1:0] bit s for Endpoint 0. For the other Endpoints, the Endpoint number on which the trans fer was made is identified by the EP[1:0] bits and the type of transfer by the IN/OUT bit. 0: No Correct Transfer detected 1: Correct Transfer detected

Note: A transfer where the device sent a NAK or STALL handshake i s considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 P ID is sent as expected, if there were no data overruns, bit stuffing or framing errors.

Bit 6 = Reserved, forced by hardware to 0.

Bit 5 = SOVR Setup Overrun. This bit is set by hardware when a correct Setup transfer operation is performe d whi le the software is servicing an interrupt which occurred on the same Endpoint (CTR0 bit in the EP0R register is still set when SETUP correct transfer occurs). 0: No SETUP overrun detected 1: SETUP overrun detected

When this even t occurs, the USBSR reg ister is no t updated because the only source of the SOVR event is the SETUP token reception on the Control Endpoint (EP0).

0000

BUFNUM

STATB1STAT

CLR

Meaning

STATBn Value

Upload

Mode

Buffer n not full (USB waiting to read Buffer n)

Buffer n full (USB can upload this buffer)

Download

Mode

Buffer n empty (Can be written to by USB)

Buffer n not empty (USB waiting to write to this buffer)

CTR 0 SOVR ERROR SUSP ESUSP RESET SOF

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USB INTERFACE (Cont’d) Bit 4 = E RR

Error

. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing, nonstandard

framing or buffer overrun error detected

Note: Refer to the ERR[2:0] bits in the USBSR register to determine the error type.

Bit 3 = SUSP

Suspend mode request

. This bit is set by ha rdware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB.

The suspend request check is active immediately after each USB reset event and is disabled by hardware when suspend m ode is forced (FSUS P bit in the CTLR register) until the en d of resume sequence.

Bit 2 = ESUSP

End Suspend mode

. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode.

This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected

Bit 1 = R ESET

USB reset.

This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected

Note: The DADDR, EP0R, EP1RXR, EP1TXR and EP2RXR, EP2TXR registers are reset by a USB reset.

Bit 0 = SO F

Start of frame.

This bit is set by hardware when a SOF token is received on the USB. 0: No SOF received 1: SOF received

Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load in struction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND, XOR..

INTERRUPT MASK REGISTER (IMR)

Read/Write Reset Value: 0000 0000 (00h)

These bits are mask bits for all the interrupt condition bits included in the ISTR register. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I- bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the description of the ISTR register.

CONTROL REGISTER (CTLR)

Read/Write Reset value: 0000 0110 (06h)

Bit 7 = RSM

Resume Detected

This bit shows when a resume sequence has started on the USB port, requesting the US B interface to wake-up from suspend s tate. It can be u sed to determine the cause of an ESUSP event. 0: No resume sequence detected on USB 1: Resume sequence detected on USB

Bit 6 = USB_RST

USB Reset detected

. This bit shows that a reset sequence has started on the USB. It can be used to determine the cause of an ESUSP event (Reset sequence). 0: No reset sequence detected on USB 1: Reset sequence detected on USB

Bits 5:4 Reserved, forced by hardware to 0.

Bit 3 = RESUME

Resume

. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate delay.

CTRM 0

SOVR

ERRM

SUSPMESUSPMRESET

SOFM

RSM

USB_

RST

RESU

PDWN FSUSP FRES

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USB INTERFACE (Cont’d) Bit 2 = PDW N

Power down

. This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off

Note: After turning on the voltage regulator, software should allow at leas t 3 µs for stabilisation of the power supply before using the USB interface.

Bit 1 = FSUSP

Force suspend mode

. This bit is set by software to enter Suspend mode. The ST7 should also be put in Halt mode to reduce power consumption. 0: Suspend mode inactive 1: Suspend mode active

When the hardware det ects USB act ivity, it resets this bit (it can also be reset by software).

Bit 0 = FRES

Force reset.

This b it is set b y softw are to for ce a res et of the USB inte r fa ce , just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced.

The USB interface is held in RESET state until software clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled.

DEVICE ADDRESS REGISTER (DADDR) Read/Write Reset Value: 0000 0000 (00h)

Bit 7 Reserved, forced by hardware to 0.

Bits 6:0 = ADD[6:0]

Device address, 7 bits.

Software must write into this register the address sent by the host during enumeration.

Note: This register is also reset when a USB reset is received or forced through bit FRES in the CTLR register.

USB STATUS REGISTER (USBSR) Read only Reset Value: 0000 0000 (00h)

Bits 7:6 = PID[1:0]

Token PID bits 1 & 0 for End-

point 0 Control

. USB token PIDs are encoded in four bits. PID[1:0] correspond to the m ost significant bits of the PID field of the last token PID received by Endpoint 0. Note: The le ast s ignificant PI D bits have a fixed value of 01 . When a CTR interrupt occurs on Endpoint 0 (see register ISTR) the software should read the PID[1:0] bits to retrieve the PID name of the token received. The USB specification defines PID bits as:

Bit 5 = IN/OUT

Last transaction direction for End-

point 1 or 2.

This bit is set by hardware when a CTR interrupt occurs on Endpoint 1 or Endpoint 2. 0: OUT transaction 1: IN transaction

Bits 4:3 = EP[1:0]

Endpoint number.

These bits identify the endpoint which required attention. 00 = Endpoint 0 01 = Endpoint 1 10 = Endpoint 2

0 ADD6ADD5ADD4ADD3ADD2ADD1ADD0

PID1 PID0

IN/

OUT

EP1 EP0 ERR2 ERR1 ERR0

PID1 PID0 PID Name

0 0 OUT 10 IN 1 1 SETUP

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USB INTERFACE (Cont’d) Bits 2:0 = ERR[2:0]

Error type

These bits identify the type of error which occurred:

Note: These bits are set by hardware when an error interrupt occurs and are reset automatically when the error bit (ISTR bit 4) is cleared by software.

ENDPOINT 0 REGISTER (EP0R) Read/Write Reset value: 0000 0000 (00h)

This register is used for c ontrolling Endpoint 0. Bits 6:4 and bits 2:0 a re also reset by a US B reset, e ither r ecei ve d from the USB o r fo rced throu gh the FRES bit in CTLR.

Bit 7 = CTR0

Correct Transfer

. This bit is set by hardware when a correct transfer operation is performed on Endpoint 0. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR on Endpoint 0 1: Correct transfer on Endpoint 0

Bit 6 = DTOG_TX

Data Toggle, for transmission

transfers

. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted

data packet. This bit is set by hardware on reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token.

Bits 5:4 = STAT_TX [1:0]

Status bits, for transmis-

sion transfers

. These bits contain the information about the endpoint status, as listed below:

Table 20. Transmission Status

Encoding

These bits are written b y s oftware. Hardware s ets the STAT_TX and STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted.

Bit 3 = Reserved, forced by hardware to 0.

Bit 2 = DTOG_RX

Data Toggle, for reception

transfers

. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_ RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit.

ERR2 ERR1 ERR0 Meaning

0 0 0 No error 0 0 1 Bitstuffing error 0 1 0 CRC error

011

EOP error (unexpected end of packet or SE0 not followed by J-state)

100

PID error (PID encoding error, unexpected or unknown PID)

101

Memory over / underrun (memory controller has not answered in time to a memory data request)

111

Other error (wrong packet, timeout error)

CTR0

DTOG

_TX

STAT_

TX1

STAT_

TX0

DTOG

_RX

STAT_

RX1

STAT_

RX0

STAT_TX1 STAT_TX0 Meaning

DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored.

STALL: the endpoint is stalled and all transmission requests result in a STALL handshake.

NAK: the endpoint is NAKed and all transmission requests result in a NAK handshake.

VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).

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USB INTERFACE (Cont’d) Bits 1:0 = STAT_RX [1:0]

Status b its , for rece ption

transfers

. These bits contain the information abo ut the e ndpoint status, as listed below:

Table 21. Reception Status Encoding

These bits are written by softw are. Hardware set s the STAT_RX and STAT_ TX bits to NAK when a correct transfer has occurred (CTR =1) addressed to this endpoint, so the software has the t ime to examine the received data before acknowledging a new transaction.

Notes:

If a SETUP is received while the status is other than DISABLED, it is acknowledged and the tw o directional status bits are set to NAK by hardware.

When a STALL is answered by the USB device, the two directional status bits are set to S T ALL by hardware.

ENDPOINT 1 RECEPTION REGISTER (EP1RXR)

Read/Write Reset value: 0000 0000 (00h)

This register is used for controlling Endpoint 1 reception. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register.

Bits 7:4 Reserved, forced by hardware to 0.

Bit 3 = CTR_RX

Correct Reception Transfer

. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after the corresponding interrupt has been serviced.

Bit 2 = DTOG_RX

Data Toggle, for reception

transfers

. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit.

Bits 1:0 = STAT_RX [ 1:0]

Status bits, for reception

transfer s

. These bits contain the information about the endpoint status, as listed below:

Table 22. Reception Status Encoding:

These bits are written by software, but hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction.

STAT_RX1 STAT_RX0 Meaning

DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored.

STALL: the endpoint is stalled and all reception requests result in a STALL handshake.

NAK: the endpoint is NAKed and all reception requests result in a NAK handshake.

VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).

0000

CTR_RXDTOG

_RX

STAT_

RX1

STAT_

RX0

STAT_RX1 STAT_RX0 Meaning

DISABLED: reception transfers cannot be executed.

STALL: the endpoint is stalled and all reception requests result in a STALL handshake.

NAK: the endpoint is naked and all reception requests result in a NAK handshake.

VALID: this endpoint is enabled for reception.

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USB INTERFACE (Cont’d) ENDPOINT 1 TRANSMISSION REGISTER

(EP1TXR)

Read/Write Reset value: 0000 0000 (00h)

This register is used for controlling Endpoint 1 transmission. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register.

Bit 3 = CTR_TX

Correct Transmission Transf e r

. This bit is set by hardware when a correct transfer operation is performed in transmission. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR in transmission on Endpoint 1 1: Correct transfer in transmission on Endpoint 1

Bit 2 = DTOG_TX

Data Toggle, for transmission

transfers

. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX toggles only whe n the transmitter has received the ACK signal from the USB host. DTOG_TX and DTOG_RX are normally upd ated by hardware, at the receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token.

Bits 1:0 = STAT_TX [1:0]

Status bits, for transmis-

sion transfers

. These bits contain the information abo ut the e ndpoint status, which is listed below

Table 23. Transmission S tatus Enco di ng

These bits are written by software, but hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint. This allows software to prepare the next set of data to be transmitted.

ENDPOINT 2 RECEPTION REGISTER (EP2RXR)

Read/Write Reset value: 0000 0000 (00h)

This register is u sed for controlling endpoint 2 reception. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register.

Bits 7:6 = MOD[1:0]

Endpoint 2 mode

. These bits are set and cleared by software. They select the Endpoint 2 mode (See Figure 42 and

Figure 43).

Notes:

1. Before selecting Download mode, software must write the maximum packet size value (for instance 64) in the CNT2RXR register and write the STAT_RX bits in the EP2RXR register to VALID.

2. Before selecting Upload mode, software must write the maximum packet size value (for instance

64) in the CNT2TXR register and write the STAT_TX bits in the EP2TXR register to NAK.

0000

CTR_TXDTOG

_TX

STAT_

TX1

STAT_

TX0

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission transfers cannot be executed.

STALL: the endpoint is stalled and all transmission requests result in a STALL handshake.

NAK: the endpoint is naked and all transmission requests result in a NAK handshake.

VALID: this endpoint is enabled for transmission.

MOD1 MOD0 0 0

CTR_RXDTOG

_RX

STAT_

RX1

STAT_

RX0

MOD1 MOD0 Mode

Normal mode: Endpoint 2 is managed by user software

Upload mode to USB data buffer: Bulk mode IN under hardware control from DTC

Download mode from USB data buffer: Bulk mode OUT under hardware control to DTC

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USB INTERFACE (Cont’d) Download Mode

IN transactions are managed the same way as in normal mode (by software with the help of CTR interrupt) but OUT transactions are managed by hardware. This means that no CTR interrupt is generated at the end of an OUT transact ion and the STAT_RX bits are set to valid by hardware when the buffer is ready to receive new data. This allows the 512-byte buffer to be written without software intervention.

If the USB interface receives a packet which has a length lower than the maximum pack et size (written in the CNT2RXR register, see Note below), t he USB interface switches back to normal mode an d generates a CTR interrupt an d the STAT _RX bits of the EP2R register are set to NAK by hardware as in normal mode.

Upload Mode

OUT transactions are m anaged in the same way as normal mode and IN transactions are managed by hardware in the same way as OUT transactions in download mode.

Bits 5:4 Reserved, forced by hardware to 0.

Bit 3 = C TR_RX

Reception Correct Transfer

. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after that the corresponding interrupt has been serviced.

Bit 2 = DTOG_RX

Data Toggle, for reception

transfers

. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. USB INTERFACE ( C ont’d)

The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit.

Bits 1:0 = STAT_RX [1:0]

Status b its , for rece ption

transfers

. These bits contain the information abo ut the e ndpoint status, which is listed below:

Table 24. Reception Status Encoding

Note: These bits are write protected in download mode (if MOD[1:0] =10b in the EP2RXR register)

ENDPOINT 2 TRANSMISSION REGISTER (EP2TXR)

Read/Write Reset value: 0000 0000 (00h)

This register is used for controlling Endpoint 2 transmission. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register.

Bit 3 = CTR_TX

Transmission Transfer Correct

. This bit is set by hardware when a correct transfer operation is performed in transmission. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR in transmission on Endpoint 2 1: Correct transfer in transmission on Endpoint 2

STAT_RX1 STAT_RX0 Meaning

DISABLED: reception transfers cannot be executed.

STALL: the endpoint is stalled and all reception requests result in a STALL handshake.

NAK: the endpoint is naked and all reception requests result in a NAK handshake.

VALID: this endpoint is enabled for reception.

0000

CTR_TXDTOG

_TX

STAT_

TX1

STAT_

TX0

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USB INTERFACE (Cont’d) Bit 2= DTOG_TX

Data Toggle, for transmission

transfers

. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX and DTOG_RX are normally upd ated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token.

Bits 1:0 = STAT_TX [1:0]

Status bits, for transmis-

sion transfers

. These bits contain the information abo ut the e ndpoint status, which is listed below

Table 25. Transmission S tatus Enco di ng

These bits are written by software, but hardware sets the STAT_TX bits to NAK when a correct transfer (CTR=1) addressed to this endpo int has occurred. This allows software to prepare the next set of data to be transmitted.

Note: These bits are write protected in upload mode (MOD[1:0] =01b in the EP2RXR register)

RECEPTION COUNTER REGISTER (CNT0RXR, CNT1RXR)

Read/Write Reset Value: 0000 0000 (00h)

This register contains the al located buff er size for endpoint 0 or 1

reception, setting the maximum number of bytes the related endpo int can receive with the next OUT (or SETUP for Endpoint 0) transaction. At the end of a reception, the value of this register is the max s ize decremented by the number of bytes received (to determine the

number of byt es received, the software m ust subtract the content of th is register from the allocated buffer size).

RECEPTION COUNTER REGISTER (CNT2RXR) Read/Write Reset Value: 0000 0000 (00h)

This register contains the allocated b uffer size for endpoint 2

reception, setting the maximum number of bytes the related end point can receive with the next OUT transact ion. At the end of a reception, the value of this register is the maximum size decremented by the number of bytes received (to determine the number of bytes received, the software must subtract the content of this register from the allocated buffer size).

TRANSMISSION COUNTER REGISTER (CNT0TXR, CNT1TXR)

Read/Write Reset Value 0000 0000 (00h)

This register co ntains t he number of bytes to be transmitted by Endpoint 0 or 1 at the next IN token addressed to it.

TRANSMISSION COUNTER REGISTER (CNT2TXR)

Read/Write Reset Value 0000 0000 (00h)

This register co ntains t he number of bytes to be transmitted by Endpoint 2 at the next IN tok en addressed to it.

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission transfers cannot be executed.

STALL: the endpoint is stalled and all transmission requests result in a STALL handshake.

NAK: the endpoint is naked and all transmission requests result in a NAK handshake.

VALID: this endpoint is enabled for transmission.

0 0 0 CNT4 CNT3 CNT2 CNT1 CNT0

0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0

0 0 0 CNT4 CNT3 CNT2 CNT1 CNT0

0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

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Table 26. USB Register Map and Reset values

Address

(Hex.)

Name

76543210

BUFCSR Reset Va l ue

0 0

BUFNUM0BUF1ST

BUF0ST0RESETST

USBISTR Reset Va l ue

CTR

0 0

SOVR

ERR

SUSP

ESUSP

RESET

SOF

USBIMR Reset Va l ue

CTRM

0 0

SOVRM

ERRM

SUSPM0ESUSPM0RESETM

SOFM

USBCTLR Reset Va l ue

RSM0USB_RST

RESUME0PDWN

FSUSP

FRES

DADDR Reset Va l ue

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

USBSR Reset Va l ue

PID1

PID0

IN /OUT

EP1

EP0

ERR2

ERR1

ERR0

EP0R Reset Va l ue

CTR00DTOG_TX0STAT_TX10STAT_TX0

0 0

DTOG_RX0STAT_RX10STAT_RX0

CNT0RX R Reset Va l ue

0 0

CNT4

CNT3

CNT2

CNT1

CNT0

CNT0TXR Reset Va l ue

0 0

CNT4

CNT3

CNT2

CNT1

CNT0

EP1RXR Reset Va l ue

00 0 0

CTR_RX0DTOG_RX0STAT_RX10STAT_RX0

CNT1RX R Reset Va l ue

0 0

CNT4

CNT3

CNT2

CNT1

CNT0

EP1TXR Reset Va l ue

00 0 0

CTR_TX0DTOG_TX0STAT_TX10STAT_TX0

CNT1TXR Reset Va l ue

0 0

CNT4

CNT3

CNT2

CNT1

CNT0

EP2RXR Reset Va l ue

MOD1

MOD0

CTR_RX0DTOG_RX0STAT_RX10STAT_RX0

CNT2RX R Reset Va l ue

0 0

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

EP2TXR Reset Va l ue

00 0 0

CTR_TX0DTOG_TX0STAT_TX10STAT_TX0

CNT2TXR Reset Va l ue

0 0

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

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11.4 16-BIT TIMER

11.4.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

11.4.2 Main Features

■ Programmable prescaler: f

CPU

divided by 2, 4 or 8.

■ Overflow status flag and maskable interrupt

■ Output compare functions with

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ 2 alternate functions on I/O ports (OCMP1,

OCMP2)

The Block Diagram is shown in Figure 45.

11.4.3 Functional Description

11.4.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nifican t b yte (MS By te ) .

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Count er H igh Re gister ( ACHR) is t he

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byt e (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register reset s the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer).

The timer clock depends on th e clock control bits of the CR2 register, as illustrated in Table 27 Clock

Control Bits. The value i n the counter register re-

peats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

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16-B IT TIMER (Cont’d) Figure 45. Timer Block Diagram

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE

OVERFLOW

DETECT CIRCUIT

1/2 1/4

1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1

OCMP1

CPU

TIMER INTERRUPT

00 000OCF2OCF1 TOF

0OC1E

0CC0CC1

OC2E

0FOLV20 OLVL10OLVL2FOLV1OCIETOIE

LATCH2

OCMP2

8 low

8 high

16 16

(Control Register 1) CR1

(Control Register 2) CR2

(Status Register) SR

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT

OUTPUT COMPARE REGISTER

CC[1:0]

COUNTER

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16-B IT TIMER (Cont’d) 16-bit read sequence: (from either the Counter

The user must read the MS Byte first, then the LS Byte value is buffered automatically.

This buffered val ue remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the c ount value at the time of the read.

Whatever the timer mode used an overflow occurs when the counter rolls over from FFFFh to 0000h then :

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bits of the CC register is cleared.

If one of these co nditions i s fa lse, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

is buffered

Read

At t0

Read

Returns the buffered

LS Byte value at t0

At t0 +∆t

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

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16-B IT TIMER (Cont’d) Figure 46. Counter Timing Diagram, internal clock divided by 2

Figure 47. Counter Timing Diagram, internal clock divided by 4

Figure 48. Counter Timing Diagram, internal clock divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

CPU CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

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16-B IT TIMER (Cont’d)

11.4.3.2 Output Compare

In this section, the index,

, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer .

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is fou nd bet ween the Output Com pare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCIE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be c ompared to the counter register each timer clock cycle.

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

R value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– S et the OCiE bit if an output is needed then the

OCMP

pin is dedica ted to the output c ompare

signal.

– Select the timer clock (CC[1:0]) (see Table 27

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVL

bit to applied to the OCMPi pins

after the match occurs. – S et the OCIE b it to generate an in terrupt if it is

needed. When a match is found between OCRi register

and CR register: – OCF

bit is set.

– The OCMP

pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bits are cleared in the CC register (CC).

The OC

R register value required for a specific timing application can be calculated using the following f ormula:

Where:

∆t = Output compare period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 27

Clock Control Bits)

If the timer clock is an external clock, the formula is:

Where:

∆t = Output compare period (in seconds)

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e. clearing the OCF

bit) is done by:

1. Reading the SR register while the OCF

bit is

set.

2. An access (read or write) to the OC

LR register.

The following procedure is recommended to prevent the OCF

bit from being set between the time

it is read and the write to the OC

R register:

– Write to the OC

HR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

bit, which may be already set).

– Write to the OC

LR register (enables the output

compare function and clears the OCF

bit).

MS Byte LS Byte

ROC

HR OCiLR

∆ OC

R =

∆t * f

CPU

PRESC

∆ OC

R = ∆t

* fEXT

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16-B IT TIMER (Cont’d) Notes:

1. After a process or write cycle to t he O C

iHR

iLR

2. If the OC

E bit is not set, the OCMPi pin is a

general I/O port and the OLVL

bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCFi and

OCMP

are set while the counter value equals

the OC

R register value (see Figure 50 on

page 86).

When the timer clock is f

CPU

/4, f

CPU

/8 or in

external clock mode , OCF

and OCMPi are set

while the counter value equals the OC

R regis-

ter value plus 1 (see F igure on page 86).

4. The output compare functions can be used both for generating external events on the OCMP

pins even if the input capture mode is also used.

5. The value in the 16-bit OC

R register and the

OLV

bit should be changed after each successful comparison in order to control an output waveform or establish a new timeout period.

Forced Compare Output capab ility

When the FOLV

bit is set by software, the OLVL

bit is copied to the OCMPi pin. The OLVi bit has to be toggled in o rder t o t oggle the OCMP

pin when

it is enabled (OC

E bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

Figure 49. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2

FOLV1

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16-B IT TIMER (Cont’d) Figure 50. Output Compare Timing Diagram, f

TIMER

CPU

Figure 51. Output Compare Timing Diagram, f

TIMER

CPU

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

(OCRi)

OUTPUT COMPARE FLAG

(OCFi)

OCMP

PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

(OCRi)

COMPARE REGISTER

LATCH

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

OCMPi PIN (OLVLi=1)

OUTPUT COMPARE FLAG

(OCFi)

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16-B IT TIMER (Cont’d)

11.4.4 Low Power Modes

11.4.5 Interrupts

Note: The 16-bit Timer interrupt events are co nnecte d to the sa me interru pt vector (see In terrupts chap-

ter). These events generate an interrup t if the corresponding Enable Control Bit is set and the interrupt mask bits in the CC register are reset (RIM instruction).

Mode Description

WAIT

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

Output Compare 1 event OCF1

OCIE

Yes No

Output Compare 2 event OCF2 Yes No Timer Overflow event TOF TOIE Yes No

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16-B IT TIMER (Cont’d)

11.4.6 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the c ounter and the a lternate counter.

CONTROL REGISTER 1 (TCR1)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = Reserved, forced by hardware to 0.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE

Timer Overflow Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the T OF

bit of the SR register is set.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the O C2E bit is set and even if there is no successful compari so n.

Bit 3 = FOLV1

Forced Output Compare 1.

This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bi t is set and e ven if there i s no successful comparison.

Bit 2 = OLVL2

Output Level 2.

This bit is copied to the OCMP2 pin wh enever a successful co mpa ri so n o ccurs with the OC2R register and OCxE is set in the CR2 register.

Bit 1 = Reserved, forced by hardware to 0.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bi t is copied t o t he O CMP 1 pin whenever a successful comparison occurs with the OC1R register and the O C1E bit is set in the CR2 register.

70 0 OCIE TOIE FOLV2 FOLV1 OLVL2 0 OLVL1

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16-B IT TIMER (Cont’d) CONTROL REGISTER 2 (TCR2)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternat e function di sabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternat e function di sabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bits 5:4 = Reserved, forced by hardware to 0.

Bits 3:2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 27. Clock Control Bits

Bits 1:0 = Reserved, forced by hardware to 0.

STATUS REGIST ER (TSR )

Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.

Bit 7 = Reserved, forced by hardware to 0.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R reg ister. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = Reserved, forced by hardware to 0.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC2R reg ister. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Bits 2:0 = Reserved, forced by hardware to 0.

OC1E O C2E 0 0 CC1 CC0 0 0

Timer Clock CC1 CC0

CPU

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

Reserved 1 1

70 0 OCF1 TOF 0 OCF2 0 0 0

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16-B IT TIMER (Cont’d) OUTPUT COMPARE 1 HIGH REGISTER

(OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit regi ster that cont ains the high part of the value to be compared to the CHR register.

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

OUTPUT COMPARE 2 HIGH REGISTER (OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit regi ster that cont ains the high part of the value to be compared to the CHR register.

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

COUNTER HIGH REGISTER (CHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister that contains t he hi gh pa rt of the counter value.

COUNTER LOW REGISTER (CLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister that contains t he hi gh pa rt of the counter value.

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does no t clear the TOF bit in SR register.

MSB LSB

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16-B IT TIMER (Cont’d) Table 28. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Name

76543210

TCR1 Reset Value

0 0

OCIE

TOIE

FOLV20FOLV10OLVL2

0 0

OLVL1

TCR2 Reset Value

OC1E

OC2E

0 0

CC1

CC0

0 0

TSR Reset Value

0 0

OCF1

TOF

0 0

OCF2

0 0

CHR Reset Value

MSB

1111111

LSB

CLR Reset Value

MSB

1111110

LSB

ACHR Reset Value

MSB

1111111

LSB

ACLR Reset Value

MSB

1111110

LSB

OC1HR Reset Value

MSB

1000000

LSB

OC1LR Reset Value

MSB

0000000

LSB

OC2HR Reset Value

MSB

1000000

LSB

OC2LR Reset Value

MSB

0000000

LSB

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11.5 PWM/BRM GENERATOR (DAC)

11.5.1 Introduction

This PWM/BRM periphera l includes a 6-bit Pulse Width Modulator (PWM) and a 4-bit Binary Rate Multiplier (BRM) Generator. It allows the digital to analog conversion (DAC) when used with external filtering.

Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map.

11.5.2 Main Features

■ Fixed frequency: f

CPU

/64

■ Resolution: T

CPU

■ Steps of V

/210 (5mV if VDD=5V)

11.5.3 Functional Description

The 10 bits of the 10-bit PWM/BRM are distributed as 6 PWM bits and 4 BRM bits. The generator consists of a 10-bit counter (common for all channels), a comparator and the PWM/BRM generation logic.

PWM Genera t ion

The counter increments continuously, clocked at internal CPU clock. Whenever the 6 least significant bits of the counter (defined as the PWM counter) overflow, the output level for all active channel s is set.

The state of the PWM counter is continuously compared to the PWM binary weight for each channel, as defined in the relevant P WM register, and when a match occurs the output level for that channel is reset.

This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. T his provides an analog voltage proportional to the average charge passed to the external capacitor. Thus for a higher mark/space ratio (high time much greater than low time) the av erage output voltage is higher. The external components of the RC network should be selecte d for the filtering l evel required for control of the system variable.

Each output may individually have its polarity inverted by software, and can also be used as a logical output.

Figure 52. PWM Generation

COUNTER

COMPARE

VALUE

OVERFLOWOVERFLOW OVERFLOW

000

PWM OUTPUT

CPU

x 64

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PWM/BRM GENERATOR (Cont’d) PWM/BRM Outputs

The PWM/BRM outputs are assigned to dedicated pins. The PWM/BRM outputs can be connected to an RC filter (see Figure 53 for an example). The RC filter time must be higher than T

CPU

x64.

Figure 53. Typical PWM Output Filter

Table 29. 6-Bit PWM Ripple After Filtering

With R C fi lter ( R=1K Ω ), f

CPU

= 8 MHz

= 5V PWM Duty Cycle 50% R=R

ext

Note: after a reset these pins are tied low by default and are not in a high impedance state.

Figure 54. PWM Simplified Voltage Outpu t After Filtering

ext

OUTPUT VOLTAGE

STAGE

OUTPUT

ext

Cext (µF) V RIPPLE (mV)

0.128 78

1.28 7.8

12.8 0.78

ripple

(mV)

OUTAVG

"CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"

OUTAVG

(mV)

ripple

"CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"

PWMOUT

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

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PWM/BRM GENERATOR (Cont’d) BRM Generation

The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of “fine-tuning” the PWM Duty cycle (witho ut modify ing t he b ase duty cycle ), thus, with the external filtering, providing additional fine voltage steps.

The incremental pulses (with duration of T

CPU

) are added to the beginning of the original PWM pulse. The PWM intervals which are added to are specified in the 4-bit BRM register and are encoded as shown in the following table. The BRM values shown may be combined together to provide a summation of the incremental pulse intervals specified.

The pulse increment corresponds to the PWM resolution.

For example,if – Data 18h is written to the PWM register – Data 06h (00000110b) is written to the BRM reg-

ister – with a 8MHz internal clock (125ns resolution) Then 3.0 µs-long pulse will be output at 8 µs inter-

vals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 µs.

Note. If 00h is written to both PWM and BR M registers, the generator output will remain at “0”. Conversely, if both registers hold data 3Fh and 0Fh, respectively, th e o ut p ut w ill r emain a t “1” fo r all intervals 1 to 15, but it wi l l return t o zero at interval 0 for an amount of time corres ponding to the PWM resolution (T

CPU

An output can be set to a cont inuous “1” level by clearing the PWM and BRM values and setting POL = “1” (inverted polarity) in the PWM register. This allows a PWM/BRM channel to be used as an additional I/O pin if the DAC function is not required.

Table 30. Bit BRM Added Pulse Intervals (Interval #0 not selected).

Figure 55. BRM pulse addition (PWM > 0)

BRM 4 - Bit Data Incremental Pulse Intervals

0000 none 0001 i = 8 0010 i = 4,12 0100 i = 2,6,10,14 1000 i = 1,3,5,7,9,11,13,15

CPU

x 64 T

CPU

x 64 T

CPU

x 64

CPU

x 64 increment

m = 1 m = 0 m = 2

CPU

x 64

m = 15

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PWM/BRM GENERATOR (Cont’d) Figure 56. Simplified Filtered Voltage Output Schematic with BRM Added

Figure 57. Graphical Representation of 4-Bit BRM Added Pulse Positions

VDD

PWMOUT

VDD

OUTPUT

VOLTAGE

BRM = 1 BRM = 0

CPU

BRM

EXTENDED PULSE

0100 bit2=1

1514131211109876543210

PWM Pulse Number (0-15)

BRM VALUE

0001 bit0=1 0010 bit1=1

1000 bit3=1

Examples

0110 1111

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PWM/BRM GENERATOR (Cont’d) Figure 58. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)

11.5.4 Register Description

On a channel basis, the 10 bits are separated into two data registers:

Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map.

PULSE BINARY WEIGHT REGISTERS (PWMi)

Read / Write Reset Value 1000 0000 (80h)

Bit 7 = Reserved (Forced by hardware to “1”)

Bit 6 = PO L

Polarity Bit for channel i.

0: The channel i outputs a “1” level during the bina-

ry pulse and a “0” level after.

1: The channel

outputs a “0” level during the bina-

ry pulse and a “1” level after.

Bit 5:0 = P[5:0]

PWM Pulse Binary Weight for

channel i.

This register contains the binary value of the pulse.

BRM REGISTERS

Read / Write Reset Value: 0000 0000 (00h)

These registers define the intervals where an incremental pulse is added to the beginning of the original PWM pulse. Two BRM channel values share the same register.

Bit 7:4 = B[7:4]

BRM Bits (channel i+1).

Bit 3:0 = B[3:0]

BRM Bits (channel i)

Note: From the programmer's point of view, the PWM and BRM registers can be regarded as being combined to give one data value.

For example :

Effective (with external RC filtering) DAC value

1 POL P5 P4 P3 P2 P1 P0

B7 B6 B5 B4 B3 B2 B1 B0

1POLPPPPPP+BBBB

1POLPPPPPPBBBB

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PULSE WIDTH MODULATION (Cont’d) Table 31. PWM Register Map and Reset Values

Address

(Hex.)

Name

76543210

PWM0

Reset Value

1 1

POL

BRM10

Reset Value

PWM1

Reset Value

1 1

POL

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11.6 SERI AL PER IPHERAL INTERFACE (SPI )

11.6.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may cons ist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system.

11.6.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

■ Six master mode frequencies (f

CPU

/2 max.)

■ f

CPU

/2 max. slave mode frequency

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write co llision, Master Mode Fault and Overrun

flags

11.6.3 General Description

Figure 59 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connec ted to ext ernal devices th rough 3 pins:

– MISO: Master In / Slave Out data – M OSI: Master Out / Slave In data – SCK: Serial Clock out by SPI mas ters and in-

put by SPI slaves

–SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS

inputs can be driven by stand-

ard I/O ports on the master MCU.

Figure 59. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE SPE

MSTR

CPHA SPR0SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL MODF 0OVR SSISSMSOD

SOD

bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.6.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 60.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re-

sponds by sending da ta to the master device via the MISO pin. This implies full duplex communication with both data out an d data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communicati on is possib le).

Four possible data/clock timin g relationships may be chosen (see Figure 63) b ut master and slave must be programmed with the same timing mode.

Figure 60. Single Master/ Single Slave Application

8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

8-BIT SHIFT REGISTE R

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit LSBit MSBit LSBit

Not used if SS is managed by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.6.3.2 Slave Select Management

As an alternative to using the SS

pin to control the Slave Select signal, the appli cation c an choose to manage the Slave Select signal by softwa re. This is configured by the SSM bit in the S P ICSR register (see Figure 62)

In software management, the external SS

pin is free for other application uses and t he i nternal S S signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Fi gure 61):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire transmission. T his im plies t hat in s in gle s lave applications the SS

pin either can be t ied to

, or made free for standard I/O by manag-

ing the S S

function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.6.5.3).

Figure 61. Generic SS

Timing Dia gram

Figure 62. Hardware/Software Slave Select Management

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2

Byte 3

SS internal

SSM bit

SSI bit

external pin

Datasheet ST72F652R4T1, ST72F652, ST72F651R6T1, ST72F651AR6T1, ST72F651 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual