Datasheet ST72F324K6T6, ST72F324K6, ST72F324K2, ST72F324J6T6, ST72F324J6 Datasheet (SGS Thomson Microelectronics)

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Rev. 1.9

August 2003 1/161

ST72324

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC ,

4 TIMERS, SPI, SCI INTERFACE

■ Memories

– 8 to 32K dual voltage High Density Flash (HD-

Flash) or ROM with read-out protection capability. In-Application Programming and In-

Circuit Programming for HDFlash devices – 384 to 1K bytes RAM – HDFlash endurance: 100 cycles, data reten-

tion: 20 years at 55°C

■ Clock , Res et And Supply Manag e m ent

– Enhanced low voltage supervisor (LVD) for

main supply with 3 programmable reset

thresholds and auxiliary voltage detector

(AVD) with interrupt capability – Clock sources: crystal/ceramic res onator os-

cillators , internal RC osci llator, clock secu rity

system and bypass for external clock – PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 9/6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines – 22/17 alternate function lines – 12/10 high sink outputs

■ 4 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capab ilities – Configurable watchdog timer – 16-bit Timer A w ith: 1 input capt ure, 1 output

compare, external clock input, PWM and

pulse generator modes – 16-bit Timer B with: 2 input captures, 2 output

compares, PWM and pulse generator modes

■ 2 Communication Interfaces

– SPI synchronous serial interface – SCI asynchronous serial interface (LIN com-

patible)

■ 1 Analog Peripheral

– 10-bit ADC with up to 12 input pins

■ Instruction Set

– 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– Full hardware/software development package – In-Circuit Testing capability

Device Summary

TQFP44

10 x 10

SDIP42 600 mil

SDIP32 400 mil

TQFP32

7 x 7

Features ST72324(J/K)6 ST72324(J/K)4 ST72324(J/K)2

Program memory - bytes 32K 16K 8K RAM (stack) - byte s 1024 (256) 512 (256) 384 (256) Operat i ng V ol tage 3.8V to 5.5V (l ow volta ge Flash version planned with 3.0 to 3.6V range) Temp. Range (ROM) up to -40°C to +125°C Temp. Range (Fla sh) up to -40 °C to +125°C -40°C t o +85 °C Packages SDIP42 ( JxB), TQF P 44 10x10 (J xT),SDI P 32 (K xB), TQ FP32 7x7 (Kx T )

Table of Cont ents

161

2/161

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 As ynchronous External RES ET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.5 Inte rnal Watchdog RE SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.2 Aux iliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 38

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.1 I nput Mode s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 56

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.1 Minimum and Maximum v alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.2 General Operating Conditions for low voltage Flash devices (planned) . . . . . . . . 116

12.3.3 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 117

12.3.4 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.4.1 RUN and SLOW Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.4.2 WAIT and SLOW WAIT Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table of Cont ents

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12.4.3 RUN and SLOW Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.5.3 Crystal and Ceramic Resonat or Os cillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 149

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 151

14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table of Cont ents

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15.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.3 Safe Connection of OSC1/OSC2 P ins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.5 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.2.6 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.3 FLASH REV “X” AND ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.1 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.3 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.4 LVD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.4 ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.4.1 AVD not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.4.2 Internal RC oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section “IMPORTANT NOTES” on page 157

ST72324

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1 INTRODUCTION

The ST72324K and ST 72324J devices are members of the ST7 microcontroller family. They can be grouped as follows:

– The 32-pin ST72324K devices are designed for

mid-range applications

– The 42/44-pin ST723 24J devices target the

same range of applications requiring more than 24 I/O ports.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM program memory.

Under software control, all devices c an be p laced in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

Figure 1. Device Block Diagram

8-BI T CO RE

ALU

ADDRESS AND DATA BUS

OSC1

CONTROL

PROGRAM

(8K - 60K Bytes)

RESET

PORT F

PF7:6,4, 2: 0

TIM E R A

BEEP

PORT A

RAM

(384 - 2048 Bytes)

PORT C

10-BIT ADC

AREF

SSA

PORT B

PB4:0

PORT E

PE1:0 (2 bits)

SCI

TIMER B

PA7:3 (5 bits on J devices)

PORT D

PD5:0

SPI

PC7:0

(8 bits)

WATCHDOG

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on J devices) (3 bits on K devices)

(6 bits on J devices) (2 bits on K devices)

(6 bits on J dev i ces) (5 bits on K devices)

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2 PIN DESCRIPTION

Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

DD_0

SS_0

AIN5 / PD5

AREF

SSA

44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

ei2

ei3

ei0

ei1

PB3

(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4

RDI / PE1

PB0

PB1

PB2

PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12

SS_1

DD_1

PA3 (HS) PC7 / SS

/ AIN15

RESET

/ ICCSEL

PA7 (HS)

PA6 (HS)

PA5 (HS)

PA4 (HS)

PE0 / TDO

OSC1

OSC2

38 37 36 35 34 33 32 31 30 29 28 27

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(HS) PB4

AIN0 / PD0

AIN12 / OCMP 2_B / PC0

EXTCLK_A / (HS) PF7

ICAP1_A / (HS) PF6

AIN10 / OCMP1_A / PF4

(HS) PF2

BEEP / (HS) PF1

MCO / AIN8 / PF0

AIN5 / PD5

AIN4 / PD4

AIN3 / PD3

AIN2 / PD2

AIN1 / PD1

SSA

AREF

PB3 PB2

PA4 (HS)

PA5 (HS)

PA6 (HS)

PA7 (HS)

/ ICC SEL

RESET

VSS_2

PE0 / TDO

PE1 / RDI

PB0

PB1

OSC1 OSC2

ei3

ei0

ei2

ei1

17 18 19

AIN14 / MOSI / PC5

ICCDATA / MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B/ (HS) PC2

AIN13 / OCMP1_B / PC1

26 25 24 23 22

PC6 / SCK / ICCCLK

PC7 / SS

/ AIN15

PA3 (HS)

DD_1

SS_1

eix associated external interrupt vector

(HS) 20mA high sink capability

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PIN DESCRIPTION (Cont’d) Figure 3. 32-Pin SDIP Package Pinout

Figure 4. 32-Pin TQFP 7x7 Package Pinout

28 27 26 25 24 23 22 21 20 19 18 17

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(HS) PB4

AIN0 / PD0

AIN14 / MOSI / PC5

ICCDATA/ MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B / (HS) PC2

AIN13 / OCMP1_B / PC1

AIN12 / OCMP2_B / PC0

EXTCLK_A / (HS) PF7

BEEP / (HS) PF1

MCO / AIN8 / PF0

SSA

AREF

AIN1 / PD1

ICAP1_A / (HS) PF6

OCMP1_ A / AIN10 / PF4

PB3

PB0

PC6 / SCK / ICCCLK

PC7 / SS

/ AIN15

PA3 (HS)

PA4 (HS)

PA6 (HS)

PA7 (HS)

/ ICCSEL

OSC2

OSC1

PE0 / TDO

PE1 / RDI

RESET

ei0

ei3

ei2

ei1

eix associated external interrupt vector

(HS) 20mA high sink capability

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

ICCCLK / SCK / PC6

AIN15 / SS

/ PC7

(HS) PA3

AIN13 / OC M P1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10111213141516

1 2 3 4 5 6 7 8

ei1

ei3

ei0

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AREF

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

/ ICCSEL PA7 (HS) PA6 (HS) PA4 (HS)

OSC1 OSC2 V

RESET

PB0

PE1 / RDI

PE0 / TDO

PD1 / AIN1

PD0 / AIN0

PB4 (HS)

PB3

ei2

eix associated external interrupt vector

(HS) 20mA high sink capability

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PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.

Legend / Abbreviations for Table 1 :

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

/0.7V

CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

, ana = analog

– Output: OD = open drain

, PP = push-pull Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports. The RESET con fi g ur at i on of each pin i s sh o wn in bo ld. This config u ra tion is valid as long as the devi ce is

in reset state.

Table 1. Device Pin Description

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate Function

TQFP44

SDIP42

TQFP32

SDIP32

Input

Output

Input Output

float

wpu

int

ana

6 1 30 1 PB4 (HS)

I/O CTHS X ei3 X X Port B4

7 2 31 2 PD0/AIN0 I/O C

X X X X X Port D0 ADC Analog Input 0

8 3 32 3 PD1/AIN1 I/O C

X X X X X Port D1 ADC Analog Input 1

9 4 PD2/AIN2 I/O C

X X X X X Port D2 ADC Analog Input 2

10 5 PD3/AIN3 I/O C

X X X X X Port D3 ADC Analog Input 3

11 6 PD4/AIN4 I/O C

X X X X X Port D4 ADC Analog Input 4

12 7 PD5/AIN5 I/O C

X X X X X Port D5 ADC Analog Input 5

13 8 1 4 V

AREF

S Analog Reference Voltage for ADC

14 9 2 5 V

SSA

S Analog Ground Voltage

15 10 3 6 PF0/MCO/AIN8 I/O C

X ei1 X X X Port F0

Main clock out (f

OSC

/2)

ADC Analog Input 8

16 11 4 7 PF1 (HS)/BEEP I/O C

HS X ei1 X X Port F1 Beep signal output

17 12 PF2 (HS) I/O C

HS X ei1 X X Port F2

18 13 5 8

PF4/OCMP1_A/ AIN10

I/O C

X X X X X Port F4

Timer A Output Compare 1

ADC Analog Input 10

19 14 6 9 PF6 (HS)/ICAP1_A I/O C

HS X X X X Port F6 Timer A Input Capture 1

20 15 7 10

PF7 (HS)/ EXTCLK_A

I/O C

HS X X X X Port F7

Timer A External Clock Source

21 V

DD_0

S Digital Main Supply Voltage

22 V

SS_0

S Digital Ground Voltage

23 16 8 11

PC0/OCMP2_B/ AIN12

I/O C

X X X X X Port C0

Timer B Output Compare 2

ADC Analog Input 12

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Notes:

1. In the interrupt input column, “eiX” def ine s the associate d external in terrupt vecto r. If the weak pul l-up

24 17 9 12

PC1/OCMP1_B/ AIN13

I/O C

X X X X X Port C1

Timer B Output Compare 1

ADC Analog Input 13

25 18 10 13 PC2 (HS)/ICAP2_B I/O C

HS X X X X Port C2 Timer B Input Capture 2

26 19 11 14 PC3 (HS)/ICAP1_B I/O C

HS X X X X Port C3 Timer B Input Capture 1

27 20 12 15

PC4/MISO/ICCDATA

I/O C

X X X X Port C4

SPI Master In / Slave Out Data

ICC Data Input

28 21 13 16 PC5/MOSI/AIN14 I/O C

X X X X X Port C5

SPI Master Out / Slave In Data

ADC Analog Input 14

29 22 14 17 PC6/SCK/ICCCLK I/O C

X X X X Port C6

SPI Serial Clock

ICC Clock Output

30 23 15 18 PC7/SS

/AIN15 I/O C

X X X X X Port C7

SPI Slave Select (active low)

ADC Analog Input 15

31 24 16 19 PA3 (HS) I/O C

HS X ei0 X X Port A3

32 25 V

DD_1

S Digital Main Supply Voltage

33 26 V

SS_1

S Digital Ground Voltage

34 27 17 20 PA4 (HS) I/O C

HS X X X X Port A4

35 28 PA5 (HS) I/O C

HS X X X X Port A5

36 29 18 21 PA6 (HS) I/O C

HS X T Port A6

37 30 19 22 PA7 (HS) I/O CTHS X T Port A7

38 31 20 23 V

/ICCSEL I

Must be tied low. In the flash programming mode, this pin acts as the programming voltage input V

. See

Section 12.9.2 for more details. High

voltage must not be applied to ROM devices.

39 32 21 24 RESET

I/O C

Top priority non maskable interrupt.

40 33 22 25 V

SS_2

S Digital Ground Voltage

41 34 23 26 OSC2 O Resonator oscillator inverter output 42 35 24 27 OSC1 I

External clock input or Resonator oscillator inverter input

43 36 25 28 V

DD_2

S Digital Main Supply Voltage

44 37 26 29 PE0/TDO I/O C

X X X X Port E0 SCI Transmit Data Out

1 38 27 30 PE1/RDI I/O C

X X X X Port E1 SCI Receive Data In

2 39 28 31 PB0 I/O C

X ei2 X X Port B0

3 40 PB1 I/O C

X ei2 X X Port B1

4 41 PB2 I/O C

X ei2 X X Port B2

5 42 29 32 PB3 I/O C

X ei2 X X Port B3

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate Function

TQFP44

SDIP42

TQFP32

SDIP32

Input

Output

Input Output

float

wpu

int

ana

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column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V

are not implemented). See See “I/O PORTS” on page 45. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crys tal/ceram ic resonator, or an external source t o t he on-chi p os cillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The c onfiguration of these pad s mu st b e k ept at res et s tat e t o avoi d added current consumption.

5. In ROM devices, there is no weak pull-up on PB4.

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3 REGISTER & MEMORY MAP

As sho wn i n Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space in cludes up to 256 byt es for the stack from 0100h to 01FFh.

The highest address bytes contain the user re set and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must ne ver be accessed. Ac cessing a reseved area can have u npredict able effects on t he device.

Figure 5. Me m ory M a p

0000h

RAM

Program Memory (32K, 16K or 8K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

FFDFh FFE0h

FFFFh

(see Table 7)

0880h

Reserved

087Fh

Short Addressing RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

027Fh

0080h

0200h

00FFh

32 KBytes

8000h

FFFFh

(1024,

or 047Fh

16 KBytes

C000h

512 or 384 Bytes)

8 Kbytes

E000h

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Table 2. Hardware Register Map

Address Block

Label

Reset

Status

Remarks

0000h 0001h 0002h

Port A

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

00h

00h 00h

R/W R/W R/W

0003h 0004h 0005h

Port B

PBDR PBDDR PBOR

Port B Data Register Port B Data Direction Register Port B Option Register

00h

00h 00h

R/W R/W R/W

0006h 0007h 0008h

Port C

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register Port C Option Register

00h

00h 00h

R/W R/W R/W

0009h 000Ah 000Bh

Port D

PDDR PDDDR PDOR

Port D Data Register Port D Data Direction Register Port D Option Register

00h

00h 00h

R/W R/W R/W

000Ch 000Dh 000Eh

Port E

PEDR PEDDR PEOR

Port E Data Register Port E Data Direction Register Port E Option Register

00h

00h 00h

R/W R/W

R/W

000Fh 0010h 0011h

Port F

PFDR PFDDR PFOR

Port F Data Register Port F Data Direction Register Port F Option Register

00h

00h 00h

R/W R/W R/W

0012h

0020h

Reserved Area (15 Bytes)

0021h 0022h 0023h

SPI

SPIDR SPICR SPICSR

SPI Data I/O Register SPI Control Register SPI Control/Status Register

xxh 0xh 00h

R/W R/W R/W

0024h 0025h 0026h 0027h

ITC

ISPR0 ISPR1 ISPR2 ISPR3

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

FFh FFh FFh FFh

R/W R/W R/W R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W 002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W 002Ch

002Dh

MCC

MCCSR MCCBCR

Main Clock Control / Status Register Main Clock Controller: Beep Control Register

00h 00h

R/W R/W

002Eh

0030h

Reserved Area (3 Bytes)

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Legend: x=undefined, R/W=read/write

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

TIMER A

TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register

Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Reserved

Reserved

Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

00h 00h

xxx0 x0xx b

xxh

xxh 80h 00h FFh FCh FFh FCh

80h 00h

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only

Write Only

0040h Reserved Area (1 Byte)

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER B

TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

00h 00h

xxxx x0xx b

xxh

xxh 80h 00h FFh FCh FFh FCh

xxh

xxh 80h 00h

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

SCI

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

C0h

xxh 00h

x000 0000b

00h 00h

---

00h

Read Only R/W R/W R/W R/W R/W

R/W

0070h 0071h 0072h

ADC

ADCCSR ADCDRH ADCDRL

Control/Status Register Data High Register Data Low Register

00h 00h 00h

R/W Read Only Read Only

0073h 007Fh

Reserved Area (13 Bytes)

Address Block

Label

Reset

Status

Remarks

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Notes:

1. The contents of the I/O port DR regist ers are readable only in out put c onf iguration. I n i nput c onf iguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. These registers and the ICF2 and OCF2 flags are not present in the ST72324 but are present in the emulator. For compatibility with the e mulator, it is recommended to p erform a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.

4. The registers can be written, but reading them will return undefined values.

5. Bits 2 and 4 of this register (ICF2 and OCF 2) are forced by hardware to 0. Consequent ly, the corresponding interrupts cannot be used.

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4 FLASH PROGRAM ME MORY

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugge d in a programm ing tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organ isation allows each sector to be erased and reprogramm ed without affecting other sectors.

4.2 Main Features

■ Three Flash programming modes :

– Insertion in a programming tool. In this m ode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board a nd wh ile the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection against piracy

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4. 3 S tructure

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flas h memory when only a partial erasing is required.

The first two sectors have a fixed siz e of 4 Kby tes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so t he reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 3. Sectors available in Flash devices

4.3.1 Read-out Protection

Read-out protection, when s elected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Even ST cannot access the user code.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depend s on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 6. Me m ory M a p and Sector A dd re ss

Flash Size (bytes) Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4 Kbytes

2Kbytes

SECTOR 1 SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 6 0K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh 7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes

52 Kby tes

9FFFh BFFFh D7FFh

4K 10K 24K 48K

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a m inimum of 4 and up to 6 pins to b e connected to the programming tool (see Figure 7). These pins are:

– RESET

: device reset

–V

: device power supply ground

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V

: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

–V

: application board power su pply (option-

al, see Figure 7, Note 3)

Figure 7. Typical ICC Interface

Notes:

1. If the ICCCLK or ICCDATA pins are only u sed as outputs in t he ap plication, n o s ign al iso lation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET

pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be us ed to iso late the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

agement IC with open drain ou tput and pu ll-up resistor>1K, no additional com ponents are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC con nector de pends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be co nnected to the OS C1 or OSCIN pin of the ST7 when the clock is not available in the application or if the sel ected clock opt ion is not programmed in t he option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cab le

OPTIONAL (See No te 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION RESET SOURCE

APPLICATI ON

I/O

(See No te 4)

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code dow nloaded in RAM, Flash memory programming can be fully customized (number of bytes to prog ram, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supp orts ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description.

4.6 IA P ( I n-Ap plication Pr ogram m ing)

This mode uses a BootLoader program previously stored in Sector 0 by the us er (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of comm unications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, whi ch is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash program ming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Re ference Manual

4.7.1 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. Flash Control/Status Register Address and Reset Value

00000000

Address

(Hex.)

Label

76543210

0029h

FCSR

Reset Value00000000

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5 CENTRAL PRO CESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by spec ifi c ins t ru c tio n s .

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the res ults of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as tempo rary storage areas f or data manipulation. (The Cross -Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 8. CPU Registers

ACCUMULA TOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

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CENTRAL PROC ESSING UNIT (Cont’d) Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

The 8-bit Condition Code regist er contains the i nterrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instructions. It is reset by hardware during the same instructio n s.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutine s .

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. I t’s a copy of the result 7

bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accesse d by the JRMI and JRPL instructions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions. Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an un derflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It i s also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Managem ent B i ts

Bit 5,3 = I1, I0

Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

11I1HI0NZ

Interrupt Software Priorit y I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

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CENTRAL PROC ESSING UNIT (Cont’d) Stack Poi nter (SP)

Read/Write Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hard ware. Following a n MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to sav e the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location po inted t o by t he SP. Th en t he other registers are stored in the next locations as shown in Figure 9.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ion s i n the stack ar ea.

Figure 9. Stack Manipulation Example

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

PCH PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

PCL

PCH

PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

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6 SUPPLY, RESET AND CLO CK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplyi ng the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crysta l/ C er amic resonator osc illa t or s – 1 Interna l RC o s c illat o r

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

– Clock Security System (CSS) with Cl ock Filte r

and Backup Safe Oscillator (enabled by option byte)

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC 2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 = fOSC

/2.

Caution: T he PLL is not rec ommended for ap plications where timing accuracy is required. See “PLL Characteristics” on page 128.

Figure 10. PLL Block Diagram

Figure 11. Clock, Reset and Supply Block Diagram

PLL OPTION BIT

PLL x 2

OSC2

/ 2

OSC

LOW VOLTAG E

DETECTOR

(LVD)

OSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

RESET SEQUENCE

MANAGER

(RSM)

CLOCK FILTER

SAFE

OSC

CLOCK SECURITYSYSTEM

(CSS)

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTR O LLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (W DG )

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD

LVD

CSS

CSSDWDG

OSC

OSC2

(option)

CPU

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given freq uency range in terms of consumption and is selectable through the option byte. The assoc iated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.

Caution: T he OSC1 and/or OSC2 pins must not be left unconnected. F or the purposes o f Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main osc illator m ay sta rt an d, in this configuration, could generate an f

OSC

clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are le ft unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: External clo ck source is not suppo rted with the PLL enabled.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The s election within a list of 4 os cillators with different frequency ran ges has to be done by option byte in order to redu ce consumption (refer to Se ction 14.1 on p age 149 for more details on the frequency ranges). In this mode o f the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected osci lla tor .

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capac it or. Int ernal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timin g .

In this mode, the two oscillator pins have to be tied to ground.

Table 4. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

OSC1 OSC2

ST7

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introd uc tion

The reset sequence manager in cludes three RESET sources as shown in F igure 13:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RE SET sequence consists of 3 phases

as shown in F igure 12:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

opt ion byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from t he Reset st ate. T he short er or longer clock cycle delay should be selected by option byte to correspond to the stabilization t ime of the external oscillator used in the application (see Section 14.1 on page 149).

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

6.3.2 Async hr onous Extern a l RESET

The RESET

pin is both an input and an open-drain

output with integrated R

weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See

“CONTROL PIN CHARACTERISTICS” on page 138 for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET LVD RESET

INTERNAL RESET

PULSE

GENERATOR

Filter

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RESET SEQUENCE MANAGER (Cont’d) The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the elect rical characteristics section.

If the external RESET

pulse is shorter than

w(RSTL)out

(see short ext. Reset in Figure 14), the

signal on the RESET

pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 14). Starting from the external RESET pulse recognition, the device RESET

pin acts as an output that is pulled low during at least t

w(RSTL)out

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V

is over the minimum

level specified for the selected f

OSC

frequency.

(see “OPERATING COND ITIO NS” on page 115)

A proper reset signal for a sl ow rising V

supply can generally be p rovided by an e xternal RC ne twork connected to the RESET

pin.

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two differe nt RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET

pin acts as an output that is

pulled low when V

DD<VIT+

(rising edge) or

DD<VIT-

(falling edge) as shown in Figure 14 .

The LVD filters spikes on V

larger than t

g(VDD)

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the device RESET

pin acts as an output that is pulled

low during at least t

w(RSTL)out

Figure 14. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

w(RSTL)out

RUN

h(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN RUN

RESET

RESET SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTE RNAL RESET ( 256 or 4096 T

CPU

)

VECTOR FETCH

w(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Mana gement block co ntains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) functions and Clo ck Security System (CSS). It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Dete ctor function (LVD) generates a static reset when the V

supply voltage is

below a V

IT-

reference value. This means that it secures the power-up as well as the power-dow n keeping the ST7 in reset.

The V

IT-

reference value for a voltage drop is lower

than the V

IT+

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generat es a reset when V

is below:

–V

IT+

when VDD is rising

–V

IT-

when VDD is falling

The LVD func t io n is illustrat ed in F igure 15. The voltage threshold can be configured by option

byte to be low, medium or high.

Provided the minimum V

value (guaranteed for

the oscillator frequency) is above V

IT-

, the MCU

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. If the medium or low thresholds are selected, the

detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional func tion which can be selected by option byte.

Figure 15. Low Voltage Detector vs Reset

IT+

RESET

IT-

hys

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V

IT-(AVD)

and

IT+(AVD)

reference value and the VDD main sup-

ply. The V

IT-

reference value f or falling voltage is

lower than the V

IT+

reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in t he S ICS R regi ster. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the V

Main Sup ply

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byt e (see Section 14.1 on page 149).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V

IT+(AVD )

IT-(AVD)

threshold (AVDF bit toggles).

In the case of a drop i n v oltage, t he A V D i nterrupt acts as an early warning, allowing software to shut down safely before the LV D resets the microcontroller. See Figure 16.

The interrupt on the rising edge is used to info rm the application that the V

warning state is over.

If the voltage rise time t

is less than 256 or 4 096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

IT+(AVD)

is reached.

If t

is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached then only one AVD interrupt will occur.

Figure 16. Using the AVD to Monitor V

IT+(AVD)

IT-(AVD)

AVDF bit 0 0RESET VALUE

IF AVDIE bit = 1

hyst

AVD INTERRUPT REQUEST

INTERRUPT PROCESS

IT+(LVD)

IT-(LVD)

LVD RESET

Early Warning Interrup t

(Power has dropped, MCU not not yet in reset)

VOLTAGE RISE TIME

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock sourc e (f

OSC

). It is based on a clock filter and a clock detection control with an internal safe oscillator (f

SFOSC

Caution: The CSS function is not guaranteed. Refer to Section 15

6.4.3.1 Clock Filter Control

The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. This feature is available only when t he PLL is enabled. If glitches occur on f

OSC

(for example, due to loose connection or noise), the CSS filters t hese automatically, so the internal CPU frequency (f

CPU

)

continues deliver a glitch-free signal (see Figure

17).

6.4.3.2 Clock detection Control

If the clock signal disappears (due to a broke n or disconnected resona tor...), the safe os cillator delivers a low frequency clock signal (f

SFOSC

) whi c h allows the ST7 to perform some rescue operations.

Automatically, the ST7 clock source switches back from the safe o scillator (f

SFOSC

) if the main clock

source (f

OSC

) recovers.

When the internal clock (f

CPU

) is driven by the safe

oscillator (f

SFOSC

), the application software is noti-

fied by hardware setting the CSSD bit in the SI C-

SR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the SICSR register description.

6.4.4 Low Power Mo des

6.4.4.1 Interrupts

The CSS or AVD interrupt events g enerate an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Figure 17. Clock Filter Function

Mode Description

WAIT

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

HALT

The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

CSS event detection (safe oscillator activated as main clock)

CSSD CSSIE Yes No

AVD event AVDF AVDIE Yes No

OSC2

CPU

OSC2

CPU

SFOSC

PLL ON

Clock Filter Function

Clock Detection Function

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.5 Register Description SYSTEM INTE GRITY (SI) CONTRO L/ STATUS REGISTER (SIC SR )

Read/Write Reset Value: 000x 000x (00h)

Bit 6 = AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Bit 5 = AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to

Figure 16 and to Section 6. 4.2.1 for additional de-

tails. 0: V

over V

IT+(AVD)

threshold

1: V

under V

IT-(AVD)

thres h old

Bit 4 = L VDRF

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bits 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE

Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled

1: Clock security system interrupt enabled When the CSS is disabled by OPTION BYTE, t he CSSIE bit has no effect.

Bit 1 = CSSD

Clock security system dete cti o n

This bit indicates that the safe oscillator of the Clock Security System block has been selected by hardware due to a disturbance on the ma in clock signal (f

OSC

). It is set by hardware a nd clea red by reading the SICSR register when the original oscillat o r recove rs . 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is disabled by OPTION BYTE, t he CSSD bit value is forced to 0.

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog p eripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

Applicat i on notes

The LVDRF flag i s not cleared when another RE SET type occurs (external or watchdog), the LVDRF flag remains set to ke ep trace of the original failure. In this case, a watchdog res et can be detected by software while an external reset can not.

CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.

AVD

AVDFLVD

CSSIECSSDWDG

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses locat ed at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt cont roller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKI N G AND PRO C ESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 5 ). The processing flow is shown in Figure 18

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which c auses the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 5. Interrupt Software Priority Levels

Figure 18. Int errupt Processing Flowchart

Interrupt software priority Level I1 I0

Level 0 (main) Low

High

10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

“IRET”

RESTORE PC, X, A, C C

STACK PC, X, A, CC

LOAD I1:0 FRO M INTERR UPT SW REG.

FETCH NEX T

RESET

TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT STAYS PENDING

than c u rrent one

Interrupt has a higher

softwarepriority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

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INTERRUPTS (Cont’d) Servicing Pending In te rrup t s

As several interrupts can b e pen ding at the s ame time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 19 describes this decision process.

Figure 19. Priority Decision Process

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one i s not. This allows the prev ious process to succeed with only one interrupt. Note 2: RESET and TRAP can be conside red as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maska ble type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 18). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 18.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrup t vector sourc es can be servi ced if the corresponding in terrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two co nditions is false, the interrupt is la tched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these w ill be log i cally ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except thos e mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the c orresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupt s allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present whi le exiting HALT mode, the first one serviced can only be an interrupt with e xit from HALT mode c apability and it is selected through the same decision proc ess shown in Figure 19.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and do es not allow an interrupt to be interrupted, unlike the nested mode in

Figure 21. The interrupt hardware priority is given

in this order from the l owes t to the hi ghest: M A IN, IT4, IT3, IT2, IT1, IT0. The softwa re priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Figure 20. Concurrent Interru pt Manage me nt

Figure 21. Nested Interrupt Management

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

HARDWARE PRIORITY

SOFTWARE

3 3 3 3 3 3/0

11 11 11 11 11

11 / 10

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

PRIORITY LEVEL

USED STACK = 10 BYTES

MAIN

IT2

TRAP

MAIN

IT0

IT2

IT1

IT4

TRAP

IT3

IT0

HARDWARE PRIORITY

3 2 1 3 3 3/0

11 00 01 11 11

RIM

IT1

IT4 IT4

IT1

IT2

IT3

I1 I0

11 / 10

SOFTWARE PRIORITY LEVEL

USED STACK = 20 BYTES

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INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0

Soft w a re In te r rupt Pr i ority

These two bits indicate the current interrupt software priority.

These two bits are set/cle ared by hardware whe n entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also s et/cleared by s oft ware wi th the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: TRAP and RESET events can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is execu ted the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is highe r than the previous one, the interrupt x is re-ent ered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

11I1 H I0 NZC

Interrupt Software Priority Level I1 I0

Level 0 (main) Low

High

10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

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INTERRUPTS (Cont’d)

Table 6. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 (level 3) I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

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INTERRUPTS (Cont’d) Table 7. Interrupt Mapping

Notes:

1. Valid for HA LT mode except f or the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT mode.

2. Exit from HALT possible when SPI is in slave mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Po r t Inter r upt Sensi tivit y

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows to have up to 4 fully independent external interrupt source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR.

N°

Source

Block

Description

Label

Priority

Order

Exit from

HALT

Address

Vector

RESET Reset

N/A

yes FFFEh-FFFFh

TRAP Software interrupt no FFFCh-FFFDh

0 Not used FFFAh-FFFBh 1

MCC/RTC

CSS

Main clock controller time base interrupt Safe oscillator activation interrupt

MCCSR

SICSR

Higher

Priority

yes FFF8h-FFF9h

2 ei0 External interrupt port A3..0

N/A

yes FFF6h-FFF7h 3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h 4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h 7 SPI SPI peripheral interru pts SPICS R yes

FFECh-FFEDh 8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh 9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h

10 SCI SCI Peripheral interr upts SCISR

Lower

Priority

no FFE6h-FFE7h

11 AVD Auxiliary Voltage detector interrupt SICSR no FFE4h-FFE5h

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INTERRUPTS (Cont’d) Figure 22. Exte rn al Int erru pt Control bits

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.3

PBDDR.3

IPB BIT

PB3

ei2 INTE R RUPT SOURCE

PORT B [3:0] IN T ERRUPTS

PB3 PB2

PB1 PB0

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.7

PBDDR.7

PB7

ei3 INT ERRUPT S O URCE

PORT B [7:4] INTERRUPTS

PB7 PB6

PB5 PB4

IS20 IS21

EICR

SENSITIVITY

CONTROL

PAOR.3

PADDR.3

IPA BIT

PA3

ei0 INTERRUPT SOURCE

PORT A3 INTERRUPT

IS20 IS21

EICR

SENSITIVITY

CONTR O L

PFOR.2

PFDDR.2

PF2

ei1 INT ERRUPT S O URCE

PORT F [2:0] INTE R RUPTS

PF2 PF1

PF0

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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts:

- ei2 (port B3..0)

- ei3 (port B4)

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = IPB

Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set a nd clea red by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sens it iv ity inv e r sio n 1: Sensit iv it y inve r s ion

Bit 4:3 = IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

- ei0 (port A3..0)

- ei1 (port F2..0)

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 2 = IPA

Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

IS11 IS10 IPB IS21 IS20 IPA 0 0

IS11 IS10

External Interrupt Sensit ivity

IPB bit =0 IPB bit =1

Falling edge &

low level

Rising edge

& high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

IS21 IS20

External Interrupt Sensitivity

IPA bit =0 IPA bit =1

Falling edge &

low level

Rising edge

& high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

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INTERRUPTS (Cont’d) Table 8. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Label

76543210

0024h

ISPR0

Reset Value

ei1 ei0 MCC + SI

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

111

0025h

ISPR1

Reset Value

SPI ei3 ei2

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

0026h

ISPR2

Reset Value

AVD SCI TIMER B TIMER A

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

0027h

ISPR3

Reset Value 1 1 1 1

I1_13

I0_13

I1_12

I0_12

0028h

EICR

Reset Value

IS11

IS10

IPB

IS21

IS20

IPA

000

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8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): SLOW, WAIT (SLOW WAIT ), AC- TIVE HALT and HALT.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (f

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 23. P ower Savin g Mode Trans i tio ns

8.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

CPU

In this mode, the master clock frequency (f

OSC 2

) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (f

CPU

Note: SLOW-WAIT mode is activated when entering the WAIT mode wh ile the device is already in SLOW mode.

Figure 24. SLOW Mode Clock Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

00 01

SMS

CP1:0

CPU

NEW SLOW

NORMAL RUN MODE

MCCSR

FREQUENCY

REQUEST

OSC2

/2 f

OSC2

/4 f

OSC2

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POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power c onsumption mode by stopping the CPU. This pow e r s a v ing mo de is se lected b y ca llin g the ‘WFI’ inst ru c ti on . All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC regist er are fo rced t o ‘ 10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remai ns in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches t o the starting address of the interrupt or Reset service routine. The MCU w ill re mai n in W AIT mo de unt il a Res et or an Interrupt occurs, causing it to wake up.

Refer to Figure 25.

Figure 25. WAIT Mode Flow-chart

Note:

1. Before servicing an interrupt , the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

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POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MC U. They are both entered by exe cuting the ‘HALT’ in struction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the M CU with a real time c lock available. It is entered by ex ecut ing the ‘ HAL T’ instruction when the OI E bit of t he M ain Clock Controller Status register (MCCSR) is set (see Section

10.2 on page 56 for m ore details on the M CCSR

tion of an MCC/RTC interrupt or a RESET. When exiting ACTIVE-HALT mode by means of an MCC/ RTC interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pendi ng, the MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked ex cept t hose which get the ir clock supply from another clock generator (such as externa l or au x iliary oscilla t or ) .

The safeguard against st aying locked in AC TIVEHALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode following an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before t

DELAY

after

the interrupt occurs (t

DELAY

= 256 or 4096 t

CPU

delay depending on option byte). Otherwise, the ST7 enters HALT mode for the rem aining t

DELAY

peri-

od.

Figure 26. ACTIVE-HALT Timing Overview

Figure 27. ACTIVE-H A LT Mode Flow - chart

Notes:

1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET.

2. Peripheral clocked with an external clock source can still be active.

3. Only the MCC/RTC interrupt can exit the MCU from ACTIVE-HALT mode.

4. Before servicing an interrupt , the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 HALT mode 1 ACTIVE-HALT mode

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256OR4096CPUCLOCK

CYCLE DELAY

(MCCSR.OIE=1)

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POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 10.2 on page 56 for more details on the MCCSR register).

The MCU can e xit HAL T mode on reception of either a specific interrupt (see Table 7, “Interrupt

Mapping,” on page 36) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by s ervicing the i nterrupt o r by fetching the reset vector which woke it up (see Fig-

ure 29).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 14.1 on page 149 for more details).

Figure 28. HALT Timing Overview

Figure 29. H A LT Mode Fl ow-cha rt

Notes:

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts c an ex it the M C U from HALT mode (such as ext ernal inte rrupt). Refer to Table 7, “Interrupt Mapping,” on page 36 for more details.

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

(MCCSR.OIE=0)

CYCLE

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POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up t he

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

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9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs

and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Im plement ation section). The generic I/O block diagram is shown in Figure 30

9.2.1 Input Modes

The input configuration is s ele cted by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies t he latch v alu e but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independen tly generat e an interrupt request. The interrupt sensitivity is independent ly programmable using the sensitivity bits in the EICR register.

Each external interrupt vecto r is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several inpu t pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.

9.2.2 Output Modes

The output configuration is selecte d by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to t he I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is au tomatically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is autom ati cally conf igured in ou tput mode (push-pull or open drain according to the peripheral).

When the signal is goi ng t o an on-c hip pe ripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin h as to be configured in input floating mode.

DR Push-pull Open-drain

Vss

Floating

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I/O PORTS (Cont’d) Figure 30. I/O Port General B lo ck D iag ram

Table 9. I/O Port Mode Options

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

Note: The diode to V

is not implemented in the true open drain pads. A local protection between the pad and V

is implemented to protect the de-

vice against positive stress.

Configuration Mode Pull-Up P-Buffe r

Diodes

to V

Input

Floating with/without Interrupt Off

Off

Pull-up with/withou t Interrupt On

Output

Push-pull

Off

On Open Drain (logic level) Off True Open Drain NI NI NI (see note)

DDR

DATA BUS

PAD

ALTERNATE ENABLE

ALTERNATE OUTPUT

OR SEL

DDR SEL

DR SEL

PULL-UP CONDITION

P-BUFFER (see table below)

N-BUFFER

PULL-UP (see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

DIODES (see table below)

EXTERNAL

SOURCE (eix)

INTERRUPT

CMOS SCHMITT TRIGGER

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I/O PORTS (Cont’d) Table 10. I/O Port Configurations

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate func tion outp ut status.

2. When the I/O port is in output configuration and t he associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

Hardware Configuration

INPUT

OPEN-DRAIN OUTPUT

PUSH-PULL OUTPUT

CONDITION

PAD

EXTERNAL INTERRUPT

DAT A BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

SOURCE (ei

)

CONDITION

ALTERNATE INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

ANALOG INPUT

PAD

DAT A BUS

DR REGISTER ACCESS

R/W

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

PAD

DAT A BUS

DR REGISTER ACCESS

R/W

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

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I/O PORTS (Cont’d) CAUTION: The alternate funct ion must not be ac -

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. Th e analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins loca ted clos e to a s ele cted analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum r a tings.

9.3 I/O PORT IMPL EMENTATION

The hardware implementation on each I/O port depends on the settings in t he DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state t o another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions are potentially risky and shou ld be av oided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 31. Interrupt I/O Port State Transitions

9.4 LOW POWER MODES

9.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Mode Description

WAIT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

HALT

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on selected external event

DDRx

ORx

Yes Yes

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

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I/O P O R TS (Cont’d)

9.5.1 I/O Port Implementation

The I/O port register configurations are summarised as follows.

Stan da rd Po rt s PA5:4, PC7:0, PD5:0,

PE1:0, PF7:6, 4

Interrupt Ports PB4, PB2:0, PF1:0 (wit h pu ll- up )

PA3, PB3, PF2 (without pull-up)

True Open D rai n Ports PA7:6

Table 11. Port Configuration

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1

MODE DDR

floating input 0 open drain (high sink ports) 1

Port Pin name

Input Output

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA7:6 floating true open-drain PA5:4 floating pull-up open drain push-pull PA3 floating floating interrupt open drain push-pull

Port B

PB3 floating floating interrupt open drain push-pull

PB4, PB2:0 floating pull-up interrupt open drain push-pull Port C PC7:0 floating pull-up open drain push-pull Port D PD5:0 floating pull-up open drain push-pull Port E PE1:0 floating pull-up open drain push-pull

Port F

PF7:6, 4 floating pull-up open drain push-pull

PF2 floating floating interrupt open drain push-pull

PF1:0 floating pull-up interrupt open drain push-pull

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I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values

Address

(Hex.)

Label

76543210

Reset Value

of all I/O port registers

00000000

0000h PADR

MSB LSB0001h PADDR 0002h PAOR 0003h PBDR

MSB LSB0004h PBDDR 0005h PBOR 0006h PCDR

MSB LSB0007h PCDDR 0008h PCOR 0009h PDDR

MSB LSB000Ah PDDDR

000Bh PDOR

000Ch PEDR

MSB LSB000Dh PEDDR

000Eh PEOR 000Fh PFDR

MSB LSB0010h PFDDR

0011h PFOR

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10 ON-CHIP PER IPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog t imer is used to d etect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

10.1.2 Main Features

■ Programmable free-running downc ount er

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 f

OSC2

cycles (approx.), and the length of the timeout period can be program med by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becom es cleared ), it initiates a reset cycle pulling low the reset pin for typically 500ns.

The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h:

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34).

Following a reset, the watchdog is disabled. Onc e activated it cannot be disabled, except by a reset.

The T6 bit can be used to gen erate a software reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Figure 32. Watchdog Bl oc k Diagram

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

OSC2

T6 T0

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

MCC/RTC

TB[1:0] bits (MCCSR Register)

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WATCH DOG TI MER (Cont’d)

10.1.4 How to Program the Watchdog Timeout

Figure 3 3 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If

more precision is needed, use the formulae in Fig-

ure 34.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.

Figure 33. Approx imat e Timeout Duration

CNT Value (hex.)

Watchdog timeout (ms) @ 8 MHz. f

OSC2

128

1.5 65

503418 82 98 114

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WATCH DOG TI MER (Cont’d) Figure 34. Exact Timeout Duration (t

min

and t

max

)

WHERE:

min0

= (LSB + 128) x 64 x t

OSC2

max0

= 16384 x t

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are v alues f rom the t able b elow d epending on the timeba se s elected by t he T B[1:0] bits

in the MCCSR register

To calculat e t he m i ni m um W at chdog Tim e ou t (t

min

IF THE N

ELSE

To calculate the maximum Watchdog Timeout (t

max

IF THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value. Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.)

TB0 Bit

(MCCSR Reg.)

Selected MCCSR

Timebase

MSB LSB

0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

00 1.496 2.048

3F 128 128.552

CNT

MSB

-------------

mintmin0

16384 C NT t

osc2

××

mintmin0

16384 C NT

4CNT

MSB

---------------- -

–





× 192 LSB+()64

4CNT

MSB

---------------- -

××

osc2

×+=

CNT

MSB

-------------

≤

maxtmax0

16384 CNT t

osc2

××

maxtmax0

16384 C NT

4CNT

MSB

---------------- -

–





× 192 LSB+()64

4CNT

MSB

---------------- -

××

osc2

×+=

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WATCH DOG TI MER (Cont’d)

10.1.5 Low Power Mo des

10.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by o ption byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Ref er to the Option B yt e description.

10.1.7 Using Halt Mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

10.1.8 Interrupts

None.

10.1.9 Register Description CONTROL REGISTER (WDGCR)

Read/Write Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA

Activation bit

. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every 16384 f

OSC2

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

HALT

OIE bit in

MCCSR register

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.7 below.

0 1 A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

WDGA T6 T5 T4 T3 T2 T1 T0

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Table 13. Watchdog Time r Register Map and Rese t Values

Address

(Hex.)

Label

76543210

002Ah

WDGCR

Reset Value

WDGA

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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consi sts of three di fferent functions:

■

a programmable CPU clock prescaler

■

a clock-out signal to supply external devices

■

a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1

Programmable CPU Clock Prescaler

The programmable CPU clock prescaler suppli es the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See

Section 8.2 SLOW MODE for more details).

The prescale r select s t he f

CPU

main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS.

10.2.2

Clock-out Capability

The clock-out capability is an alternate function of an I/O port pin that outputs a f

OSC2

clock to drive

external devices. It is co ntrolled by the M C O bit in the MCCSR register. CAUTION: When selected, the clock out pin sus pends the clock during ACTIVE-HALT mode.

10.2.3

Real Tim e C lo c k Ti m er ( R TC)

The counter of the real time c lock timer allows an interrupt to be generated based on an accurate real time clock. Four di fferent t ime bases de pending directly on f

OSC2

are available. The whole functionality is controlled by four bits of the M CCSR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OI E bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 8.4 AC-

TIVE-HALT AND HALT MODES for more details.

10.2.4

Beeper

The beep function is cont rolled by the MCCB CR register. It can output three selectable frequencies on the BEEP pin (I/O port altern a te function).

Figure 35.

Main Clock Controller (MCC/RTC) Block Diagram

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMSCP1 CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

12-BIT MCC RTC

COUNTER

TO CPU AND

PERIPHERALS

OSC2

CPU

MCO

BC1 BC0

MCCBCR

BEEP

SELECTION

BEEP SIGNAL

WATCHDOG

TIMER

DIV 64

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5

Low Power Mo des

10.2.6

Interrupts

The MCC/RTC interrupt even t generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).

Note: The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

10.2.7

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0000 (00h

)

Bit 7 = MCO

Main clock out selectio n

This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

CPU

on I/O

port)

Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.

Bit 6:5 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

Bit 4 = SMS

Slow mode select

This bit is set and cleared by software. 0: Normal mode. f

CPU

= f

OSC2

1: Slow mode. f

CPU

is given by CP1, CP0 See Sec tion 8.2 SLOW MODE and S ection 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0]

Time base control

These bits select the programmable divider time base. They are set and cleared by software.

A mod ification of th e time base is taken into ac count at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode

Mode Description

WAIT

No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode.

ACTIVEHALT

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

HALT

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow event

OIF OIE Yes No

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

CPU

in SLOW mode CP1 CP0

OSC2

/ 2 0 0

OSC2

/ 4 0 1

OSC2

/ 8 1 0

OSC2

/ 16 1 1

Counter

Prescaler

Time Base

TB1 TB0

OSC2

=4MHz f

OSC2

=8MHz

16000 4 ms 2ms 0 0 32000 8 ms 4ms 0 1 80000 20ms 10ms 1 0

200000 50 ms 25ms 1 1

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF

Oscilla t or in t er ru pt fl ag

This bit is set by hardware and cleared by soft ware reading the MCCSR register. It indicates when set that the main os cillator has reached t he selected elapsed time (TB1:0). 0: Ti meout not re ached 1: Timeout reached

CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVEHALT mode but has t o be disabled to reduce the consumption.

Table 14. Main Clock Controll er Register Ma p and Reset Values

000000BC1BC0

BC1 BC0 Beep mode with f

OSC2

=8MHz

00 Off 0 1 ~2-KHz

Output

Beep signal

~50% duty cycle

1 0 ~1-KHz 1 1 ~500-Hz

Address

(Hex.)

Label

76543210

002Bh

SICSR

Reset Value 0

AVDIE

AVDF0LVDRF

CSSIE

CSSD0WDGRF

002Ch

MCCSR

Reset Value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh

MCCBCR

Reset Value000000

BC1

BC0

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10.3 16-BIT TIMER

10.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurem ent of up to two in put signals (

input capture

) or generation of up to two out-

put waveforms (

output compare

and

PWM

Pulse lengths and wave form periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit t imers. They are completely independent, and do not share any resources. They are synchronized a fter a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two tim ers, register names are prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main Features

■ Programmable prescaler: f

CPU

divided by 2, 4 or 8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower than the CPU

clock speed) with the choice

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 36. *Note: Some timer pins may not available (not

bonded) in some ST7 devices. Refer to the device pin out description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.3.3 Functional D escripti on

10.3.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nifican t b yte (MS By te ) .

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate C ounter H igh Re gister ( ACHR) is t he

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byt e (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register reset s the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on th e clock control bits of the CR2 register, as illustrated in Table 15 Clock

Control Bits. The value i n the counter register re-

peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

Caution: Timer A functionality has the following restrictions:

– TAOC2 HR and TAOC2LR regist ers are write

only – Input Capture 2 is not implemented – The correspondi ng inte rrupts cannot be used

(ICF2, OCF2 forced by hardware to zero)

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16-B IT TIME R (Cont’d) Figure 36. Timer Block Diagram

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE REGISTER

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT CIRCUIT

1/2 1/4

1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

EXTCLK

CPU

TIMER INTERRUPT

ICF2ICF1

TIMD

OCF2OCF1 TOF

PWMOC1E

EXEDG

IEDG2CC0CC1

OC2E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

ICAP2

LATCH2

OCMP2

8 low

8 high

16 16

(Control Register 1) CR1

(Control Register 2) CR2

(Control/Status Register)

8 8 8

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT COMPARE REGISTER

INPUT

CAPTURE

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (Se e device Interrupt V ector Tabl e)

(See note)

CSR

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16-B IT TIME R (Cont’d) 16-bit read sequence: (from either the Counter

The user must read the MS Byte first, then the LS Byte value is buffered automatically.

This buffered val ue remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the c ount value at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or P WM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchroni zed with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU c lock must occur between two consecutive active edges of the external clock; t hus the external clock frequency must be less than a quarter of the CPU clock frequency.

is buffered

Read

At t0

Read

Returns the buffered

LS Byte value at t0

At t0 +∆t

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

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16-B IT TIME R (Cont’d) Figure 37. Counter Timing Diagram, internal clock divided by 2

Figure 38. Counter Timing Diagram, internal clock divided by 4

Figure 39. Counter Timing Diagram, internal clock divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

CPU CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

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16-B IT TIME R (Cont’d)

10.3.3.3 Input Capture

In this section, the index,

, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R and IC2R) are used to latch the v alue of the free running counter after a transition is detected on th e ICAP

pin (see figure 5).

R register is a read-only register.

The active transition is software programmable through the IEDG

bit of Control Registers (CRi).

Timing resolution is one count of the free running counter: (

CPU

/CC[1:0]).

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is

available). And select the following in the CR1 register: – Set the IC IE b it to ge nerate an in terrupt after a n

input capture com ing from e ither the I CAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating inp ut or inp ut with pul l-

up without interrupt if this configuration is availa-

ble).

When an input capture occurs: – ICF

bit is set.

– The IC

R register contains the v alue of the free running counter on the active transition on the ICAP

pin (see Figure 41).

– A timer interrupt is generated if the ICIE bit is s et

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (i.e. clearing the ICF

bit) is done in two steps:

1. Reading the SR register while the ICF

bit is set.

2. An acc ess (read or write) to the IC

iLR

Notes:

1. After reading the IC

HR register, transfer of

input capture data is inhibited and ICF

will

never be set until the IC

LR register is also

read.

2. The IC

R register contains the free running counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In O ne pulse Mode and PWM mode only I nput Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly con nected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAP

pins is configured as an input and t he second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function

is disabled by reading the ICiHR (see note

1).

6. T he TO F bit c an be used wi th interrupt generation in order to m easure events that go b eyond the timer range (FFFFh).

7. T he ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A. The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).

MS Byte LS Byte

ICiR IC

HR ICiLR

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16-B IT TIME R (Cont’d) Figure 40. Input Capture Block Diagram

Figure 41. Input Capture Timing Diagram

ICIE

CC0

CC1

16-BIT FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

16-BIT

IC1R Register

IC2R Register

EDGE DETECT

CIRCUIT1

FF01 FF02 FF03

FF03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edg e.

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16-B IT TIME R (Cont’d)

10.3.3.4 Output Compare

In this section, the index,

, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer .

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is fou nd bet ween the Output Com pare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is se t – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be c ompared to the counter register each timer clock cycle.

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

R value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– S et the OCiE bit if an output is needed then the

OCMP

pin is dedica ted to the output c ompare

signal.

– Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVL

bit to applied to the OCMPi pins

after the match occurs. – S et the OCIE b it to generate an in terrupt if it is

needed. When a match is found between OCRi register

and CR register: – OCF

bit is set.

– The OCMP

pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC

R register value required for a specific timing application can be calculated using the following f ormula :

Where:

∆t = Output compare period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 15

Clock Control Bits)

If the timer clock is an external clock, the formula is:

Where:

∆t = Output compare period (in seconds)

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e. clearing the OCF

bit) is done by:

1. Reading the SR register while the OCF

bit is

set.

2. An access (read or write) to the OC

LR register.

The following procedure is recommended to prevent the OCF

bit from being set between the time

it is read and the write to the OC

R register:

– Write to the OC

HR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

bit, which may be already set).

– Write to the OC

LR register (enables the output

compare function and clears the OCF

bit).

MS Byte LS Byte

ROC

HR OCiLR

∆ OC

R =

∆t * f

CPU

PRESC

∆ OC

R = ∆t

* fEXT

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16-B IT TIME R (Cont’d) Notes:

1. After a proc essor write cycle to the O C

iHR

iLR

2. If the OC

E bit is not set, the OCMPi pin is a

general I/O port and the OLVL

bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCFi and

OCMP

are set while the counter value equals

the OC

R register value (see Figure 43 on page

67). This behaviour is the same in OPM or

PWM mode. When the timer clock is f

CPU

/4, f

CPU

/8 or in

external clock mode , OCF

and OCMPi are set

while the counter value equals the OC

R regis-

ter value plus 1 (see F igure 44 on page 67).

4. The output compare functions can be used both for generating external events on the OCMP

pins even if the input capture mode is also used.

5. The value in the 16-bit OC

R register and the

OLV

bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

6. T he TAOC2HR, TAO C2LR registers are "writeonly" in Timer A. The corresponding event cannot be generated (OCF2 is forced by hardware to 0).

Forced Compare Output capab ility

When the FOLV

bit is set by software, the OLVL

bit is copied to the OCMPi pin. The OLVi bit has to be toggled in o rder t o t oggle the OCMP

pin when

it is enabled (OC

E bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVL

bits have no effect in both one pulse

mode and PWM mode.

Figure 42. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

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16-B IT TIME R (Cont’d) Figure 43. Output Compare Timing Diagram, f

TIMER

CPU

Figure 44. Output Compare Timing Diagram, f

TIMER

CPU

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

(OCRi)

OUTPUT COMPARE FLAG

(OCFi)

OCMP

PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

(OCRi)

COMPARE REGISTER

LATCH

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

OCMPi PIN (OLVLi=1)

OUTPUT COMPARE FLAG

(OCFi)

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16-B IT TIME R (Cont’d)

10.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the op p os ite column) .

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the a ctive t ransit ion o n the

ICAP1 pin with the IEDG1 bit

(the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the t imer clock CC [1:0] (see Table 15

Clock Control Bits).

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loade d on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Clearing the Input Capture interrupt request (i.e. clearing the ICF

bit) is done in two steps:

1. Reading the SR register while the ICF

bit is set.

2. An acc ess (read or write) to the IC

iLR

The OC1R register value required for a specific timing application ca n be calculated us ing the f ollowing formula:

Where: t = Pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 15

Clock Control Bits)

If the timer clock is an external clock the formula is:

Wher e: t = Pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the O LVL1 bit is output on the OCMP1 pin, (See Figure 45).

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can gen erate an Output Compare interrupt.

2. W hen the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be us ed to perfo rm input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge o ccurs on the ICAP1 pin and IC F1 can al so generates interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but canno t generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

6.On timer A, the OCF2 bit is forced by hardware to 0.

event occurs

Counter = OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFC h

ICF1 bit is set

ICR1 = Counter

R Value =

* fCPU

PRESC

- 5

OCiR = t

EXT

-5

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16-B IT TIME R (Cont’d) Figure 45. One Pulse Mode Timing Example

Figure 46. P ul se Wi dt h M odulatio n Mode Timin g E xa m p le wi t h 2 Out put Compare Funct i ons

COUNTER

FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLV L1=0, OLV L2=1

01F8

2ED3

IC1R

COUNTER

34E2

34E2 FFFC

OLVL2

OLVL2OLVL1

OCMP1

compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLV L1=0, OLVL2= 1

FFFC FFFD FFFE

2ED0 2ED1 2ED2

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16-B IT TIME R (Cont’d)

10.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a sign al with a frequenc y and pul se length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

If OLVL1=1 and OLVL2 =0 the length of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=O LV L2 a cont inuous signal w ill b e seen on the OCMP1 pin.

The OC

R register value required for a specific timing application can be calculated using the following f ormula :

Where: t = Signal or pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 15)

If the timer clock is an external clock the formula is:

Wher e: t = Signal or pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 ev ent causes the counter to be initialized to FFFCh (See Figure 46)

Notes:

1. Af ter a write instruction to the OC

HR register, the output compare function is inhibited until the OC

LR register is also written.

2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited.

3. T he ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In P WM mode the ICA P1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is res et each period and ICF1 can also generates interrupt if ICIE is set.

5. W hen the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

6. The TAOC2HR, TAOC2LR registers in Timer A are "write only". A read operation returns an undefined value.

7. The ICAP2 registers (TAIC2HR, TAIC2LR) are

not available in Timer A . The IC F2 b it is f orced by har dware to 0.

Counter

OCMP 1 = OLVL2

Counter = OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

R Value =

* fCPU

PRESC

- 5

OCiR = t

EXT

-5

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16-B IT TIME R (Cont’d)

10.3.4 Low Power Modes

10.3.5 Interrupts

Note: The 16-bit Timer interrupt events are co nnecte d to the sa me interru pt vector (see In terrupts chap-

ter). These events generate an interrup t if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

* The ICF2 and O CF2 bits are f orced by hardware t o 0 in Tim er A, hence there i s no interrup t event for th ese flags.

10.3.6 Summary of Timer modes

1) See note 4 in Section 10. 3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mod e

3) See note 4 in Section 10. 3.3.6 Pulse Width Mod ulation M ode

4) The TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be generated, OCF2 is forced by hardware to 0.

5) Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.

Mode Description

WAIT

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF

bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

R register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode ICF1

ICIE

Yes No

Input Capture 2 event ICF2

* Yes No

Output Compare 1 event (not available in PWM mode) OCF1

OCIE

Yes No

Output Compare 2 event (not available in PWM mode) OCF2

* Yes No

Timer Overflow event TOF TOIE Yes No

MODES

TIMER RESOURCES

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

Input Capture (1 and/or 2) Yes Yes

2)5)

Yes Yes

Output Compare (1 and/or 2) Yes Yes

Yes Yes

One Pulse Mode No

Not Recommended

1)5)

No Partially

PWM Mode No

Not Recommended

3)5)

No No

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16-B IT TIME R (Cont’d)

10.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the c ounter and the a lternate counter.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE

Timer Overflow Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is enabled w henever the TOF

bit of the SR register is set.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the O C2E bit is set and even if there is no successful compari so n.

Bit 3 = FOLV1

Forced Output Compare 1.

This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bi t is set and e ven if there i s no successful comparison.

Bit 2 = OLVL2

Output Level 2.

This bit is copied to the OCMP2 pin wh enever a successful co mpa ri so n o ccurs with the OC2R reg ister and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 1 = IEDG1

Input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bi t is copied t o t he O CMP 1 pin whenever a successful comparison occurs with the OC1R register and the O C1E bit is set in the CR2 register.

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

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16-B IT TIME R (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternat e function di sabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternat e function di sabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled. Note: This bit is not available in Timer A. It must

be kept at its reset value.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is g iven by t he IEDG1 bit. Th e length of the generated pulse depends on the contents of the OC1R register.

Bit 4 = PWM

Pulse Width Modulation.

0: PWM mode is not active. 1: PWM mode is active, the OCMP 1 pin outpu ts a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Bit 3, 2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 15. Clock Control Bits

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines which type of level transition on the external clock pin EX TCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 E XEDG

Timer Clock CC1 CC 0

CPU

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

External Clock (where

available)

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16-B IT TIME R (Cont’d) CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh)

Bit 7 = ICF 1

Input Capture Flag 1.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reache d the OC2R value in PWM mode. To clear this bit, first read the S R register, then read or write the lo w byte of the IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R register. To clear this bit, first read t he SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Note: This bit is not available in Timer A and is forced by hardware to 0.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC2R reg ister. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Note: This bit is not available in Timer A and is forced by hardware to 0.

Bit 2 = TIMD

Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler an d counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allow ing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

ICF1 OCF1 TOF ICF2 O CF2 TIMD 0 0

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16-B IT TIME R (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by th e input capture 1 event).

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit re gister that contains t he hi gh pa rt of the value to be compared to the CHR register.

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

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16-B IT TIME R (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit regi ster that cont ains the high part of the value to be compared to the CHR register.

Note: This register is write-only in Timer A.

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

Note: This register is write-only in Timer A.

COUNTER HIGH REGISTER (CHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit regi ster that cont ains the high part of the counter value.

COUNTER LOW REGISTER (CLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister that contains t he hi gh pa rt of the counter value.

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does no t clear the TOF bit in the CSR register.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by t he Input Capture 2 event).

Note: This register is not implemented in Timer A.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

Note: This register is not implemented in Timer A.

MSB LSB

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16-B IT TIME R (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values

These bits are not used in Timer A and must be kept cleared.

These bits are forced by hardware to 0 in Timer A

Address

(Hex.)

Label

76543210

Timer A: 32 Timer B: 42

CR1

Reset Value

ICIE

OCIE

TOIE0FOLV2

FOLV10OLVL2

IEDG10OLVL1

Timer A: 31 Timer B: 41

CR2

Reset Value

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Timer A: 33 Timer B: 43

CSR

Reset Value

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Timer A: 34 Timer B: 44

IC1HR

Reset Value

MSB

xxxxxxx

LSB

Timer A: 35 Timer B: 45

IC1LR

Reset Value

MSB

xxxxxxx

LSB

Timer A: 36 Timer B: 46

OC1HR

Reset Value

MSB

1000000

LSB

Timer A: 37 Timer B: 47

OC1LR

Reset Value

MSB

0000000

LSB

Timer B: 4E

OC2HR

Reset Value

MSB

1000000

LSB

Timer B: 4F

OC2LR

Reset Value

MSB

0000000

LSB

Timer A: 38 Timer B: 48

CHR

Reset Value

MSB

1111111

LSB

Timer A: 39 Timer B: 49

CLR

Reset Value

MSB

1111110

LSB

Timer A: 3A Timer B: 4A

ACHR

Reset Value

MSB

1111111

LSB

Timer A: 3B Timer B: 4B

ACLR

Reset Value

MSB

1111110

LSB

Timer B: 4C

IC2HR

Reset Value

MSB

xxxxxxx

LSB

Timer B: 4D

IC2LR

Reset Value

MSB

xxxxxxx

LSB

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10.4 SERI AL PER IPHERAL INTERFACE ( SPI)

10.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may cons ist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system.

10.4.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

■ Six master mode frequencies (f

CPU

/4 max.)

■ f

CPU

/2 max. slave mode frequency

■ SS Management by software or hardware

■ Programmable clock polarity and phas e

■ End of transfer interrupt flag

■ Write co llision, Master Mo de Fault and Ove r run

flags

10.4.3 General Description

Figure 47 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connec ted to ext ernal devices th rough 3 pins:

– MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI mas ters and in-

put by SPI slaves

–SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS

inputs can be driven by stand-

ard I/O ports on the master MCU.

Figure 47. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE SPE

MSTR

CPHA SPR0SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL MODF 0OVR SSISSMSOD

SOD

bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 48.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re-

sponds by sending da ta to the master device via the MISO pin. This implies full duplex communication with both data out an d data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communicati on is possib le).

Four possible data/clock timin g relationships may be chosen (see Figure 51) b ut master and slave must be programmed with the same timing mode.

Figure 48. Single Master/ Single Slave Application

8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

8-BIT SHIFT REGISTE R

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit LS Bit MSBit LSBit

Not used if SS is managed by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.2 Slave Select Management

As an alternative to using the SS

pin to control the Slave Select signal, the appli cation c an choose to manage the Slave Select signal by softwa re. This is configured by the SSM bit in the S P ICSR register (see Figure 50)

In software management, the external SS

pin is free for other application uses and t he i nternal S S signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Fi gure 49):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire transmission. T his im plies t hat in s in gle s lave applications the SS

pin either can be t ied to

, or made free for standard I/O by manag-

ing the S S

function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 10.4.5.3).

Figure 49. Generic SS

Timing Dia gram

Figure 50. Hardware/Software Slave Select Management

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2

Byte 3

SS internal

SSM bit

SSI bit

external pin

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The c lock f requency, polarity an d phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

To operate the SPI in master mode, perform the following two steps in order (if t he SPICSR register is not written first, the SPICR register setting may be not taken into account):

1. Write to the SPICSR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock pola rity and clock pha se by

configuring the CP OL a nd CP HA b its. Fig ure

51 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

– Either set the SSM bit and s et the SSI bit or

clear the SSM bit and tie the SS

pin high for

the complete byte transmit sequence.

2. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MST R and SPE bits remain set onl y if SS

is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

10.4.3.4 Master Mode Transmit Sequen ce

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the C CR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is rea d.

10.4.3.5 Slave Mode Operation

In slave mode, the s erial clock is received on t he SCK pin from the master device.

To operate the SPI in slave mode:

1. W rite to the SPI CSR register to perform the f ollowing actions:

– Select the clock po larity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 51).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS

pin as described in Section

10.4.3.2 and Figure 49. If C PHA=1 SS

must

be held low continuously. If CPHA=0 SS

must be held low during byte transmission and pulled up between each b yte to let the slave write in the shift register.

2. W rite to the SP ICR register t o clear the M STR bit and set the SPE bit to enable the SPI I/O functions.

10.4.3.6 Slave Mode Transmit Seq uence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives th e clock si g n al and the most significant bit of the data on its MOSI pin.

When dat a transf er is comp lete:

– The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While th e SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it m ust be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 10.4.5.2).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be cho sen by software, using the CPOL an d CPHA bits (Se e

Figure 51).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge

Figure 51, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MIS O pin, the MOSI pin are direct ly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI m ust be disabled by resetting the SPE bit.

Figure 51. Dat a C lo ck Ti m in g D i agram

SCK

MSB it Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 L SBit

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 L SBit

MISO

(from maste r)

MOSI

(from slav e )

(to slave)

CAPTURE STROBE

CPHA =1

MSB it Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBi t

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from m aster)

MOSI

(to slave)

CAPTUR E STROB E

CPHA =0

Note:

This figure should n ot be used as a re plac ement for param etric information.

Refer to the E lectrical Characteristics chapter.

(from slav e )

(CPOL = 1) SCK

(CPOL = 0)

SCK (CPOL = 1)

SCK (CPOL = 0)

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS

pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI peri pheral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read ac cess to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS

pin must be pulled high during the MODF bit clearing sequenc e. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs, when the master device has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs: – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains t he byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the softwa re tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 10.4.3.2 Slave Select

Management.

Note: a "read collision" will never occur since the received data b yte is placed i n a buffer in which access is always synchronous with the MCU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 52).

Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPICSR

Read SPIDR

2nd Step

SPIF =0 WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

RESULT

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5.4 Single Master Systems

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 53).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS

pins of the slave devices.

The SS

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO l ine the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or dat a bytes with co mmand fields.

Figure 53. Single Master / Multiple Slave Configuration

MISO

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS SS

SCK SCK

SCK

Ports

Slave MCU

Slave

MCU

Slave MCU

Master MCU

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.6 Low Power Mo des

10.4.6.1 Using the SPI to wakeup the MCU from Halt mode

In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SP IF interrupt. The data received i s subsequently rea d from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before sof tware clears the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mo de, if the SPI remains in Slave mode, it is recommended to perform an extra communications cy cle to bring the SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake up t he S T7 from Halt mode only if the S lave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section

10.4.3.2), make sure the master drives a low level

on the SS

pin when the slave enters Halt mode.

10.4.7 Interrupts

Note: The SPI interrupt ev ents are connected to

the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the in terrupt m ask in the CC register is reset (RIM instruction).

Mode Description

WAIT

No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode.

HALT

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

SPI End of Transfer Event

SPIF

SPIE

Yes Yes

Master Mode Fault Event

MODF Yes No

Overrun Error OVR Yes No

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.8 Register Description CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE

Serial Peripheral Interrupt Enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR register

Bit 6 = SPE

Serial Peripheral Output Enable.

This bit is set and cl eared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.4.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the exte rnal pins . 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2

Divider Enable

. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 17 SPI Mast er

mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR

Master Mode.

This bit is set and cl eared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 10.4.5.1 Master Mode Fault

(MODF)).

0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL

Clock Polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI m ust be disabled by resetting the SPE bit.

Bit 2 = CPHA

Clock Phase.

This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0]

Serial Clock Frequency.

These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode.

No te : These 2 bits have no effect in slave mode. Table 1 7. S PI Ma ster mode S C K Frequency

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Serial Clock SPR2 SPR1 SPR0

CPU

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

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SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a t ransfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is rea d.

Bit 6 = WCOL

Write Collision status (Read only).

This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 52).

0: No write collision occurred 1: A write collision has been detected

Bit 5 = OVR S

PI Overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is ready to b e transferred into the SPIDR register while SPIF = 1 (See Section 10.4.5.2). An interrupt is generated if SPIE = 1 in SPICSR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected

Bit 4 = MO DF

Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see Sect ion 10.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD

SPI Output Disable.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled

Bit 1 = SSM

SS Management .

This bit is set and cleared by software. When set, it disables the alternate func tion of the SPI SS

and uses the SSI bit value instead. See Section

10.4.3.2 Slave Select Management.

0: Hardware management (SS

managed by exter-

nal pin)

1: Software management (internal SS

signal con-

trolled by SSI bit. External SS

pin free for gener-

al-purpose I/O)

Bit 0 = SSI

SS Internal Mode.

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS

slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write Reset Value: Undefined

The SPIDR register is used to t ransmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle the SPI F bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register f or t ransmission.

A read to the SPIDR register returns the value located in the buffer and not the co ntent of the shift register (see Figure 47).

SPIF WCOL OVR MODF - SOD SSM SSI

D7 D6 D5 D4 D3 D2 D1 D0

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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 18. SPI Register Map and Reset Values

Address

(Hex.)

Label

76543210

0021h

SPIDR

Reset Value

MSB

xxxxxxx

LSB

0022h

SPICR

Reset Value

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

0023h

SPICSR

Reset Value

SPIF

WCOL

MODF

SOD

SSM

SSI

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10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring a n industr y stand ard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

10.5.2 Main Features

■ Full duplex, asynchronous communi ca tions

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

■ Independently programmable transmit and

receive baud rates up to 500K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB) – Idle line

■ Muting function for multiprocessor configurations

■ Separate enable bits for Transmitter and

Receiver

■ Four error detection flags:

– Overrun error – Noise error – Frame error – Parity error

■ Five interrupt sources with flags:

– Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

■ Parity control:

– Transmits parity bit – Checks parity of received data byte

■ Reduced power consumption mode

10.5.3 General Description

The interface is externally connected to another device by two pins (see Figure 55):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

– An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: – A convent iona l type for commonly-use d baud

rates,

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 54. SCI Block Diagram

WAKE

UNIT

RECEIVER

CONTROL

TRANSMIT

CONTROL

TDRE TC RDRFIDLE OR NF FE PE

SCI

CONTROL

INTERRUPT

CR1

R8 T8 SCID M WAKE PCE PS PIE

Received Data Register (RDR)

Received Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER) DR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

RECEIVER RA T E

TRANSMITTER RATE

BRR

SCP1

CPU

CONTR O L

CONTROL

SCP0 SC T2

SCT1SCT0SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

SBKRWURETEILIERIETCIETIE

CR2

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4 Functional Description

The block diagram of the Serial Control Inte rface, is shown in F igure 54. It contains 6 dedicated reg- isters:

– Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) – An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

10.5.7for the definitions of each bit.

10.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming t he M bit in the SCICR1 register (see Figure 54).

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an en tire frame

of “1”s followed by the start bit of the n ext frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the trans mitter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

Figure 55. Word Length Programming

Bit0 Bit1

Bit2

Bit3 Bit4

Bit5 Bit6

Bit7 Bit8

Start

Bit

Stop

Bit

Next Start

Bit

Idle Frame

Bit0 Bit1

Bit2

Bit3 Bit4 Bit5

Bit6

Bit7

Start

Bit

Stop

Bit

Start

Bit

Start

Bit

Idle Frame

Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame

Start

Bit

Extra

’1’

Data Frame

Break Frame

Start

Bit

Extra

’1’

Data Frame

Next Data Frame

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit s tatus. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shif ts out least significant bit first on the TDO pin. In this m ode, the SCIDR register consists of a buffer (TDR ) between the internal bus and the transmit shift register (see Figure 54).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in t he SCI DR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR regi ster stores the dat a in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is ta king place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame t ransmission is com plete (after t he stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. Th e break frame length de pends on the M bit (see Figur e 55).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI t o send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

Note: Resetting an d s etti ng the TE bit caus es t he data in the TDR register to b e lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bi t is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 54).

Procedure

– Select the M bit to define the word length. – Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception. Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register. The RDRF bit must be cleared before the end of t he

reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SPI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Er ror

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared.

When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating betwee n valid i ncomi ng data and noise.

When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself generates an interrupt.

The NF bit is reset by a SCISR register read operation followed by a SCIDR register read operation.

Framing E rror

A framing error is detected when: – The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the

SCIDR register. – No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt. The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 56. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER

RECEIVER

SCIETPR

SCIERPR

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

EXTENDED PRESCALER

CLOCK

RECEI V ER RA T E

TRANSMITTER RATE

SCIBRR

SCP1

CPU

CONTROL

SCP0

SCT2

SCT1SCT0SCR2 SCR1SCR0

/PR

/16

CONVENT IONAL BAUD RATE GE NERATOR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED TRANSMITTER PRESCAL ER REGISTER

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver a nd t ransmi tter (Rx and Tx) are set inde pendently and calculated as follo ws:

with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If f

CPU

is 8 M Hz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.

10.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Gen erator retains industry standard software compatibility.

The extended baud rat e generator block di agram is described in the Figure 56.

The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.

Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. T he baud rates are cal c ulated as follows:

with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register)

10.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desirable that only the intended message recipient should actively recei ve th e f ull me ssag e c ontent s, thus reducing redundant SCI service overhead for all non addressed receivers.

The non addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU b it by software puts the SCI in sleep mode:

All the reception status bits can not be set. All the receive interrupts are inhibited. A muted receiver may be awakened by on e of the

following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RW U bit and sets the RDRF bit, which allows the receiver t o receiv e thi s word normally and to use it as an address word.

Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) b efore the write operation, the RW U bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.

Tx =

(16

PR)*TR

CPU

Rx =

(16

PR)*RR

CPU

Tx =

ETPR*(PR* TR)

CPU

Rx =

ERPR*(PR*RR)

CPU

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.7 Parity Control

Parity control (generation of parity bit in trasmission and and parity chencking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 19.

Table 19. Frame Formats

Legend : SB = Start Bit , STB = Sto p Bit,

PB = Pa rity Bi t Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not the parity bit

Even p arity: the p arity bit is calculated to ob tain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on w hether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).

Odd pa rity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.

10.5.5 Low Power Modes

10.5.6 Interrupts

The SCI interrupt events are connected to the same interrupt vecto r .

These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB |

Mode Description

WAIT

No effect on SCI. SCI interrupts cause the device to exit

from Wait mode.

HALT

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

Transmit Data Register Empty

TDRE TIE Yes No

Transmission Complete

TC TCIE Yes No

Received Data Ready to be Read

RDRF

RIE

Yes No

Overrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No Parity Error PE PIE Yes No

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.7 Register Description STATUS REGISTER (SCISR)

Read Only Reset Value: 1100 0000 (C0h)

Bit 7 = T DRE

Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared b y a s oftw are sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register

Note: Data will not be transferred to t he shift register unless the TDRE bit is cleared.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a frame containing Data , a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by a sof tware sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Bit 5 = R DRF

Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred to the S CIDR register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read

Bit 4 = IDL E

Idle line detect.

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a sof tware sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected

Note: T he IDLE bit will not be set again unt il the RDRF bit has been set itself (i.e. a new idle line occurs).

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently being received in t he shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error is detected

Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchronization, excessive noise or a b reak character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Framing error is detected 1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be s et.

Bit 0 = PE

Parity error.

This bit is set by hardware when a parity error occurs in receiver mode . It is cleared by a software sequence (a read to the status register followed by an access to the SCI DR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error

TDRE TC RDRF IDLE OR NF FE PE

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1)

Read/Write Reset Value: x000 0000 (x0h)

Bit 7 = R8

Receive data bit 8.

This bit is used to store the 9th bit of th e recei ve d word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store t he 9 th b it of the transm itted word when M=1.

Bit 5 = SCID

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled

Bit 4 = M

Word length.

This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark

Bit 2 = PCE

Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity c ontrol is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. On ce it is set, PCE is act ive after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled

Bit 1 = PS

Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by s oftware. The parity will be selected after the current byte. 0: Even parity 1: Odd parity

Bit 0 = PIE

Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control w hen a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled.

R8 T8 SCID M WAKE PCE PS PIE

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7 = TIE

Transmitter interrupt enable

. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE

Receiver interrupt enable

. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled

Notes: – During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line) after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).

Bit 2 = RE

Receiver enable.

This bit enables the rec eiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU

Receiver wake-up.

This bit determi nes if the SCI is in m ute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wakeup by idle line detection.

Bit 0 = SBK

Send break.

This bit set is used to send break cha racters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word.

TIE TCIE RIE ILIE TE RE RWU

SBK

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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR)

Read/Write Reset Value: Undefined Contains the Received or Transmitted data char-

acter, depending on whether it is read from or written to.

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (T DR) and one for recep tion (RDR). The TDR register provides the parallel interface between the internal b us and the output shift register (see Figure 54). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 54).

BAUD RATE REGISTER (SCIBRR)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7 :6= SCP[1:0]

First SCI Presca ler

These 2 prescaling bits allow several standard clock division ranges:

Bits 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.

Bits 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conj unction with t he S CP [ 1:0] bits define the total division applied to the bus cloc k to yield the receive rate clock in convention al Baud Rate Generator mode.

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

PR Prescaling factor SCP1 SCP0

100 301 410

13 1 1

TR dividing factor SCT2 SCT1 SCT0

1000 2001 4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

RR Dividing factor SCR2 SCR1 SCR0

1000

2001

4010

8011 16 1 0 0 32 1 0 1 64 1 1 0

128 1 1 1

Datasheet ST72F324K6T6, ST72F324K6, ST72F324K2, ST72F324J6T6, ST72F324J6 Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

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