SGS Thomson Microelectronics ST72E511R9G0S, ST72E5111R9G0 Datasheet

Rev. 1.5

September 1999 1/159

This ispreliminary information on anew product in development or undergoing evaluation. Details are subject tochange without notice.

ST72311R, ST72511R,

ST72512R, ST72532R

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,

16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

PRELIMINARY DATA

■ 16K to 60K Program memory

(ROM/OTP/EPROM) with read-out protection

■ EEPROM Datamemory (only on ST72532R4)

■ Master Reset and Power-on Reset

■ Low voltage supply supervisor

■ Low consumption resonator oscillator and by-

pass for external clock source

■ 4 Power saving modes

■ Nested interrupt controller

■ NMI dedicated non maskable interrupt pin

■ 48 multifunctional bidirectional I/O lines with:

– External interrupt capability (4 vectors) – 32 alternate function lines – 12 high sink outputs

■ Real time base, Beep and Clock-out capabilities

■ Configurable watchdog reset

■ Two 16-bit timers with:

– 2 input captures – 2 output compares – External clock input on one timer – PWM and Pulse generator modes

■ 8-bit PWM Auto-reload timer

(except on ST72512R4, ST72532R4) with: – 4 independent output channels

– Output compare and time base interrupt – External clock with event detector

■ SPI synchronous serial interface

■ SCI asynchronous serial interface

■ CAN interface (except on ST72311Rx)

■ 8-bit ADC with 8 input pins

■ 8-bit data manipulation

■ 63 basic instructions

■ 17 main addressing modes

■ 8 x 8 unsigned multiply instruction

■ Truebit manipulation

■ Full hardware/software development package

Device Summary

Note 1. See Section 7.3.1 on page 130 for more information on VDDversus f

OSC

TQFP64

14 x 14

Features ST72511R9 ST72511R7 ST72511R6 ST72311R9 ST72311R7 ST72311R6 ST72512R4 ST72532R4

Program memory - bytes 60K 48K 32K 60K 48K 32K 16K 16K RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256) 1024 (256) EEPROM - bytes - - - ----256

Peripherals

Watchdog, 16-bit Timers, 8-bit PWM

ART, SPI,SCI, CAN, ADC

Watchdog, 16-bit Timers, 8-bit PWM

ART, SPI, SCI, ADC

Watchdog, 16-bit Timers,

SPI, SCI, CAN, ADC

Operating Supply 3.0V to 5.5V 3.0 to 5.5V

CPU Frequency 2 to 8 MHz (with 4 to 16 MHz oscillator) 2 to 4 MHz

Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional) Packages TQFP64

Table of Contents

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1 GENERAL DESCRIPTION . . . . . . ................................................ 6

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 6

1.2 PIN DESCRIPTION . . ..................................................... 7

1.3 REGISTER & MEMORY MAP . . . ...........................................10

1.4 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . .................... 14

1.5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 15

1.5.1 Introduction . . . . . . . . . . . . ...........................................15

1.5.2 Main Features . . . . . . . . . . ...........................................15

1.5.3 Memory Access . . . . . . . . . . . . . . . . . . ................................. 16

1.5.4 Data EEPROM and Power Saving Modes . . . . . . . . . . . . . . . . . . . . ...........17

1.5.5 Data EEPROM Access Error Handling . ................................. 17

1.5.6 Register Description . . . . . ...........................................18

2 CENTRAL PROCESSING UNIT . . ............................................... 19

2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................19

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 19

2.3 CPU REGISTERS . . . .................................................... 19

3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . ................................22

3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . ........................... 23

3.2 RESET MANAGER . . ....................................................24

3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . .. . . . . . ............28

3.4 MAIN CLOCK CONTROLLER (MCC) . . . . ....................................29

4 INTERRUPTS & POWER SAVING MODES . . . . . . . ................................. 31

4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Introduction . . . . . . . . . . . . ...........................................31

4.1.2 Interrupt Masking and Processing Flow . . . . . . . . . . . . . . . . . . . . . . ...........31

4.1.3 Interrupts and Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.4 Concurrent and Nested Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.5 Interrupt Register Descriptions . . . . ....................................34

4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 37

4.2.1 Introduction . . . . . . . . . . . . ...........................................37

4.2.2 HALT Modes . . . . . . . . . . . ...........................................37

4.2.3 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . .................................39

4.2.4 SLOW Mode . . .. . . . . . . . . . . . . . . . . . ................................. 39

5 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 40

5.1 I/O PORTS . . . . . . . . . . . . . . . . . . ........................................... 40

5.1.1 Introduction . . . . . . . . . . . . ...........................................40

5.1.2 Functional Description . . .. . . ........................................ 40

5.1.3 I/O Port Implementation . . . . . . . . . ....................................42

5.1.4 Register Description . . . . . ...........................................43

5.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . 45

5.2.2 I/O Port Alternate Functions . . . . . . . . . ................................. 45

5.2.3 Miscellaneous Registers Description . . . . . . . . ........................... 46

5.3 WATCHDOG TIMER (WDG) . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . 49

5.3.1 Introduction . . . . . . . . . . . . ...........................................49

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5.3.2 Main Features . . . . . . . . . . ...........................................49

5.3.3 Functional Description . . .. . . ........................................ 49

5.3.4 Hardware Watchdog Option . . . . . . ....................................50

5.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 50

5.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 50

5.3.7 Register Description . . . . . ...........................................50

5.4 PWM AUTO-RELOAD TIMER (ART) . . . . . ....................................52

5.4.1 Introduction . . . . . . . . . . . . ...........................................52

5.4.2 Functional Description . . .. . . ........................................ 53

5.4.3 Register Description . . . . . ...........................................56

5.5 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................59

5.5.1 Introduction . . . . . . . . . . . . ...........................................59

5.5.2 Main Features . . . . . . . . . . ...........................................59

5.5.3 Functional Description . . .. . . ........................................ 59

5.5.4 Low Power Modes . . . . . . . . . . . . . . . . ................................. 70

5.5.5 Interrupts . . . . . . . . . ...............................................70

5.5.6 Register Description . . . . . ...........................................71

5.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . ...........76

5.6.1 Introduction . . . . . . . . . . . . ...........................................76

5.6.2 Main Features . . . . . . . . . . ...........................................76

5.6.3 General description . . . . . . ........................................... 76

5.6.4 Functional Description . . .. . . ........................................ 78

5.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 85

5.6.6 Interrupts . . . . . . . . . ...............................................85

5.6.7 Register Description . . . . . ...........................................86

5.7 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.7.1 Introduction . . . . . . . . . . . . ...........................................89

5.7.2 Main Features . . . . . . . . . . ...........................................89

5.7.3 General Description . . . . . . . . . . . . . . . . . . .............................. 89

5.7.4 Functional Description . . .. . . ........................................ 91

5.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 96

5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 96

5.7.7 Register Description . . . . . ...........................................97

5.8 CONTROLLER AREA NETWORK (CAN) . . . . ................................ 101

5.8.1 Introduction . . . . . . . . . . . . ..........................................101

5.8.2 Main Features . . . . . . . . . . ..........................................102

5.8.3 Functional Description . . .. . . ....................................... 102

5.8.4 Register Description . . . . . ..........................................108

5.9 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . .......................... 118

5.9.1 Introduction . . . . . . . . . . . . ..........................................118

5.9.2 Main Features . . . . . . . . . . ..........................................118

5.9.3 Functional Description . . .. . . ....................................... 118

5.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 119

5.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 119

5.9.6 Register Description . . . . . ..........................................120

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . .......................................122

6.1 ST7 ADDRESSING MODES . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.1 Inherent . . . ...................................................... 123

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6.1.2 Immediate . . . . . .. . . . . . . . . . .......................................123

6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . ................................123

6.1.4 Indexed (No Offset, Short, Long) . . ................................... 123

6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.1.6 Indirect Indexed (Short, Long) . . . . . . . ................................124

6.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . .............. 124

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . ................................ 125

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . ............................. 128

7.1 PARAMETER CONDITIONS . . . . . . . . . . . ................................... 128

7.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........128

7.1.2 Typical values . . . . . . .............................................. 128

7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . ................................ 128

7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.2 ABSOLUTE MAXIMUM RATINGS . . . .......................................129

7.2.1 Voltage Characteristics .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 129

7.2.2 Current Characteristics . . ..........................................129

7.2.3 Thermal Characteristics . . . . . . . . . . . ................................. 129

7.3 OPERATING CONDITIONS . .............................................. 130

7.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........130

7.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . .. . . . . . . . . . 131

7.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . .............. 132

7.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . .............................132

7.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . .......................... 133

7.4.3 HALT and ACTIVE-HALT Modes . . . . ................................ 134

7.4.4 Supply and Clock Managers . . ....................................... 134

7.4.5 On-Chip Peripheral ............................................... 134

7.5 CLOCK AND TIMING CHARACTERISTICS . . . . . ............................. 135

7.5.1 General Timings . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.2 External Clock Source . . . . . . . . . . . . . . . . ............................. 135

7.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . ..........135

7.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . .............. 136

7.6.2 EEPROM Data Memory . . . .. . . . . . . ................................. 136

7.6.3 EPROM Program Memory .......................................... 136

7.7 ESD PIN PROTECTION STRATEGY . . . . . . . ................................ 137

7.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . ................... 139

7.8.1 General Characteristics . . . . . . . . . . . . . ...............................139

7.8.2 Output Driving Current . . .. . . . . . . . . . ................................ 140

7.9 CONTROL PIN CHARACTERISTICS .......................................141

7.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.9.2 VPP Pin . . . . . . . . . . .............................................. 141

7.10TIMER PERIPHERAL CHARACTERISTICS . . ................................ 142

7.10.1 Watchdog Timer . . . . . . . ..........................................142

7.10.2 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . ................... 142

7.10.3 16-Bit Timer ..................................................... 142

7.11COMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . ..........143

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7.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.11.2 I2C- Inter IC Control Interface .......................................145

7.11.3 SCI - Serial Comunication Interface ................................... 146

7.11.4 CAN - Controller Area Network Interface . . . ............................ 146

7.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . .......................... 147

8 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . ............................. 149

8.1 PACKAGE MECHANICAL DATA . . . . . . .. . . . . . . . . . .......................... 149

8.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

8.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . .......... 151

8.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

8.4.1 User-supplied TQFP64 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

9 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . ................... 153

9.1 OPTION BYTES . . ...................................................... 153

9.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 154

9.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 156

10 ST7 GENERIC APPLICATION NOTE . . . ....................................... 157

11 SUMMARY OF CHANGES ...................................................158

ST72311R, ST72511R, ST72512R, ST72532R

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72311R, ST72511R, ST72512R and ST72532R devices are members of the ST7 microcontroller family. They can be grouped as follows:

– ST725xxR devices are designed for mid-range

applications witha CANbusinterface (Controller Area Network)

– ST72311R devices target the same rangeof ap-

plications but without CAN interface.

All devices are based on a common industrystandard 8-bit core, featuringan enhanced instruction set.

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibilityto software developers, enabling the design ofhighly efficient andcompact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

CONTROL

PROGRAM

(16K - 60K Bytes)

RESET

PORT F

PF7:0

(8-BIT)

TIMER A

BEEP

PORT A

RAM

(1024, 2048 Bytes)

PORT C

8-BIT ADC

DDA

SSA

PORT B

PB7:0

(8-BIT)

PWM ART

PORT E

CAN

PE7:0

(8-BIT)

SCI

TIMER B

PA7:0

(8-BIT)

PORT D

PD7:0

(8-BIT)

SPI

PC7:0

(8-BIT)

EEPROM

(256 Bytes)

WATCHDOG

NMI

OSC + MCC

LVD

OSC2

MEMORY

ST72311R, ST72511R, ST72512R, ST72532R

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1.2 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout

DDA

SSA

DD_3

SS_3

MCO / PF0

BEEP / PF1

PF2

OCMP2_A / PF3

OCMP1_A / PF4

ICAP2_A / PF5

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

EI2

EI3

EI0

EI1

PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3

ARTCLK / PB4

PB5 PB6 PB7

AIN0 / PD0 AIN1 / PD1

AIN2 / PD2 AIN3 / PD3

(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7

PA1 PA0 PC7 / SS PC6 / SCK PC5 / MOSI PC4 / MISO PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B

PC0 / OCMP2_B V

SS_0

DD_0

SS_1

DD_1

PA3 PA2

OSC1

OSC2

NMIncRESET

PA7 (HS)

PA6 (HS)

PA5 (HS)

PA4 (HS)

PE3 / CANRX

PE2 / CANTX

PE1 / RDI

PE0 / TDO

ST72311R, ST72511R, ST72512R, ST72532R

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PIN DESCRIPTION (Cont’d) Legend / Abbreviations:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD,

CT= CMOS 0.3VDD/0.7VDDwith input trigger Output level: HS = high sink (on N-buffer only), Port configuration capabilities:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana= analog – Output: OD = open drain, T = true open drain, PP = push-pull

Note: the Reset configuration of each pin is shown in bold. Table 1. Device Pin Description

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate function

TQFP64

Input

Output

Input Output

float

wpu

int

ana

1 PE4 (HS) I/O CTHS X X X X Port E4 2 PE5 (HS) I/O C

HS X X X X Port E5

3 PE6 (HS) I/O C

HS X X X X Port E6

4 PE7 (HS) I/O C

HS X X X X Port E7

5 PB0/PWM3 I/O C

X EI2 X X Port B0 PWM Output 3

6 PB1/PWM2 I/O C

X EI2 X X Port B1 PWM Output 2

7 PB2/PWM1 I/O C

X EI2 X X Port B2 PWM Output 1

8 PB3/PWM0 I/O C

X EI2 X X Port B3 PWM Output 0

9 PB4/ARTCLK I/O C

X EI3 X X Port B4 PWM-ART External Clock

10 PB5 I/O C

X EI3 X X Port B5

11 PB6 I/O C

X EI3 X X Port B6

12 PB7 I/O C

X EI3 X X Port B7

13 PD0/AIN0 I/O C

X X X X X Port D0 ADC Analog Input 0

14 PD1/AIN1 I/O C

X X X X X Port D1 ADC Analog Input 1

15 PD2/AIN2 I/O C

X X X X X Port D2 ADC Analog Input 2

16 PD3/AIN3 I/O C

X X X X X Port D3 ADC Analog Input 3

17 PD4/AIN4 I/O C

X X X X X Port D4 ADC Analog Input 4

18 PD5/AIN5 I/O C

X X X X X Port D5 ADC Analog Input 5

19 PD6/AIN6 I/O C

X X X X X Port D6 ADC Analog Input 6

20 PD7/AIN7 I/O C

X X X X X Port D7 ADC Analog Input 7

21 V

DDA

S Analog Power Supply Voltage

22 V

SSA

S Analog Ground Voltage

23 V

DD_3

S Digital Main Supply Voltage

24 V

SS_3

S Digital Ground Voltage

25 PF0/MCO I/O C

X EI1 X X Port F0 Main clock output (f

OSC

/2)

26 PF1/BEEP I/O C

X EI1 X X Port F1 Beep signal output

27 PF2 I/O C

X EI1 X X Port F2

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28 PF3/OCMP2_A I/O C

X X X X Port F3 Timer A Output Compare 2

29 PF4/OCMP1_A I/O C

X X X X Port F4 Timer A Output Compare 1

30 PF5/ICAP2_A I/O C

X X X X Port F5 Timer A Input Capture 2

31 PF6 (HS)/ICAP1_A I/O C

HS X X X X Port F6 Timer A Input Capture 1

32 PF7 (HS)/EXTCLK_A I/O C

HS X X X X Port F7 Timer A External Clock Source

33 V

DD_0

S Digital Main Supply Voltage

34 V

SS_0

S Digital Ground Voltage

35 PC0/OCMP2_B I/O C

X X X X Port C0 Timer B Output Compare 2

36 PC1/OCMP1_B I/O C

X X X X Port C1 Timer B Output Compare 1

37 PC2 (HS)/ICAP2_B I/O C

HS X X X X Port C2 Timer B Input Capture 2

38 PC3 (HS)/ICAP1_B I/O C

HS X X X X Port C3 Timer B Input Capture 1

39 PC4/MISO I/O C

X X X X Port C4 SPI Master In / Slave Out Data

40 PC5/MOSI I/O C

X X X X Port C5 SPI Master Out/ Slave In Data

41 PC6/SCK I/O C

X X X X Port C6 SPI Serial Clock

42 PC7/SS I/O C

X X X X Port C7 SPI Slave Select (active low)

43 PA0 I/O C

X EI0 X X Port A0

44 PA1 I/O C

X EI0 X X Port A1

45 PA2 I/O C

X EI0 X X Port A2

46 PA3 I/O C

X EI0 X X Port A3

47 V

DD_1

S Digital Main Supply Voltage

48 V

SS_1

S Digital Ground Voltage

49 PA4 (HS) I/O C

HS X X X X Port A4

50 PA5 (HS) I/O C

HS X X X X Port A5

51 PA6 (HS) I/O C

HS X T Port A6

52 PA7 (HS) I/O C

HS X T Port A7

53 V

Must be tiedlow in user mode. Inprogramming mode when available, this pin acts as the programming voltage input V

. 54 RESET I/O C X X Top priority non maskable interrupt (active low) 55 NC Not Connected 56 NMI I C

X Non maskable interrupt input pin

57 V

SS_3

S Digital Ground Voltage

58 OSC2 I/O

External clock mode input pull-up orcrystal/ceramic resonator oscillator inverter output

59 OSC1 I

External clock input or crystal/ceramic resonator oscillator inverter input

60 V

DD_3

S Digital Main Supply Voltage

61 PE0/TDO I/O C

X X X X Port E0 SCI Transmit Data Out

62 PE1/RDI I/O C

X X X X Port E1 SCI Receive Data In

63 PE2/CANTX I/O C

X Port E2 CAN Transmit Data Output

64 PE3/CANRX I/O C

X X X X Port E3 CAN Receive Data Input

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate function

TQFP64

Input

Output

Input Output

float

wpu

int

ana

ST72311R, ST72511R, ST72512R, ST72532R

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1.3 REGISTER & MEMORY MAP

As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, up to 2Kbytes of RAM, up to 256 bytes of data EEPROM and up to

60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 3. Memory Map

0000h

1024 Bytes RAM

Program Memory

(60K, 48K, 32K, 16K Bytes)

Interrupt & Reset Vectors

HW Registers

0BFFh

0080h

007Fh

0D00h

0FFFh

Reserved

2048 Bytes RAM

(see Table 2)

1000h

FFDFh FFE0h

FFFFh

(see Table 7 on page 35)

0C00h

0CFFh

Optional EEPROM

(256 Bytes)

0880h

Reserved

087Fh

Short Addressing RAM (zero page)

Stack

(256 Bytes)

16-bit Addressing

RAM

0100h

01FFh

047Fh

0080h

0200h

00FFh

or 067Fh or 087Fh

1536 Bytes RAM

16 KBytes

4000h

1000h

48 KBytes

C000h

8000h

32 KBytes

60 KBytes

FFFFh

ST72311R, ST72511R, ST72512R, ST72532R

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Table 2. Hardware Register Map

Address Block

Label

Reset

Status

Remarks

0000h 0001h 0002h

Port A

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

00h

00h 00h

R/W R/W R/W

0003h Reserved Area (1 Byte) 0004h

0005h 0006h

Port C

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register Port C Option Register

00h

00h 00h

R/W R/W R/W

0007h Reserved Area (1 Byte)

0008h 0009h

000Ah

Port B

PBDR PBDDR PBOR

Port B Data Register Port B Data Direction Register Port B Option Register

00h

00h 00h

R/W R/W R/W

000Bh Reserved Area (1 Byte)

000Ch 000Dh 000Eh

Port E

PEDR PEDDR PEOR

Port E Data Register Port E Data Direction Register Port E Option Register

00h

00h 00h

R/W R/W

R/W

000Fh Reserved Area (1 Byte)

0010h 0011h 0012h

Port D

PDDR PDDDR PDOR

Port D Data Register Port D Data Direction Register Port D Option Register

00h

00h 00h

R/W R/W R/W

0013h Reserved Area (1 Byte)

0014h 0015h 0016h

Port F

PFDR PFDDR PFOR

Port F Data Register Port F Data Direction Register Port F Option Register

00h

00h 00h

R/W R/W R/W

0017h

001Fh

Reserved Area (9 Bytes)

0020h MISCR1 Miscellaneous Register 1 00h R/W

0021h 0022h 0023h

SPI

SPIDR SPICR SPISR

SPI Data I/O Register SPI Control Register SPI Status Register

xxh 0xh 00h

R/W R/W Read Only

0024h 0025h 0026h 0027h

ITC

ISPR0 ISPR1 ISPR2 ISPR3

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

FFh FFh FFh FFh

R/W R/W R/W R/W

0028h Reserved Area (1 Byte)

0029h MCC MCCSR Main Clock Control / Status Register 01h R/W

ST72311R, ST72511R, ST72512R, ST72532R

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002Ah 002Bh

WATCHDOG

WDGCR WDGSR

Watchdog Control Register Watchdog Status Register

7Fh

000x 000x

R/W

R/W 002Ch EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

002Dh

0030h

Reserved Area (4 Bytes)

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h

0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

TIMER A

TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

00h 00h

xxh xxh

xxh 80h 00h FFh

FCh FFh FCh

xxh

xxh 80h 00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W

R/W 0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h

004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER B

TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

00h 00h

xxh xxh

xxh 80h 00h

FFh FCh FFh FCh

xxh

xxh 80h 00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

SCI

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register

C0h

xxh

00xx xxxx

xxh 00h 00h

00h

Read Only R/W R/W R/W R/W R/W

R/W

Address Block

Label

Reset

Status

Remarks

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Legend: x=unknown, R/W=read/write Notes:

1. The real valueof I/Oportdata register is readable onlyinoutput configuration. As thereset configuration

of the I/O port is usually input, the associated pin status is read instead of the real register content when the reading at the DR address.

2. The unused bits must always keep the reset value.

0058h 0059h

Reserved Area (2 Bytes)

005Ah 005Bh 005Ch 005Dh 005Eh 005Fh

0060h

006Fh

CAN

CANISR CANICR CANCSR CANBRPR CANBTR CANPSR

CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X

00h 00h 00h 00h 23h 00h

R/W R/W R/W R/W R/W R/W See CAN Description

0070h 0071h

ADC

ADCDR ADCCSR

Data Register Control/Status Register

xxh 00h

Read Only R/W

0072h 0073h 0074h 0075h 0076h

0077h 0078h 0079h

PWM ART

PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR

ARTCSR ARTCAR ARTARR

PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register

00h 00h 00h 00h 00h

00h 00h 00h

R/W R/W R/W R/W R/W

R/W R/W R/W

007Ah

007Fh

Reserved Area (6 Bytes)

Address Block

Label

Reset

Status

Remarks

ST72311R, ST72511R, ST72512R, ST72532R

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1.4 EPROM PROGRAM MEMORY

The programmemory of the OTP and EPROMdevices can be programmed with EPROM programming tools available from STMicroelectronics

EPROM Erasure

EPROM devices are erased by exposure to high intensity UVlightadmitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current.

It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of

sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure.

An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under theselighting conditions. Covering the window also reduces IDDin power-saving modes due to photo-diode leakage currents.

ST72311R, ST72511R, ST72512R, ST72532R

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1.5 DATA EEPROM

1.5.1 Introduction

The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data.Using the EEPROM requires a basic access protocol described in this chapter.

1.5.2 Main Features

■ Up to 16 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained erase and programming cycles

■ Internal control of the global programming cycle

duration

■ End of programming cycle interrupt flag

■ WAIT mode management

Figure 4. EEPROM Block Diagram

EECSR

EEPROM INTERRUPT

FALLING

EDGE

HIGH VOLTAGE

PUMP

IE LAT00000 PGM

EEPROMRESERVED

DETECTOR

EEPROM

MEMORY MATRIX

(1 ROW = 16 x 8 BITS)

ADDRESS

DECODER

DATA

MULTIPLEXER

16 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

128128

ADDRESS BUS

ST72311R, ST72511R, ST72512R, ST72532R

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DATA EEPROM (Cont’d)

1.5.3 Memory Access

The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart inFigure 5 describes these different memory access modes.

Read Operation (LAT=0)

The EEPROM canbe read as a normal ROM location when the LAT bit of the EECSR register is cleared. Ina read cycle, the byte to be accessed is put onthedatabusin less than 1CPUclock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code.

Write Operation (LAT=1)

To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches(up to16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bitis set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by thefalling edge of LAT bit. It is not possible toread the latched data. This note is ilustrated by the Figure 13.

Figure 5. Data EEPROM ProgrammingFlowchart

READ MODE

LAT=0

PGM=0

WRITEMODE

LAT=1

PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 16 BYTES

IN EEPROM AREA

(with the same 12 MSB of the address)

START PROGRAMMING CYCLE

LAT=1

PGM=1 (set by software)

LAT

INTERRUPT GENERATION

IF IE=1 0 1

CLEARED BY HARDWARE

ST72311R, ST72511R, ST72512R, ST72532R

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DATA EEPROM (Cont’d)

1.5.4 Data EEPROM and Power Saving Modes Wait mode

The DATAEEPROMcan enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.

Halt mode

The DATA EEPROM immediatly enters HALT mode if themicrocontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

1.5.5 Data EEPROM Access Error Handling

If a read access occurs while LAT=1, thenthe data bus will not be driven.

If a write access occurs while LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.

Figure 6. Data EEPROM ProgrammingCycle

LAT

ERASE CYCLE WRITE CYCLE

PGM

PROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

INTERNAL PROGRAMMING VOLTAGE

EEPROM INTERRUPT

ST72311R, ST72511R, ST72512R, ST72532R

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DATA EEPROM (Cont’d)

1.5.6 Register Description CONTROL/STATUS REGISTER (CSR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = IE

Interrupt enable

Thisbitissetandclearedbysoftware.Itenables the Data EEPROM interrupt capability when the PGM bit iscleared by hardware. The interrupt request is automatically cleared when thesoftware enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled

Bit 1 = LAT

Latch Access Transfer

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode

Bit 0 = PGM

Programming control and status

This bitisset bysoftwaretobeginthe programming cycle. At the end of theprogramming cycle, this bit is clearedby hardwareand aninterruptisgenerated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress

Note: ifthe PGM bit iscleared duringthe programming cycle, the memory data is not guaranteed.

Table 3. DATA EEPROM Register Map and Reset Values

00000IELATPGM

Address

(Hex.)

Label

76543210

002Ch

EECSR

Reset Value

00000IE0

RWM

PGM

ST72311R, ST72511R, ST72512R, ST72532R

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2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

2.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ 8 MHz CPU internal frequency

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in thememory mapping andare accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y registeris not affectedby the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) andPCH (Program CounterHigh which is the MSB).

Figure 7. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

715 8

PCH

PCL

87 0

RESET VALUE = STACKHIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

RESET VALUE= XXh

X = Undefined Value

ST72311R, ST72511R, ST72512R, ST72532R

20/159

CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result ofthe instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic management bits

Bit 4 = H

Half carry

This bit is set by hardware whena carryoccursbetween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: An half carry hasoccurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7thbit. 0: Theresultof the lastoperation ispositive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. Thisbit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions. Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow hasoccurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt management bits

Bit 5,3 = I1, I0

Interrupt.

The combination of the Iand I0 bits gives the current interrupt software priority.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

11I1HI0NZC

Interrupt SoftwarePriority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

ST72311R, ST72511R, ST72512R, ST72532R

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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is always pointingto the next free location in the stack. It isthen decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits areset) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wrapsin case of anunderflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by meansof the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from thestack.

A subroutine call occupies twolocations and an interrupt five locations in the stack area.

Figure 8. Stack Manipulation Example

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

PCH PCL

PCL

PCH

PCL

PCH

PCL

PCH

PCH PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

ST72311R, ST72511R, ST72512R, ST72532R

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3 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72311R, ST72511R, ST72512R and ST72532R microcontrollersinclude a range ofutility features for securing the application in critical situations (for example in case of a power brownout), and reducing the number of external components. An overview is shown in Figure 9.

Main features

■ Main supply low voltage detection (LVD)

■ RESET Manager

■ Low consumption resonator oscillator

■ Main clock controller (MCC)

Figure 9. Clock, RESET, Option and Supply Management Overview

OSC

MAIN CLOCK

CONTROLLER

(MCC)

LOW VOLTAGE

DETECTOR

(LVD)

CPU

FROM

WATCHDOG

PERIPHERAL

MCC INTERRUPT

MCO

OSC2

OSC1

RESET

OSC

OSCILLATOR

RESET

ST72311R, ST72511R, ST72512R, ST72532R

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3.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDDsupply voltage is below a V

IT-

reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-

referencevalue fora voltage drop is lower

than the V

IT+

referencevalue forpower-on in order to avoid a parasitic reset when theMCUstarts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDDis below:

–V

IT+

when VDDis rising

–V

IT-

when VDDis falling

The LVD function is illustrated in Figure 10. Provided the minimum VDDvalue (guaranteed for

the oscillator frequency) is below V

IT-

, the MCU

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During aLow Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes: The LVDallows the device to be used without any

external RESET circuitry. The LVD is an optional function which can be se-

lected when ordering the device (ordering information).

Figure 10. Low Voltage Detector vs Reset

IT+

RESET

IT-

hys

ST72311R, ST72511R, ST72512R, ST72532R

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3.2 RESET MANAGER

The RESET block includes three RESET sources as shown in Figure 11:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in theST7 memory map.

A 4096 CPUclock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. Reset Block Diagram

CPU

COUNTER

RESET

WATCHDOG RESET

LVD RESET

INTERNAL RESET

ST72311R, ST72511R, ST72512R, ST72532R

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RESET MANAGER (Cont’d) External RESET pin

The RESETpin is both an input andan open-drain output with integrated RONweak pull-up resistor (see Figure11). This pull-up has no fixedvalue but varies in accordance with the input voltage. Itcan be pulled low by external circuitry to reset the device.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized. Two RESET sequences can be associated with this RESET source as shown in Figure 12.

When the RESET is generated by a internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an output that ispulled low.

Generic Power On RESET

The function of the POR circuit consists of waking up the MCU by detecting (at around 2V) a dynamic (rising edge) variation of the VDDSupply. At the beginning of this sequence, the MCU is configured in the RESET state. When the power supply voltage rises toa sufficient level, the oscillator starts to operate, whereupon an internal 4096 CPU cycles delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level forthe chosen frequency (seeElectrical Characteristics) before the reset signal is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (oscillating) VDDsupplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performance.

Figure 12. External RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

h(RSTL)in

IT-

DD nominal

WATCHDOG RESET

DELAY

ST72311R, ST72511R, ST72512R, ST72532R

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RESET MANAGER (Cont’d) Internal Low VoltageDetection RESET (option)

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

- LVD Power-On RESET

- Voltage Drop RESET

In the second sequence, a “delay” phase is used to keep the device in RESET state until VDDrises up to V

IT+

(see Figure 13).

Figure 13. LVD RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

POWER-

RESET PIN

EXTERNAL RESET SOURCE

WATCHDOG RESET

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

DDnominal

WATCHDOG RESET

DELAY

IT+

IT-

DDnominal

IT+

LVD POWER-ON RESET

VOLTAGE DROP RESET

OFF

ST72311R, ST72511R, ST72512R, ST72532R

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RESET MANAGER (Cont’d) Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow has the shortest reset phase (see Figure 14).

Figure 14. Watchdog RESET Sequence

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

IT-

DDnominal

WATCHDOG RESET

WATCHDOG UNDERFLOW

ST72311R, ST72511R, ST72512R, ST72532R

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3.3 LOW CONSUMPTION OSCILLATOR

The main clock of the ST7 can be generated by two differentsources:

■ an external source

■ a crystal or ceramic resonator oscillators

External Clock Source

In this mode, asquare clock signal with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to VDDthrough a R

OBP

resistance (see

Figure 15).

Figure 15. External Clock

Crystal/Ceramic Oscillators

This oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in Figure 16 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time.

This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Figure 16. Crystal/Ceramic Resonator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OBP

OSC1 OSC2

LOAD

CAPACITANCES

ST7

ST72311R, ST72511R, ST72512R, ST72532R

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3.4 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows to manage the power saving modes such as the SLOW and ACTIVE-HALT modes. The whole functionality is managed by the Main Clock Control/Status Register (MCCSR) and the Miscellaneous Register 1 (MISCR1).

The MCC block consists of:

– a programmable CPU clock prescaler – a time base counter with interrupt capability – a clock-out signalto supply external devices

The prescaler allows to select the main clock frequency and is controlled with three bits of the MISCR1: CP1, CP0 and SMS.

The counterallows to generate an interrupt based on a accurate real time clock. Four different time bases depending directly on f

OSC

are available. The wholefunctionality is controlled by four bits of the MCCSR register: TB1, TB0, OIE and OIF.

The clock-out capability allowsto configure a dedicated I/O port pin as an f

OSC

/2 clock out to drive external devices. It is controlled by the MCO bit in the MISCR1 register. When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.

Figure 17. Main Clock Controller (MCC) Block Diagram

DIV 2, 4, 8, 16

MCC INTERRUPT

DIV 2

SMSCP1 CP0

TB1 TB0 OIE OIF

CPU CLOCK

MISCR1

PROGRAMMABLE

DIVIDER

CAN PERIPHERAL

TO CPU AND

PERIPHERALS

OSC

CPU

MCO

PORT

FUNCTION

ALTERNATE

OSC2

OSC1

MCO ----

0000MCCSR

OSCILLATOR

MCC

OSC

ST72311R, ST72511R, ST72512R, ST72532R

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MAIN CLOCK CONTROLLER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1)

See “MISCELLANEOUS REGISTERS” Section.

MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0001 (01h)

Bit 7:4 = Reserved, always read as 0.

Bit 3:2 = TB1-TB0

Time base control

These bits select the programmable divider time base. They are set and cleared by software.

A modification of the time base is taken into account at the end of the current period (previously set) to avoid unwanted time shift. This allows to use this time base as a real time clock.

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt allows to exit from ACTIVE-HALT mode. When this bit is set,calling the ST7 software HALT instruction enters theACTIVE-HALTpower saving mode.

Bit 0 = OIF

Oscillator interrupt flag

This bit is set by hardware andcleared by software reading the CSR register. It indicates when set that the mainoscillator has measured the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached

Warning: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

Table 4. MCC Register Map and Reset Values

0000TB1TB0OIEOIF

Counter

Prescaler

Time Base

TB1 TB0

OSC

=8MHz f

OSC

=16MHz

32000 4ms 2ms 0 0

64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1

Address

(Hex.)

Label

76543210

0029h

MCCSR

Reset Value 0 0 0 0

TB1

TB0

OIE

OIF

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