Datasheet ST72E511R9G0S, ST72E5111R9G0 Datasheet (SGS Thomson Microelectronics)

Rev. 1.5

September 1999 1/159

This ispreliminary information on anew product in development or undergoing evaluation. Details are subject tochange without notice.

ST72311R, ST72511R,

ST72512R, ST72532R

8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,

16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

PRELIMINARY DATA

■ 16K to 60K Program memory

(ROM/OTP/EPROM) with read-out protection

■ EEPROM Datamemory (only on ST72532R4)

■ Master Reset and Power-on Reset

■ Low voltage supply supervisor

■ Low consumption resonator oscillator and by-

pass for external clock source

■ 4 Power saving modes

■ Nested interrupt controller

■ NMI dedicated non maskable interrupt pin

■ 48 multifunctional bidirectional I/O lines with:

– External interrupt capability (4 vectors)
– 32 alternate function lines
– 12 high sink outputs

■ Real time base, Beep and Clock-out capabilities

■ Configurable watchdog reset

■ Two 16-bit timers with:

– 2 input captures
– 2 output compares
– External clock input on one timer
– PWM and Pulse generator modes

■ 8-bit PWM Auto-reload timer

(except on ST72512R4, ST72532R4) with:
– 4 independent output channels

– Output compare and time base interrupt
– External clock with event detector

■ SPI synchronous serial interface

■ SCI asynchronous serial interface

■ CAN interface (except on ST72311Rx)

■ 8-bit ADC with 8 input pins

■ 8-bit data manipulation

■ 63 basic instructions

■ 17 main addressing modes

■ 8 x 8 unsigned multiply instruction

■ Truebit manipulation

■ Full hardware/software development package

Device Summary

Note 1. See Section 7.3.1 on page 130 for more information on VDDversus f

OSC

.

TQFP64

14 x 14

Features ST72511R9 ST72511R7 ST72511R6 ST72311R9 ST72311R7 ST72311R6 ST72512R4 ST72532R4

Program memory - bytes 60K 48K 32K 60K 48K 32K 16K 16K
RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256) 1024 (256)
EEPROM - bytes - - - ----256

Peripherals

Watchdog, 16-bit Timers, 8-bit PWM

ART, SPI,SCI, CAN, ADC

Watchdog, 16-bit Timers, 8-bit PWM

ART, SPI, SCI, ADC

Watchdog, 16-bit Timers,

SPI, SCI, CAN, ADC

Operating Supply 3.0V to 5.5V 3.0 to 5.5V

1)

CPU Frequency 2 to 8 MHz (with 4 to 16 MHz oscillator) 2 to 4 MHz

1)

Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)
Packages TQFP64

1

Table of Contents

159

2/159

2

1 GENERAL DESCRIPTION . . . . . . ................................................ 6

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 6

1.2 PIN DESCRIPTION . . ..................................................... 7

1.3 REGISTER & MEMORY MAP . . . ...........................................10

1.4 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . .................... 14

1.5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 15

1.5.1 Introduction . . . . . . . . . . . . ...........................................15

1.5.2 Main Features . . . . . . . . . . ...........................................15

1.5.3 Memory Access . . . . . . . . . . . . . . . . . . ................................. 16

1.5.4 Data EEPROM and Power Saving Modes . . . . . . . . . . . . . . . . . . . . ...........17

1.5.5 Data EEPROM Access Error Handling . ................................. 17

1.5.6 Register Description . . . . . ...........................................18

2 CENTRAL PROCESSING UNIT . . ............................................... 19

2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................19

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 19

2.3 CPU REGISTERS . . . .................................................... 19

3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . ................................22

3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . ........................... 23

3.2 RESET MANAGER . . ....................................................24

3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . .. . . . . . ............28

3.4 MAIN CLOCK CONTROLLER (MCC) . . . . ....................................29

4 INTERRUPTS & POWER SAVING MODES . . . . . . . ................................. 31

4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Introduction . . . . . . . . . . . . ...........................................31

4.1.2 Interrupt Masking and Processing Flow . . . . . . . . . . . . . . . . . . . . . . ...........31

4.1.3 Interrupts and Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.4 Concurrent and Nested Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.5 Interrupt Register Descriptions . . . . ....................................34

4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 37

4.2.1 Introduction . . . . . . . . . . . . ...........................................37

4.2.2 HALT Modes . . . . . . . . . . . ...........................................37

4.2.3 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . .................................39

4.2.4 SLOW Mode . . .. . . . . . . . . . . . . . . . . . ................................. 39

5 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 40

5.1 I/O PORTS . . . . . . . . . . . . . . . . . . ........................................... 40

5.1.1 Introduction . . . . . . . . . . . . ...........................................40

5.1.2 Functional Description . . .. . . ........................................ 40

5.1.3 I/O Port Implementation . . . . . . . . . ....................................42

5.1.4 Register Description . . . . . ...........................................43

5.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . 45

5.2.2 I/O Port Alternate Functions . . . . . . . . . ................................. 45

5.2.3 Miscellaneous Registers Description . . . . . . . . ........................... 46

5.3 WATCHDOG TIMER (WDG) . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . 49

5.3.1 Introduction . . . . . . . . . . . . ...........................................49

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3

5.3.2 Main Features . . . . . . . . . . ...........................................49

5.3.3 Functional Description . . .. . . ........................................ 49

5.3.4 Hardware Watchdog Option . . . . . . ....................................50

5.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 50

5.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 50

5.3.7 Register Description . . . . . ...........................................50

5.4 PWM AUTO-RELOAD TIMER (ART) . . . . . ....................................52

5.4.1 Introduction . . . . . . . . . . . . ...........................................52

5.4.2 Functional Description . . .. . . ........................................ 53

5.4.3 Register Description . . . . . ...........................................56

5.5 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................59

5.5.1 Introduction . . . . . . . . . . . . ...........................................59

5.5.2 Main Features . . . . . . . . . . ...........................................59

5.5.3 Functional Description . . .. . . ........................................ 59

5.5.4 Low Power Modes . . . . . . . . . . . . . . . . ................................. 70

5.5.5 Interrupts . . . . . . . . . ...............................................70

5.5.6 Register Description . . . . . ...........................................71

5.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . ...........76

5.6.1 Introduction . . . . . . . . . . . . ...........................................76

5.6.2 Main Features . . . . . . . . . . ...........................................76

5.6.3 General description . . . . . . ........................................... 76

5.6.4 Functional Description . . .. . . ........................................ 78

5.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 85

5.6.6 Interrupts . . . . . . . . . ...............................................85

5.6.7 Register Description . . . . . ...........................................86

5.7 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.7.1 Introduction . . . . . . . . . . . . ...........................................89

5.7.2 Main Features . . . . . . . . . . ...........................................89

5.7.3 General Description . . . . . . . . . . . . . . . . . . .............................. 89

5.7.4 Functional Description . . .. . . ........................................ 91

5.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 96

5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 96

5.7.7 Register Description . . . . . ...........................................97

5.8 CONTROLLER AREA NETWORK (CAN) . . . . ................................ 101

5.8.1 Introduction . . . . . . . . . . . . ..........................................101

5.8.2 Main Features . . . . . . . . . . ..........................................102

5.8.3 Functional Description . . .. . . ....................................... 102

5.8.4 Register Description . . . . . ..........................................108

5.9 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . .......................... 118

5.9.1 Introduction . . . . . . . . . . . . ..........................................118

5.9.2 Main Features . . . . . . . . . . ..........................................118

5.9.3 Functional Description . . .. . . ....................................... 118

5.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 119

5.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 119

5.9.6 Register Description . . . . . ..........................................120

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . .......................................122

6.1 ST7 ADDRESSING MODES . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.1 Inherent . . . ...................................................... 123

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6.1.2 Immediate . . . . . .. . . . . . . . . . .......................................123

6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . ................................123

6.1.4 Indexed (No Offset, Short, Long) . . ................................... 123

6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.1.6 Indirect Indexed (Short, Long) . . . . . . . ................................124

6.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . .............. 124

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . ................................ 125

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . ............................. 128

7.1 PARAMETER CONDITIONS . . . . . . . . . . . ................................... 128

7.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........128

7.1.2 Typical values . . . . . . .............................................. 128

7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . ................................ 128

7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.2 ABSOLUTE MAXIMUM RATINGS . . . .......................................129

7.2.1 Voltage Characteristics .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 129

7.2.2 Current Characteristics . . ..........................................129

7.2.3 Thermal Characteristics . . . . . . . . . . . ................................. 129

7.3 OPERATING CONDITIONS . .............................................. 130

7.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........130

7.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . .. . . . . . . . . . 131

7.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . .............. 132

7.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . .............................132

7.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . .......................... 133

7.4.3 HALT and ACTIVE-HALT Modes . . . . ................................ 134

7.4.4 Supply and Clock Managers . . ....................................... 134

7.4.5 On-Chip Peripheral ............................................... 134

7.5 CLOCK AND TIMING CHARACTERISTICS . . . . . ............................. 135

7.5.1 General Timings . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.5.2 External Clock Source . . . . . . . . . . . . . . . . ............................. 135

7.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . ..........135

7.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . .............. 136

7.6.2 EEPROM Data Memory . . . .. . . . . . . ................................. 136

7.6.3 EPROM Program Memory .......................................... 136

7.7 ESD PIN PROTECTION STRATEGY . . . . . . . ................................ 137

7.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . ................... 139

7.8.1 General Characteristics . . . . . . . . . . . . . ...............................139

7.8.2 Output Driving Current . . .. . . . . . . . . . ................................ 140

7.9 CONTROL PIN CHARACTERISTICS .......................................141

7.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.9.2 VPP Pin . . . . . . . . . . .............................................. 141

7.10TIMER PERIPHERAL CHARACTERISTICS . . ................................ 142

7.10.1 Watchdog Timer . . . . . . . ..........................................142

7.10.2 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . ................... 142

7.10.3 16-Bit Timer ..................................................... 142

7.11COMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . ..........143

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7.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.11.2 I2C- Inter IC Control Interface .......................................145

7.11.3 SCI - Serial Comunication Interface ................................... 146

7.11.4 CAN - Controller Area Network Interface . . . ............................ 146

7.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . .......................... 147

8 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . ............................. 149

8.1 PACKAGE MECHANICAL DATA . . . . . . .. . . . . . . . . . .......................... 149

8.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

8.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . .......... 151

8.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

8.4.1 User-supplied TQFP64 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

9 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . ................... 153

9.1 OPTION BYTES . . ...................................................... 153

9.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 154

9.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 156

10 ST7 GENERIC APPLICATION NOTE . . . ....................................... 157

11 SUMMARY OF CHANGES ...................................................158

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72311R, ST72511R, ST72512R and
ST72532R devices are members of the ST7 mi­crocontroller family. They can be grouped as fol­lows:

– ST725xxR devices are designed for mid-range

applications witha CANbusinterface (Controller
Area Network)

– ST72311R devices target the same rangeof ap-

plications but without CAN interface.

All devices are based on a common industry­standard 8-bit core, featuringan enhanced instruc­tion set.

Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibilityto
software developers, enabling the design ofhighly
efficient andcompact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

V

PP

CONTROL

PROGRAM

(16K - 60K Bytes)

V

SS

RESET

PORT F

PF7:0

(8-BIT)

TIMER A

BEEP

PORT A

RAM

(1024, 2048 Bytes)

PORT C

8-BIT ADC

V

DDA

V

SSA

PORT B

PB7:0

(8-BIT)

PWM ART

PORT E

CAN

PE7:0

(8-BIT)

SCI

TIMER B

PA7:0

(8-BIT)

PORT D

PD7:0

(8-BIT)

SPI

PC7:0

(8-BIT)

V

DD

EEPROM

(256 Bytes)

WATCHDOG

NMI

OSC + MCC

LVD

OSC2

MEMORY

4

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1.2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout

V

DDA

V

SSA

V

DD_3

V

SS_3

MCO / PF0

BEEP / PF1

PF2

OCMP2_A / PF3

OCMP1_A / PF4

ICAP2_A / PF5

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

EI2

EI3

EI0

EI1

PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3

ARTCLK / PB4

PB5
PB6
PB7

AIN0 / PD0
AIN1 / PD1

AIN2 / PD2
AIN3 / PD3

(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7

PA1
PA0
PC7 / SS
PC6 / SCK
PC5 / MOSI
PC4 / MISO
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B

PC0 / OCMP2_B
V

SS_0

V

DD_0

V

SS_1

V

DD_1

PA3
PA2

V

DD

_2

OSC1

OSC2

V

SS

_2

NMIncRESET

V

PP

PA7 (HS)

PA6 (HS)

PA5 (HS)

PA4 (HS)

PE3 / CANRX

PE2 / CANTX

PE1 / RDI

PE0 / TDO

5

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PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,

CT= CMOS 0.3VDD/0.7VDDwith input trigger
Output level: HS = high sink (on N-buffer only),
Port configuration capabilities:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana= analog
– Output: OD = open drain, T = true open drain, PP = push-pull

Note: the Reset configuration of each pin is shown in bold.
Table 1. Device Pin Description

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate function

TQFP64

Input

Output

Input Output

float

wpu

int

ana

OD

PP

1 PE4 (HS) I/O CTHS X X X X Port E4
2 PE5 (HS) I/O C

T

HS X X X X Port E5

3 PE6 (HS) I/O C

T

HS X X X X Port E6

4 PE7 (HS) I/O C

T

HS X X X X Port E7

5 PB0/PWM3 I/O C

T

X EI2 X X Port B0 PWM Output 3

6 PB1/PWM2 I/O C

T

X EI2 X X Port B1 PWM Output 2

7 PB2/PWM1 I/O C

T

X EI2 X X Port B2 PWM Output 1

8 PB3/PWM0 I/O C

T

X EI2 X X Port B3 PWM Output 0

9 PB4/ARTCLK I/O C

T

X EI3 X X Port B4 PWM-ART External Clock

10 PB5 I/O C

T

X EI3 X X Port B5

11 PB6 I/O C

T

X EI3 X X Port B6

12 PB7 I/O C

T

X EI3 X X Port B7

13 PD0/AIN0 I/O C

T

X X X X X Port D0 ADC Analog Input 0

14 PD1/AIN1 I/O C

T

X X X X X Port D1 ADC Analog Input 1

15 PD2/AIN2 I/O C

T

X X X X X Port D2 ADC Analog Input 2

16 PD3/AIN3 I/O C

T

X X X X X Port D3 ADC Analog Input 3

17 PD4/AIN4 I/O C

T

X X X X X Port D4 ADC Analog Input 4

18 PD5/AIN5 I/O C

T

X X X X X Port D5 ADC Analog Input 5

19 PD6/AIN6 I/O C

T

X X X X X Port D6 ADC Analog Input 6

20 PD7/AIN7 I/O C

T

X X X X X Port D7 ADC Analog Input 7

21 V

DDA

S Analog Power Supply Voltage

22 V

SSA

S Analog Ground Voltage

23 V

DD_3

S Digital Main Supply Voltage

24 V

SS_3

S Digital Ground Voltage

25 PF0/MCO I/O C

T

X EI1 X X Port F0 Main clock output (f

OSC

/2)

26 PF1/BEEP I/O C

T

X EI1 X X Port F1 Beep signal output

27 PF2 I/O C

T

X EI1 X X Port F2

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28 PF3/OCMP2_A I/O C

T

X X X X Port F3 Timer A Output Compare 2

29 PF4/OCMP1_A I/O C

T

X X X X Port F4 Timer A Output Compare 1

30 PF5/ICAP2_A I/O C

T

X X X X Port F5 Timer A Input Capture 2

31 PF6 (HS)/ICAP1_A I/O C

T

HS X X X X Port F6 Timer A Input Capture 1

32 PF7 (HS)/EXTCLK_A I/O C

T

HS X X X X Port F7 Timer A External Clock Source

33 V

DD_0

S Digital Main Supply Voltage

34 V

SS_0

S Digital Ground Voltage

35 PC0/OCMP2_B I/O C

T

X X X X Port C0 Timer B Output Compare 2

36 PC1/OCMP1_B I/O C

T

X X X X Port C1 Timer B Output Compare 1

37 PC2 (HS)/ICAP2_B I/O C

T

HS X X X X Port C2 Timer B Input Capture 2

38 PC3 (HS)/ICAP1_B I/O C

T

HS X X X X Port C3 Timer B Input Capture 1

39 PC4/MISO I/O C

T

X X X X Port C4 SPI Master In / Slave Out Data

40 PC5/MOSI I/O C

T

X X X X Port C5 SPI Master Out/ Slave In Data

41 PC6/SCK I/O C

T

X X X X Port C6 SPI Serial Clock

42 PC7/SS I/O C

T

X X X X Port C7 SPI Slave Select (active low)

43 PA0 I/O C

T

X EI0 X X Port A0

44 PA1 I/O C

T

X EI0 X X Port A1

45 PA2 I/O C

T

X EI0 X X Port A2

46 PA3 I/O C

T

X EI0 X X Port A3

47 V

DD_1

S Digital Main Supply Voltage

48 V

SS_1

S Digital Ground Voltage

49 PA4 (HS) I/O C

T

HS X X X X Port A4

50 PA5 (HS) I/O C

T

HS X X X X Port A5

51 PA6 (HS) I/O C

T

HS X T Port A6

52 PA7 (HS) I/O C

T

HS X T Port A7

53 V

PP

I

Must be tiedlow in user mode. Inprogramming
mode when available, this pin acts as the pro­gramming voltage input V

PP

.
54 RESET I/O C X X Top priority non maskable interrupt (active low)
55 NC Not Connected
56 NMI I C

T

X Non maskable interrupt input pin

57 V

SS_3

S Digital Ground Voltage

58 OSC2 I/O

External clock mode input pull-up orcrystal/ce­ramic resonator oscillator inverter output

59 OSC1 I

External clock input or crystal/ceramic resona­tor oscillator inverter input

60 V

DD_3

S Digital Main Supply Voltage

61 PE0/TDO I/O C

T

X X X X Port E0 SCI Transmit Data Out

62 PE1/RDI I/O C

T

X X X X Port E1 SCI Receive Data In

63 PE2/CANTX I/O C

T

X Port E2 CAN Transmit Data Output

64 PE3/CANRX I/O C

T

X X X X Port E3 CAN Receive Data Input

Pin n°

Pin Name

Type

Level Port

Main

function

(after

reset)

Alternate function

TQFP64

Input

Output

Input Output

float

wpu

int

ana

OD

PP

ST72311R, ST72511R, ST72512R, ST72532R

10/159

1.3 REGISTER & MEMORY MAP

As shown in the Figure 3, the MCU is capable of
addressing 64K bytes of memories and I/O regis­ters.

The available memory locations consist of 128
bytes of register location, up to 2Kbytes of RAM,
up to 256 bytes of data EEPROM and up to

60Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from
0100h to 01FFh.

The highest address bytes contain the user reset
and interrupt vectors.

Figure 3. Memory Map

0000h

1024 Bytes RAM

Program Memory

(60K, 48K, 32K, 16K Bytes)

Interrupt & Reset Vectors

HW Registers

0BFFh

0080h

007Fh

0D00h

0FFFh

Reserved

2048 Bytes RAM

(see Table 2)

1000h

FFDFh
FFE0h

FFFFh

(see Table 7 on page 35)

0C00h

0CFFh

Optional EEPROM

(256 Bytes)

0880h

Reserved

087Fh

Short Addressing
RAM (zero page)

Stack

(256 Bytes)

16-bit Addressing

RAM

0100h

01FFh

047Fh

0080h

0200h

00FFh

or 067Fh
or 087Fh

1536 Bytes RAM

16 KBytes

4000h

1000h

48 KBytes

C000h

8000h

32 KBytes

60 KBytes

FFFFh

ST72311R, ST72511R, ST72512R, ST72532R

11/159

Table 2. Hardware Register Map

Address Block

Register

Label

Register Name

Reset

Status

Remarks

0000h
0001h
0002h

Port A

PADR
PADDR
PAOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

00h

1)

00h
00h

R/W
R/W
R/W

2)

0003h Reserved Area (1 Byte)
0004h

0005h
0006h

Port C

PCDR
PCDDR
PCOR

Port C Data Register
Port C Data Direction Register
Port C Option Register

00h

1)

00h
00h

R/W
R/W
R/W

0007h Reserved Area (1 Byte)

0008h
0009h

000Ah

Port B

PBDR
PBDDR
PBOR

Port B Data Register
Port B Data Direction Register
Port B Option Register

00h

1)

00h
00h

R/W
R/W
R/W

000Bh Reserved Area (1 Byte)

000Ch
000Dh
000Eh

Port E

PEDR
PEDDR
PEOR

Port E Data Register
Port E Data Direction Register
Port E Option Register

00h

1)

00h
00h

R/W
R/W

2)

R/W

2)

000Fh Reserved Area (1 Byte)

0010h
0011h
0012h

Port D

PDDR
PDDDR
PDOR

Port D Data Register
Port D Data Direction Register
Port D Option Register

00h

1)

00h
00h

R/W
R/W
R/W

0013h Reserved Area (1 Byte)

0014h
0015h
0016h

Port F

PFDR
PFDDR
PFOR

Port F Data Register
Port F Data Direction Register
Port F Option Register

00h

1)

00h
00h

R/W
R/W
R/W

0017h

to

001Fh

Reserved Area (9 Bytes)

0020h MISCR1 Miscellaneous Register 1 00h R/W

0021h
0022h
0023h

SPI

SPIDR
SPICR
SPISR

SPI Data I/O Register
SPI Control Register
SPI Status Register

xxh
0xh
00h

R/W
R/W
Read Only

0024h
0025h
0026h
0027h

ITC

ISPR0
ISPR1
ISPR2
ISPR3

Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3

FFh
FFh
FFh
FFh

R/W
R/W
R/W
R/W

0028h Reserved Area (1 Byte)

0029h MCC MCCSR Main Clock Control / Status Register 01h R/W

ST72311R, ST72511R, ST72512R, ST72532R

12/159

002Ah
002Bh

WATCHDOG

WDGCR
WDGSR

Watchdog Control Register
Watchdog Status Register

7Fh

000x 000x

R/W

R/W
002Ch EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

002Dh

to

0030h

Reserved Area (4 Bytes)

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h

0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh

TIMER A

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

00h
00h

xxh
xxh

xxh
80h
00h
FFh

FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W

R/W
0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h

004Ah
004Bh
004Ch
004Dh
004Eh
004Fh

TIMER B

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

00h
00h

xxh
xxh

xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h

SCI

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register

C0h

xxh

00xx xxxx

xxh
00h
00h

00h

Read Only
R/W
R/W
R/W
R/W
R/W

R/W

Address Block

Register

Label

Register Name

Reset

Status

Remarks

ST72311R, ST72511R, ST72512R, ST72532R

13/159

Legend: x=unknown, R/W=read/write
Notes:

1. The real valueof I/Oportdata register is readable onlyinoutput configuration. As thereset configuration

of the I/O port is usually input, the associated pin status is read instead of the real register content when
the reading at the DR address.

2. The unused bits must always keep the reset value.

0058h
0059h

Reserved Area (2 Bytes)

005Ah
005Bh
005Ch
005Dh
005Eh
005Fh

0060h

to

006Fh

CAN

CANISR
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR

CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address
to
Last address of CAN page X

00h
00h
00h
00h
23h
00h

R/W
R/W
R/W
R/W
R/W
R/W
See CAN
Description

0070h
0071h

ADC

ADCDR
ADCCSR

Data Register
Control/Status Register

xxh
00h

Read Only
R/W

0072h
0073h
0074h
0075h
0076h

0077h
0078h
0079h

PWM ART

PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR

ARTCSR
ARTCAR
ARTARR

PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register

00h
00h
00h
00h
00h

00h
00h
00h

R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W

007Ah

to

007Fh

Reserved Area (6 Bytes)

Address Block

Register

Label

Register Name

Reset

Status

Remarks

ST72311R, ST72511R, ST72512R, ST72532R

14/159

1.4 EPROM PROGRAM MEMORY

The programmemory of the OTP and EPROMde­vices can be programmed with EPROM program­ming tools available from STMicroelectronics

EPROM Erasure

EPROM devices are erased by exposure to high
intensity UVlightadmitted through the transparent
window. This exposure discharges the floating
gate to its initial state through induced photo cur­rent.

It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of

sunlight can be sufficient to cause functional fail­ure. Extended exposure to room level fluorescent
lighting may also cause erasure.

An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under theselighting con­ditions. Covering the window also reduces IDDin
power-saving modes due to photo-diode leakage
currents.

ST72311R, ST72511R, ST72512R, ST72532R

15/159

1.5 DATA EEPROM

1.5.1 Introduction

The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back­up for storing data.Using the EEPROM requires a
basic access protocol described in this chapter.

1.5.2 Main Features

■ Up to 16 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained erase and programming cycles

■ Internal control of the global programming cycle

duration

■ End of programming cycle interrupt flag

■ WAIT mode management

Figure 4. EEPROM Block Diagram

EECSR

EEPROM INTERRUPT

FALLING

EDGE

HIGH VOLTAGE

PUMP

IE LAT00000 PGM

EEPROMRESERVED

DETECTOR

EEPROM

MEMORY MATRIX

(1 ROW = 16 x 8 BITS)

ADDRESS

DECODER

DATA

MULTIPLEXER

16 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

4

4

4

128128

ADDRESS BUS

ST72311R, ST72511R, ST72512R, ST72532R

16/159

DATA EEPROM (Cont’d)

1.5.3 Memory Access

The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP­ROM Control/Status register (EECSR). The flow­chart inFigure 5 describes these different memory
access modes.

Read Operation (LAT=0)

The EEPROM canbe read as a normal ROM loca­tion when the LAT bit of the EECSR register is
cleared. Ina read cycle, the byte to be accessed is
put onthedatabusin less than 1CPUclock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe­cute machine code.

Write Operation (LAT=1)

To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac­cording to its address.

When PGM bit is set by the software, all the previ­ous bytes written in the data latches(up to16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP­ROM write sequence. To avoid wrong program­ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.

At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter­rupt is generated if the IE bitis set. The Data EEP­ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.

Note: Care should be taken during the program­ming cycle. Writing to the same memory location
will over-program the memory (logical AND be­tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by thefalling edge of LAT
bit.
It is not possible toread the latched data.
This note is ilustrated by the Figure 13.

Figure 5. Data EEPROM ProgrammingFlowchart

READ MODE

LAT=0

PGM=0

WRITEMODE

LAT=1

PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 16 BYTES

IN EEPROM AREA

(with the same 12 MSB of the address)

START PROGRAMMING CYCLE

LAT=1

PGM=1 (set by software)

LAT

INTERRUPT GENERATION

IF IE=1 0 1

CLEARED BY HARDWARE

ST72311R, ST72511R, ST72512R, ST72532R

17/159

DATA EEPROM (Cont’d)

1.5.4 Data EEPROM and Power Saving Modes
Wait mode

The DATAEEPROMcan enter WAIT mode on ex­ecution of the WFI instruction of the microcontrol­ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.

Halt mode

The DATA EEPROM immediatly enters HALT
mode if themicrocontroller executes the HALT in­struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.

1.5.5 Data EEPROM Access Error Handling

If a read access occurs while LAT=1, thenthe data
bus will not be driven.

If a write access occurs while LAT=0, then the
data on the bus will not be latched.

If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar­anteed.

Figure 6. Data EEPROM ProgrammingCycle

LAT

ERASE CYCLE WRITE CYCLE

PGM

t

PROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE

EEPROM INTERRUPT

ST72311R, ST72511R, ST72512R, ST72532R

18/159

DATA EEPROM (Cont’d)

1.5.6 Register Description
CONTROL/STATUS REGISTER (CSR)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = IE

Interrupt enable

Thisbitissetandclearedbysoftware.Itenables the
Data EEPROM interrupt capability when the PGM
bit iscleared by hardware. The interrupt request is
automatically cleared when thesoftware enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled

Bit 1 = LAT

Latch Access Transfer

This bit is set by software. It is cleared by hard­ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode

Bit 0 = PGM

Programming control and status

This bitisset bysoftwaretobeginthe programming
cycle. At the end of theprogramming cycle, this bit
is clearedby hardwareand aninterruptisgenerated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress

Note: ifthe PGM bit iscleared duringthe program­ming cycle, the memory data is not guaranteed.

Table 3. DATA EEPROM Register Map and Reset Values

70

00000IELATPGM

Address

(Hex.)

Register

Label

76543210

002Ch

EECSR

Reset Value

00000IE0

RWM

0

PGM

0

ST72311R, ST72511R, ST72512R, ST72532R

19/159

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

2.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ 8 MHz CPU internal frequency

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not
present in thememory mapping andare accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol­lowing instruction refers to the Y register.)

The Y registeris not affectedby the interrupt auto­matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) andPCH
(Program CounterHigh which is the MSB).

Figure 7. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

70

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

70

70

70

0

715 8

PCH

PCL

15

87 0

RESET VALUE = STACKHIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

RESET VALUE = XXh

RESET VALUE= XXh

X = Undefined Value

ST72311R, ST72511R, ST72512R, ST72532R

20/159

CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)

Read/Write
Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in­terrupt masks and four flags representative of the
result ofthe instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Arithmetic management bits

Bit 4 = H

Half carry

.

This bit is set by hardware whena carryoccursbe­tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.

0: No half carry has occurred.
1: An half carry hasoccurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.

Bit 2 = N

Negative

.

This bit is set and cleared by hardware. It is repre­sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re­sult 7thbit.
0: Theresultof the lastoperation ispositive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

Bit 1 = Z

Zero

.

This bit is set and cleared by hardware. Thisbit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.
Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow hasoccurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

Interrupt management bits

Bit 5,3 = I1, I0

Interrupt.

The combination of the Iand I0 bits gives the cur­rent interrupt software priority.

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more
details.

70

11I1HI0NZC

Interrupt SoftwarePriority I1 I0

Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

ST72311R, ST72511R, ST72512R, ST72532R

21/159

CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)

Read/Write
Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al­ways pointingto the next free location in the stack.
It isthen decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).

Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in­struction (RSP), the Stack Pointer contains its re­set value (the SP7 to SP0 bits areset) which is the
stack higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with­out indicating the stack overflow. The previously
stored information is then overwritten and there­fore lost. The stack also wrapsin case of anunder­flow.

The stack is used to save the return address dur­ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by meansof the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from thestack.

A subroutine call occupies twolocations and an in­terrupt five locations in the stack area.

Figure 8. Stack Manipulation Example

15 8

00000001

70

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

SP

Y

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address =

0100h

ST72311R, ST72511R, ST72512R, ST72532R

22/159

3 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72311R, ST72511R, ST72512R and
ST72532R microcontrollersinclude a range ofutil­ity features for securing the application in critical
situations (for example in case of a power brown­out), and reducing the number of external compo­nents. An overview is shown in Figure 9.

Main features

■ Main supply low voltage detection (LVD)

■ RESET Manager

■ Low consumption resonator oscillator

■ Main clock controller (MCC)

Figure 9. Clock, RESET, Option and Supply Management Overview

f

OSC

MAIN CLOCK

CONTROLLER

(MCC)

LOW VOLTAGE

DETECTOR

(LVD)

f

CPU

FROM

WATCHDOG

PERIPHERAL

MCC INTERRUPT

MCO

OSC2

OSC1

RESET

V

DD

V

SS

f

OSC

/2

OSCILLATOR

RESET

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3.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management
features in the application, the Low Voltage Detec­tor function (LVD) generates a static reset when
the VDDsupply voltage is below a V

IT-

reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.

The V

IT-

referencevalue fora voltage drop is lower

than the V

IT+

referencevalue forpower-on in order
to avoid a parasitic reset when theMCUstarts run­ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when
VDDis below:

–V

IT+

when VDDis rising

–V

IT-

when VDDis falling

The LVD function is illustrated in Figure 10.
Provided the minimum VDDvalue (guaranteed for

the oscillator frequency) is below V

IT-

, the MCU

can only be in two modes:

– under full software control
– in static safe reset

In these conditions, secure operation is always en­sured for the application without the need for ex­ternal reset hardware.

During aLow Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.

Notes:
The LVDallows the device to be used without any

external RESET circuitry.
The LVD is an optional function which can be se-

lected when ordering the device (ordering informa­tion).

Figure 10. Low Voltage Detector vs Reset

V

DD

V

IT+

RESET

V

IT-

V

hys

ST72311R, ST72511R, ST72512R, ST72532R

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3.2 RESET MANAGER

The RESET block includes three RESET sources
as shown in Figure 11:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

The RESET service routine vector is fixed at ad­dresses FFFEh-FFFFh in theST7 memory map.

A 4096 CPUclock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 11. Reset Block Diagram

f

CPU

COUNTER

RESET

R

ON

V

DD

WATCHDOG RESET

LVD RESET

INTERNAL
RESET

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RESET MANAGER (Cont’d)
External RESET pin

The RESETpin is both an input andan open-drain
output with integrated RONweak pull-up resistor
(see Figure11). This pull-up has no fixedvalue but
varies in accordance with the input voltage. Itcan
be pulled low by external circuitry to reset the de­vice.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

in
order to be recognized. Two RESET sequences
can be associated with this RESET source as
shown in Figure 12.

When the RESET is generated by a internal
source, during the two first phases of the RESET
sequence, the device RESET pin acts as an out­put that ispulled low.

Generic Power On RESET

The function of the POR circuit consists of waking
up the MCU by detecting (at around 2V) a dynamic
(rising edge) variation of the VDDSupply. At the
beginning of this sequence, the MCU is configured
in the RESET state. When the power supply volt­age rises toa sufficient level, the oscillator starts to
operate, whereupon an internal 4096 CPU cycles
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate­ly following the internal delay.

To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi­cient level forthe chosen frequency (seeElectrical
Characteristics) before the reset signal is re­leased. In addition, supply rising must start from
0V.

As a consequence, the POR does not allow to su­pervise static, slowly rising, or falling, or noisy (os­cillating) VDDsupplies.

An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performance.

Figure 12. External RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

t

h(RSTL)in

V

DD

V

IT-

V

DD nominal

WATCHDOG RESET

DELAY

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RESET MANAGER (Cont’d)
Internal Low VoltageDetection RESET (option)

Two different RESET sequences caused by the in­ternal LVD circuitry can be distinguished:

- LVD Power-On RESET

- Voltage Drop RESET

In the second sequence, a “delay” phase is used
to keep the device in RESET state until VDDrises
up to V

IT+

(see Figure 13).

Figure 13. LVD RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

POWER-

RESET PIN

EXTERNAL RESET SOURCE

WATCHDOG RESET

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

V

DD

V

DDnominal

WATCHDOG RESET

DELAY

V

IT+

V

IT-

V

DD

V

DDnominal

V

IT+

LVD POWER-ON RESET

VOLTAGE DROP RESET

OFF

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RESET MANAGER (Cont’d)
Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow has the shortest reset
phase (see Figure 14).

Figure 14. Watchdog RESET Sequence

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

V

DD

V

IT-

V

DDnominal

WATCHDOG RESET

WATCHDOG UNDERFLOW

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3.3 LOW CONSUMPTION OSCILLATOR

The main clock of the ST7 can be generated by
two differentsources:

■ an external source

■ a crystal or ceramic resonator oscillators

External Clock Source

In this mode, asquare clock signal with ~50% duty
cycle has to drive the OSC1 pin while the OSC2
pin is tied to VDDthrough a R

OBP

resistance (see

Figure 15).

Figure 15. External Clock

Crystal/Ceramic Oscillators

This oscillator (based on constant current source)
is optimized in terms of consumption and has the
advantage of producing a very accurate rate on
the main clock of the ST7.
When using this oscillator, the resonator and the
load capacitances have to be connected as shown
in Figure 16 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.

This oscillator is not stopped during the RESET
phase to avoid losing time in the oscillator start-up
phase.

Figure 16. Crystal/Ceramic Resonator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

V

DD

R

OBP

OSC1 OSC2

LOAD

CAPACITANCES

ST7

C

L2

C

L1

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3.4 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7
CPU and its internal peripherals. It allows to man­age the power saving modes such as the SLOW
and ACTIVE-HALT modes. The whole functionali­ty is managed by the Main Clock Control/Status
Register (MCCSR) and the Miscellaneous Regis­ter 1 (MISCR1).

The MCC block consists of:

– a programmable CPU clock prescaler
– a time base counter with interrupt capability
– a clock-out signalto supply external devices

The prescaler allows to select the main clock fre­quency and is controlled with three bits of the
MISCR1: CP1, CP0 and SMS.

The counterallows to generate an interrupt based
on a accurate real time clock. Four different time
bases depending directly on f

OSC

are available.
The wholefunctionality is controlled by four bits of
the MCCSR register: TB1, TB0, OIE and OIF.

The clock-out capability allowsto configure a ded­icated I/O port pin as an f

OSC

/2 clock out to drive
external devices. It is controlled by the MCO bit in
the MISCR1 register.
When selected, the clock out pin suspends the
clock during ACTIVE-HALT mode.

Figure 17. Main Clock Controller (MCC) Block Diagram

DIV 2, 4, 8, 16

MCC INTERRUPT

DIV 2

SMSCP1 CP0

TB1 TB0 OIE OIF

CPU CLOCK

MISCR1

PROGRAMMABLE

DIVIDER

CAN PERIPHERAL

TO CPU AND

PERIPHERALS

f

OSC

f

CPU

MCO

PORT

FUNCTION

ALTERNATE

OSC2

OSC1

MCO ----

0000MCCSR

OSCILLATOR

MCC

f

OSC

/2

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MAIN CLOCK CONTROLLER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)

See “MISCELLANEOUS REGISTERS” Section.

MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)

Read/Write
Reset Value: 0000 0001 (01h)

Bit 7:4 = Reserved, always read as 0.

Bit 3:2 = TB1-TB0

Time base control

These bits select the programmable divider time
base. They are set and cleared by software.

A modification of the time base is taken into ac­count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
When this bit is set,calling the ST7 software HALT
instruction enters theACTIVE-HALTpower saving
mode.

Bit 0 = OIF

Oscillator interrupt flag

This bit is set by hardware andcleared by software
reading the CSR register. It indicates when set
that the mainoscillator has measured the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached

Warning: The BRES and BSET instructions must
not be used on the MCCSR register to avoid unin­tentionally clearing the OIF bit.

Table 4. MCC Register Map and Reset Values

70

0000TB1TB0OIEOIF

Counter

Prescaler

Time Base

TB1 TB0

f

OSC

=8MHz f

OSC

=16MHz

32000 4ms 2ms 0 0

64000 8ms 4ms 0 1
160000 20ms 10ms 1 0
400000 50ms 25ms 1 1

Address

(Hex.)

Register

Label

76543210

0029h

MCCSR

Reset Value 0 0 0 0

TB1

0

TB0

0

OIE

0

OIF

1

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4 INTERRUPTS & POWER SAVING MODES

4.1 INTERRUPTS

4.1.1 Introduction

The ST7 enhanced interrupt management pro­vides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level
management:

– Up to 4 softwareprogrammable nesting levels
– Up to 16 interrupt vectorsfixed by hardware
– 3 non maskable events: NMI,RESET, TRAP

This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest­ed) ST7 interrupt controller.

4.1.2 Interrupt Masking and Processing Flow

The interruptmaskingis managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The process­ing flow is shown in Figure 18

When an interrupt request has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1and I0 bits of CC register areset according to

the corresponding values in the ISPRx registers
of the serviced interrupt vector.

– The PC isthen loadedwiththe interrupt vector of

the interrupt to service and the firstinstruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.

Table 5. Interrupt Software Priority Levels

Figure 18. Interrupt Processing Flowchart

Interrupt software priority Level I1 I0

Level 0 (main) Low

High

10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

“IRET”

RESTORE PC,X, A,CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

NMI

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PCFROM INTERRUPT VECTOR

Y

N

Y

N

Y

N

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

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INTERRUPTS (Cont’d)
Servicing Pending Interrupts

As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter­mined by the following two-stepprocess:

– the highest software priority interrupt is serviced,
– if several interrupts have thesame software pri-

ority then the interrupt with the highesthardware
priority is serviced first.

Figure 19 describes this decision process.

Figure 19. Priority Decision Process

When an interrupt request is not servicedimmedi­ately, it is latched and then processed when its
software priority combined with the hardware pri­ority becomes the highest one.

Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET,TRAP and NMIare nonmaskable
and they can be considered as having the highest
software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, NMI, TRAP) and the maskable type (ex­ternal or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 18). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit
HALT mode.

■ NMI (Non Maskable Hardware Interrupt)

This hardware interrupt occurs when a specific
edge is detected onthe dedicated NMI pin. Its de­tailed specification is given in the Miscellaneous
register chapter.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord­ing to the flowchart on Figure 18 as an NMI.

■ RESET

The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high­est hardware priority.
See the RESET chapterfor more details.

Maskable Sources

Maskable interrupt vector sourcescan be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi­tions is false, the interrupt is latched and thus re­mains pending.

■ External Interrupts

External interruptsallow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the Miscellaneous registers (MISCRx).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these willbe logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to anassociated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se­quence is executed.

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHESTHARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE
PRIORITY SERVICED

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INTERRUPTS (Cont’d)

4.1.3 Interrupts and Low Power Modes

All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in“Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter­rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 19

Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt isserviced
after the first one serviced.

4.1.4 Concurrent and Nested Interrupt
Management

The following Figure 20 and Figure 21 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in­terrupt to be interrupted, unlike the nested mode in
Figure 21 The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, NMI. The software priority is
given for each interrupt.

Warning: A stackoverflow may occur without no­tifying the software of the failure.

Figure 20. Concurrent interrupt management

Figure 21. Nested interrupt management

MAIN

IT4

IT2

IT1

NMI

IT1

MAIN

IT0

I1

HARDWARE PRIORITY

SOFTWARE

3
3
3
3
3
3/0

3

11
11
11
11
11

11 / 10

11

RIM

IT2

IT1

IT4

NMI

IT3

IT0

IT3

I0

10

PRIORITY
LEVEL

USED STACK = 10 BYTES

MAIN

IT2

NMI

MAIN

IT0

IT2

IT1

IT4

NMI

IT3

IT0

HARDWARE PRIORITY

3
2
1
3
3
3/0

3

11
00
01
11
11

11

RIM

IT1

IT4 IT4

IT1

IT2

IT3

I1 I0

11 / 10 10

SOFTWARE
PRIORITY
LEVEL

USED STACK = 20 BYTES

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INTERRUPTS (Cont’d)

4.1.5 Interrupt Register Descriptions
CPU CC REGISTER INTERRUPT BITS

Read/Write
Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0

Software Interrupt Priority

These two bits indicate the current interrupt soft­ware priority.

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the correspondingbits in the interrupt softwarepri­ority registers (ISPRx).

They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in­structions (see “Interrupt Dedicated Instruction
Set” table).

*Note: NMI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 pro­gram.

INTERRUPT SOFTWARE PRIORITY REGIS­TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)
Reset Values: 1111 1111 (FFh)

These four registers contain the interrupt software
priority of each interruptvector.

– Each interruptvector (except RESET andTRAP)

has corresponding bits in these registers where
its own software priority is stored. This corre­spondance is shown in the following table.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previouslystored valueiskept. (ex­ample: previous=CFh, write=64h,result=44h)

The RESET,TRAP and NMI vectors have no soft­ware priorities. When one isserviced, the I1 and I0
bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre­spond to the NMI can be read and written but they
are not significant in the interrupt process man­agement.

Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be­haviour has to be considered: If the interrupt x is
still pending (newinterrupt or flag not cleared) and
the new software priority is higher than the previ­ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter­rupt x).

70

11I1 H I0 NZC

Interrupt Software Priority Level I1 I0

Level 0 (main)

Low

High

10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) 1 1

70

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

ST72311R, ST72511R, ST72512R, ST72532R

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INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of thepreviously mentioned instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never

be used in an interrupt routine.

Table 7. Interrupt Mapping

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 I1:0=11 ?
JRNM Jump if I1:0<>11 I1:0<>11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0

N°

Source

Block

Description

Register

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET Reset

N/A

Highest

Priority

Lowest
Priority

yes FFFEh-FFFFh

TRAP Software Interrupt no FFFCh-FFFDh
0 NMI External Non Maskable Interrupt MISCR2 yes FFFAh-FFFBh
1 MCC Main Clock Controller Time Base Interrupt MCCSR FFF8h-FFF9h
2 EI0 External Interrupt Port A3..0

N/A

FFF6h-FFF7h
3 EI1 External Interrupt Port F2..0 FFF4h-FFF5h
4 EI2 External Interrupt Port B3..0 FFF2h-FFF3h
5 EI3 External Interrupt Port B7..4 FFF0h-FFF1h

6 CAN CAN Peripheral Interrupts CANISR FFEEh-FFEFh
7 SPI SPI Peripheral Interrupts SPISR

no

FFECh-FFEDh
8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh
9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h

10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h
11 EEPROM EEPROM Interrupt EECSR FFE4h-FFE5h
12 Not Used FFE2h-FFE3h
13 PWM ART PWM ART Overflow Interrupt ARTCSR Yes FFE0h-FFE1h

ST72311R, ST72511R, ST72512R, ST72532R

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INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

0024h

ISPR0

Reset Value

EI1 EI0 MCC NMI

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

111

0025h

ISPR1

Reset Value

SPI CAN EI3 EI2

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

0026h

ISPR2

Reset Value

EEPROM SCI TIMER B TIMER A

I1_11

1

I0_11

1

I1_10

1

I0_10

1

I1_9

1

I0_9

1

I1_8

1

I0_8

1

0027h

ISPR3

Reset Value 1 1 1 1

PWMART Not Used

I1_13

1

I0_13

1

I1_12

1

I0_12

1

ST72311R, ST72511R, ST72512R, ST72532R

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4.2 POWER SAVING MODES

4.2.1 Introduction

To give a large measure of flexibilitytotheapplica­tion in terms of power consumption, four main
power saving modes are implemented in the ST7.

After a RESET the normal operating mode is se­lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by

means of a master clock which is based on the
main oscillator frequency divided by 2 (f

CPU

).

From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil­lator status.

Figure 22. Power saving mode consumption / transitions

4.2.2 HALT Modes

The HALT modes are the lowest power consump­tion modes of the MCU. They are entered by exe­cuting the ST7 HALT instruction (see Figure 24).

Two different HALT modes can be distinguished:
– HALT: main oscillator is turned off,
– ACTIVE-HALT: only main oscillator is running.
The decision to enter either in HALT or ACTIVE-

HALT mode is given by the main oscillator enable
interrupt flag (OIE bit in CROSS-MCCSR register:
see Table 9).

When entering HALT modes, the I1 and I0 bits in
the CCRegister are forcedto level 0 (“10”) to ena­ble interrupts.

The MCU can exit HALT or ACTIVE-HALT modes
on reception of an interrupt with Exit from Halt

Mode capability or a reset (see Figure 7 on page

35). A 4096 CPU clock cycles delay is performed
before the CPU operation resumes (see Figure

23).
After the start up delay, the CPU resumes opera-

tion by servicing the interruptor by fetching the re­set vector which woke it up.

Table 9. HALT Modes selection

Figure 23. HALT /ACTIVE-HALT Modes timing overview

POWERCONSUMPTION

WAIT SLOW RUNHALT ACTIVE-HALT

High

Low

SLOW WAIT

MCCSR

OIE
flag

Power Saving Mode entered when HALT

instruction is executed

0 HALT (reset if watchdog enabled)
1 ACTIVE-HALT (no reset if watchdog enabled)

HALT OR ACTIVE-HALT

RUN

RUN

4096 CPU CYCLE

DELAY

RESET

OR

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ST72311R, ST72511R, ST72512R, ST72532R

38/159

POWER SAVING MODES (Cont’d)
Standard HALT mode

In this mode the main oscillator is turned off caus­ing all internal processing to be stopped, including
the operation ofthe on-chipperipherals. All periph­erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external orauxiliary oscillator).
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the OPTION BYTE. The HALT instruction when
executed while the Watchdog system is enabled,
can generate a Watchdog RESET (see Section

9.1 OPTION BYTES for more details).
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabi­lize the oscillator.

Specific ACTIVE-HALT mode

As soon as the interrupt capability of the main os­cillator is selected (OIE bit set), the HALT instruc­tion will make the device enter a specific ACTIVE­HALT power saving mode instead of the standard
HALT one.
This mode consists of having only the main oscil­lator and its associated counter running to keep a
wake-up time base. All other peripherals are not
clocked except the ones which get their clocksup­ply from another clock generator (such as external
or auxiliary oscillator).

The safeguard against staying locked in this AC­TIVE-HALT mode isinsured by the oscillator inter­rupt.

Note: As soon as the interrupt capability of one of
the oscillators is selected (OIE bit set), entering in
ACTIVE-HALT modewhilethe Watchdog is active
does not generate a RESET.
This means that the device cannot to spend more
than a defined delay in this power saving mode.

Figure 24. HALT modes flow-chart

HALT INSTRUCTION

OSCILLATOR

1

0

CPU

OSCILLATOR
PERIPHERALS

I1 AND I0 BITS

ON

OFF

10

OFF

Notes:

OIE BIT

CPU

OSCILLATOR
PERIPHERALS

I1 AND I0 BITS

OFF
OFF

10

OFF

RESET

EXTERNAL*

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

ON
OFF
OFF

INTERRUPT

HALT

ACTIVE-HALT

MAIN

FETCH RESET VECTOR

OR SERVICE INTERRUPT **

4096 clock cycles delay

CPU

OSCILLATOR
PERIPHERALS

ON
ON
ON

External interrupt or internal interrupts with Exit from Halt Mode capability

*

**

Before servicing an interrupt, the CC register is pushed on the stack.

WATCHDOG

YN

ENABLE

If WDGHALT
bit reset in
OPTION BYTE

ST72311R, ST72511R, ST72512R, ST72532R

39/159

POWER SAVING MODES (Cont’d)

4.2.3 WAIT Mode

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This power saving mode is selectedby calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I1 and I0 bits of the CC register are forced to
level 0 (“10”), to enable all interrupts. All other reg­isters and memory remain unchanged. The MCU
remains in WAIT mode until an interrupt or Reset
occurs, whereupon the Program Counter branch­es to the starting address of the interruptor Reset
service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.

Refer to Figure25.

Figure 25. WAIT Mode Flow-chart

Note: Before servicing an interrupt, the CC regis-

ter is pushed on the stack.The I1:0 bits of the CC
register are set according to the software priority of
the serviced interrupt routine. They are restored
when the CC register ispopped.

4.2.4 SLOW Mode

This mode has two targets:
– To reduce powerconsumption bydecreasingthe

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

)to

the available supply voltage.

SLOW modeis controlled bythree bits in the main
oscillator MISCR1 register: the SMS bit which en­ables or disables Slow mode and two CPx bits
which select the internalslow frequency (f

CPU

).

In this mode, the oscillator frequency can bedivid­ed by 4, 8, 16 or 32 instead of 2 in normal operat­ing mode. The CPU andperipherals (except CAN,
see Note) are clockedat this lower frequency.

Note: Before entering SLOW mode andin order to
guarantee low power operation, the CAN peripher­al must beplaced by software in STANDBY mode.

Figure 26. SLOW Mode Clock Transitions

WFI INSTRUCTION

RESET

INTERRUPT

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

I1:0 BITS

ON
ON

10

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I1:0 BIT

ON

OFF

11

ON

CPU

OSCILLATOR
PERIPHERALS

I1:0 BIT (see note)

ON
ON
ON

4096 CPU CLOCK CYCLE

DELAY

00 01

SMS

CP1:0

f

CPU

NEW SLOW

NORMAL RUN MODE

MISCR1

FREQUENCY

REQUEST

REQUEST

f

OSC

/2

f

OSC

/4 f

OSC

/8 f

OSC

/2

ST72311R, ST72511R, ST72512R, ST72532R

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5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introduction

The I/O ports offer different functional modes:
– transferofdatathrough digitalinputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-

ripherals (SPI, SCI, TIMERs...).

An I/O port contains up to 8 pins.Each pin can be
programmed independently as digital input(with or
without interrupt generation)or digital output.

5.1.2 Functional Description

Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/Opin may be programmed using thecorre-

sponding registerbits in DDR and ORregisters:bit
X corresponding topinXof the port. The samecor­respondence is used for the DR register.

The following description takes into account the
OR register, for specific port which do not provide
this register refer to the I/O Port Implementation
section. The generic I/O block diagram is shown
on Figure 27

Input Modes

The input configuration is selected by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can beselected bysoftware
through the OR register.

Note1: Writing the DR register modifies the latch
value but does not affect the pin status.
Note2: When switching from input to output mode,
the DR register has to be written first to drive the
correct levelon the pinassoon as the ports is con­figured as an output.

External interrupt function

When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In­terrupt request to the CPU.

Each pin can independently generate an Interrupt
request. The interrupt sensitivity is given inde­pendently according to the description mentioned
in the Miscellaneous register.

Each external interrupt vector is linked to a dedi­cated group of I/O port pins (seeInterrupt section).
If more than one input pins are selected simultane­ously as interrupt source, these are logically AND­ed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.

In case of a floating input with interrupt configura­tion, special cares mentioned in theI/O port imple­mentation sectionhave to be taken.

Output Mode

The output configuration is selected by setting the
corresponding DDR register bit.

In this case, writing the DR register applies this
digital value to the I/O pin through the latch. Then
reading the DR register returns the previously
stored value.

Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.

DR register value and output pin status:

Note: In this mode, interrupt function is disabled.

Alternate function

When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select­ed. This alternate function takes priority over the
standard I/O programming.

When the signal is coming froman on-chip periph­eral, the I/O pin is automatically configured in out­put mode (push-pull or open drain according to the
peripheral).

When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.

Note: Input pull-up configuration can cause unex­pected value attheinput ofthealternateperipheral
input. Whenan on chip peripheral use a pin as in­put and output, this pin has to be configured in in­put floating mode.

WARNING: The alternate function mustnot be ac­tivated as long as the pin is configured as input
with interrupt,in order to avoid generating spurious
interrupts.

DR Push-pull Open-drain

0V

SS

Vss

1V

DD

Floating

ST72311R, ST72511R, ST72512R, ST72532R

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I/O PORTS (Cont’d)

Figure 27. I/O Block Diagram

Table 10. Port Mode Options

Legend:NI - not implemented

Off - implemented not activated
On - implemented and activated

Note: the diode to VDDis not implemented in the
true open drain pads. A local protection between
the padandVSSisimplemented to protect the de­vice against positive stress.

Configuration Mode Pull-Up P-Buffer

Diodes

to V

DD

to V

SS

Input

Floating with/without Interrupt Off

Off

On

On

Pull-up with/without Interrupt On

Output

Push-pull

Off

On
Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

DR

DDR

OR

DATA BUS

PAD

V

DD

ALTERNATE
ENABLE

ALTERNATE
OUTPUT

1

0

OR SEL

DDR SEL

DR SEL

PULL-UP
CONDITION

P-BUFFER
(see table below)

N-BUFFER

PULL-UP
(see table below)

1

0

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

V

DD

DIODES
(see table below)

FROM
OTHER
BITS

EXTERNAL

SOURCE (EIx)

INTERRUPT

POLARITY
SELECTION

CMOS
SCHMITT
TRIGGER

ST72311R, ST72511R, ST72512R, ST72532R

42/159

I/O PORTS (Cont’d)

5.1.3 I/O Port Implementation

The I/O port register configurations are summa­rised as following.

Standard Ports
PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3

Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)

PA3, PB4, PB3, PF2 (without pull-up)

Switching theseI/O ports from one state to anoth­er should be done in a sequence that prevents un­wanted side effects. Recommended safe transi­tions are illustrated in Figure 28 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.

Figure 28. Interrupt I/O Port State Transition

True Open Drain Ports
PA7:6

Pull-up Input Port (CANTX requirement)
PE2

Table 11. Port Configuration

* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.

MODE DDR OR

floating input 0 0
pull-up input 0 1
open drain output 1 0
push-pull output 1 1

MODE DDR OR

floating input 0 0
pull-up interrupt input 0 1
open drain output 1 0
push-pull output 1 1

MODE DDR OR

floating input 0 0
floating interrupt input 0 1
open drain output 1 0
push-pull output 1 1

MODE DDR

floating input 0
open drain (high sink ports) 1

MODE

pull-up input

01

floating/pull-up

interrupt

INPUT

00

floating

(reset state)

INPUT

10

open-drain

OUTPUT

11

push-pull

OUTPUT

XX

= DDR, OR

Port Pin name

Input Output

OR = 0 OR = 1 OR = 0 OR = 1 High-Sink

Port A

PA7:6 floating true open-drain

Yes

PA5:4 floating pull-up open drain push-pull
PA3 floating floating interrupt open drain push-pull

No

PA2:0 floating pull-up interrupt open drain push-pull

Port B

PB4, PB3 floating floating interrupt open drain push-pull

PB7:5, PB2:0 floating pull-up interrupt open drain push-pull
Port C PC7:0 floating pull-up open drain push-pull PC3:2 only
Port D PD7:0 floating pull-up open drain push-pull No

Port E

PE7:3, PE1:0 floating pull-up open drain push-pull PE7:4 only

PE2 pull-up input only * No

Port F

PF7:3 floating pull-up open drain push-pull PF7:6 only

PF2 floating floating interrupt open drain push-pull

No

PF1:0 floating pull-up interrupt open drain push-pull

ST72311R, ST72511R, ST72512R, ST72532R

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I/O PORTS (Cont’d)

5.1.4 Register Description
DATA REGISTER (DR)

Port x Data Register
PxDR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour accord­ing to the selectedinput/output configuration. Writ­ing the DR register is always taken into account
even ifthe pinis configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured asoutput) or the digital value applied to
the I/O pin (pin configured as input).

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.

0: Input mode
1: Output mode

OPTION REGISTER (OR)

Port x Option Register
PxOR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implement­ed. In this case the DDR register is enough to se­lect the I/O pin configuration.

The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drainconfigurationis
selected.

Each bit is set and cleared by software.
Input mode:

0: floating input
1: pull-up input with or without interrupt

Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull

70

D7 D6 D5 D4 D3 D2 D1 D0

70

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

70

O7 O6 O5 O4 O3 O2 O1 O0

ST72311R, ST72511R, ST72512R, ST72532R

44/159

I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

Reset Value

of all IO port registers

00000000

0000h PADR

MSB LSB0001h PADDR
0002h PAOR
0004h PCDR

MSB LSB0005h PCDDR
0006h PCOR
0008h PBDR

MSB LSB0009h PBDDR

000Ah PBOR
000Ch PEDR

MSB LSB000Dh PEDDR

000Eh PEOR

0010h PDDR

MSB LSB0011h PDDDR
0012h PDOR
0014h PFDR

MSB LSB0015h PFDDR
0016h PFOR

ST72311R, ST72511R, ST72512R, ST72532R

45/159

5.2 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over
several features such as the external interrupts or
the I/Oalternate functions.

5.2.1 I/O Port Interrupt Sensitivity Description

The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the Miscellaneous
registers (Figure 29). This control allows to have
up to 4 fully independent external interrupt source
sensitivities.

Each external interrupt source can be generated
on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for EI0 and EI2)

To guarantee correct functionality, the sensitivity
bits in the MISCR registers must be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). See I/O port register and Miscel­laneous register descriptions for more details on
the programming.

5.2.2 I/O Port Alternate Functions

The MISCR registers allow to manage fourI/O port
miscellaneous alternate functions:

■ Main clock signal (f

OSC

/2) output on PF0

■ A Beep signal output on PF1 (with three

selectable audio frequencies)

■ A NMI management on a dedicated pin

■ A SPI SS pin internal control to use the PC7 I/O

port function while the SPI is active.

These functions are described in details in the
Section 5.2.3 Miscellaneous Registers Descrip­tion.

Figure 29. External Interrupt Sources vs MISCR

EI0

INTERRUPT

SOURCE

EI1

INTERRUPT

SOURCE

IS20IS21

MISCR1

SENSITIVITY

CONTROL

PA3
PA2

MISCR2.IPA

PA1
PA0

PF2
PF1
PF0

EI2

INTERRUPT

SOURCE

EI3

INTERRUPT

SOURCE

IS10IS11

MISCR1

SENSITIVITY

CONTROL

PB3
PB2

MISCR2.IPB

PB1
PB0

PB7
PB6
PB5
PB4

SOURCES

SOURCES

SOURCES

SOURCES

ST72311R, ST72511R, ST72512R, ST72532R

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MISCELLANEOUS REGISTERS (Cont’d)

5.2.3 Miscellaneous Registers Description
MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

EI2 and EI3 sensitivity

The interruptsensitivity, definedusing the IS1[1:0]
bits, is appliedto the following external interrupts:

- EI2 (port B3..0)

- EI3 (port B7..4)

These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).

Bit 5 = MCO

Main clock out selection

This bit enablesthe MCO alternatefunction on the
PF0 I/O port. It isset and cleared by software.
0: MCOalternatefunctiondisabled(I/Opinfree for

general-purpose I/O)

1: MCO alternate function enabled (f

OSC

/2on I/O

port)

Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

Bit 4:3 = IS2[1:0]

EI0 and EI1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:

- EI0 (port A3..0)

- EI1 (port F2..0)

These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software

Bit 0 = SMS

Slow mode select

This bit is set andcleared by software.
0: Normal mode. f

CPU

= f

OSC

/2

1: Slow mode. f

CPU

is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.

70

IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS

IS11 IS10

External Interrupt Sensitivity

MISCR2.IPB=0 MISCR2.IPB=1

00

Falling edge &

low level

Rising edge

& high level
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edgeonly
1 1 Rising and falling edge

IS21 IS20

External Interrupt Sensitivity

MISCR2.IPA=0 MISCR2.IPA=1

00

Falling edge &

low level

Rising edge

& high level
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge

f

CPU

in SLOW mode CP1 CP0

f

OSC

/4 0 0

f

OSC

/8 1 0

f

OSC

/16 0 1

f

OSC

/32 1 1

ST72311R, ST72511R, ST72512R, ST72532R

47/159

MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7 = IPA

Interrupt polarity for port A

This bit isusedto invert the sensitivity oftheport A
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 5.2.1 I/O Port Interrupt SensitivityDe­scription and the description of the IS2x bits of the
MISCR1 registerfor more details.

Bit 6 = IPB

Interrupt polarity for port B

This bit isusedto invert the sensitivity oftheport B
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 5.2.1 I/O Port Interrupt SensitivityDe­scription and the description of the IS1x bits of the
MISCR1 registerfor more details.

Bit 5:4 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE­HALT mode but has to be disabled to reduce the
consumption.

Bit 3 = NMIS

NMI sensitivity

This bit allows to toggle the NMI edge sensitivity. It
can be set and cleared by software only when
NMIE bit is cleared.
0: Falling edge
1: Rising edge

Bit 2 = NMIE

NMI enable

This bit allows to enable or disable the NMI capa­bility on the dedicated pin. It is set and cleared by
software.
0: NMI disabled
1: NMI enabled
Note: a parasitic interrupt can be generated when
clearing the NMIE bit.

Bit 1 = SSM

SS mode selection

This bit is set andcleared by software.
0: Normal mode - the level of the SPI SS signal is

input from the external SS pin.

1: I/Omode(PC7), the levelofthe SPI SS signalis

read from the SSI bit.

Bit 0 = SSI

SS internal mode

This bit replaces pin SS ofthe SPI when bitSSM is
set to 1. (seeSPI description).It is set and cleared
by software.

70

IPA IPB BC1 BC0 NMIS NMIE SSM SSI

BC1 BC0 Beep mode with f

OSC

=16MHz

0 0 Off
0 1 ~2-KHz

Output

Beep signal

~50% duty cycle

1 0 ~1-KHz
1 1 ~500-Hz

ST72311R, ST72511R, ST72512R, ST72532R

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MISCELLANEOUS REGISTERS (Cont’d)
Table 13. Miscellaneous Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

0020h

MISCR1

Reset Value

IS11

0

IS10

0

MCO

0

IS21

0

IS20

0

CP1

0

CP0

0

SMS

0

0040h

MISCR2

Reset Value

IPA

0

IPB

0

BC1

0

BC0

0

NMIS

0

NMIE

0

SSM

0

SSI

0

ST72311R, ST72511R, ST72512R, ST72532R

49/159

5.3 WATCHDOG TIMER (WDG)

5.3.1 Introduction

The Watchdog timer is used to detect the occur­rence of a software fault, usuallygenerated by ex­ternal interference or by unforeseen logical condi­tions, which causes the application program to
abandon its normal sequence. The Watchdog cir­cuit generates an MCU reset on expiry of a pro­grammed timeperiod, unless theprogram refresh­es the counter’s contents before the T6 bit be­comes cleared.

5.3.2 Main Features

■ Programmable timer (64 increments of 12288

CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) after a HALT

instruction or when the T6 bit reaches zero

■ Hardware Watchdog selectable by option byte

■ Watchdog Reset indicated by status flag (in

versions with Safe Reset option only)

5.3.3 Functional Description

The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy­cles, and the length of the timeout period can be
programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.

Figure 30. Watchdog Block Diagram

RESET

WDGA

7-BIT DOWNCOUNTER

f

CPU

T6 T0

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷12288

T1

T2

T3

T4

T5

ST72311R, ST72511R, ST72512R, ST72532R

50/159

WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-

ister at regularintervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table14.WatchdogTiming (fCPU = 8 MHz)):

– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-

diate reset

– TheT[5:0] bits contain the number ofincrements

which represents the time delay before the
watchdog produces a reset.

Table 14.Watchdog Timing (f

CPU

= 8 MHz)

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannotbe disabled, except
by a reset.

The T6 bit can be used to generate a software re­set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction
will generate a Reset.

5.3.4 Hardware Watchdog Option

If Hardware Watchdog Is selected by option byte,
the watchdogis always active and the WDGA bit in
the CR is not used.

Refer to the device-specific Option Byte descrip­tion.

5.3.5 Low Power Modes

5.3.6 Interrupts

None.

5.3.7 Register Description
CONTROL REGISTER (CR)

Read/Write
Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA

Activation bit

.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

Note: This bit is not used if the hardware watch­dog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).

STATUS REGISTER (SR)

Read/Write
Reset Value*: 0000 0000 (00h)

Bit 0 = WDOGF

Watchdog flag

.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred

* Only by software and power on/off reset
Note: This register is not used in versions without

LVD Reset.

CR Register

initialvalue

WDG timeout period

(ms)

Max FFh 98.304

Min C0h 1.536

Mode Description

WAIT No effect on Watchdog.

HALT

Immediate resetgenerationas soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).

70

WDGA T6 T5 T4 T3 T2 T1 T0

70

- - - - - - - WDOGF

ST72311R, ST72511R, ST72512R, ST72532R

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WATCHDOG TIMER (Cond’t)
Table 15. Watchdog Timer RegisterMap and Reset Values

Address

(Hex.)

Register

Label

76543210

002Ah

WDGCR

Reset Value

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

002Bh

WDGSR

Reset Value

-

0

-

0

-

0

-

0

-

0

-

0

-

0

WDOGF

0

ST72311R, ST72511R, ST72512R, ST72532R

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5.4 PWM AUTO-RELOAD TIMER (ART)

5.4.1 Introduction

The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare capabilities and of a 7-bit
prescaler clock source.

These resources allow three possible operating
modes:

– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
– External event detector

The two first modes can be used together with a
single counter frequency.

The timer can be used to wake up the MCU from
WAIT and HALT modes.

Figure 31. PWM Auto-Reload Timer Block Diagram

OVF INTERRUPT

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

ARTCSR

f

INPUT

PWMx

PORT

FUNCTION

ALTERNATE

OCRx

COMPARE

REGISTER

PROGRAMMABLE

PRESCALER

8-BIT COUNTER

(CAR REGISTER)

ARR

REGISTER

LOAD

OPx

POLARITY
CONTROL

OEx

PWMCR

MUX

f

CPU

DCRx

REGISTER

LOAD

f

COUNTER

ARTCLK

f

EXT

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)

5.4.2 Functional Description
Counter

The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris­ing edge of the clock signal.

It is possible to read or write the contents of the
counter onthe fly byreading or writing the Counter
Access register (CAR).

When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

f

COUNTER=fINPUT

/2

CC[2:0]

The timer counter’s input clock (f

INPUT

) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(CSR). Thus the division factor of the prescaler
can be set to 2n(where n = 0, 1,..7).

This f

INPUT

frequency source is selected through
the EXCLbit of the CSR register and canbe either
the f

CPU

or an external input frequency f

EXT

.

The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the CSR regis­ter. WhenTCE is reset, the counter is stopped and
the prescaler and counter contents are frozen.

When TCE is set, the counter runs at the rate of
the selected clock source.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are
cleared and f

INPUT=fCPU

.
The countercan be initialized by:
– Writing to the ARR register and then setting the

FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the CSR register.
– Writing to the CAR counter access register,
In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.
Direct access to the prescaler is not possible.

Output compare control

The timer compare function isbasedon four differ­ent comparisons with the counter (one for each
PWMx output). Each comparison is made be­tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy­cle register (DCRx) at each overflow of the coun­ter.

This double buffering method avoids glitch gener­ation when changing the duty cycle on the fly.

Figure 32. Output compare control

COUNTER

FDh FEh FFh FDh FEh FFh FDh FEh

ARR=FDh

f

COUNTER

OCRx

DCRx

FDh

FEh

FDh

FEh

FFh

PWMx

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation

This mode allows up to four Pulse Width Modulat­ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.

Each PWMx output signal can be selected inde­pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, thecorresponding I/Opin is configured as out­put push-pull alternate function.

The PWM signals all have the same frequency
which is controlled by the counter period and the
ARR register value.

f

PWM=fCOUNTER

/ (256 - ARR)

When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding

OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.

It should be noted that the reload values will also
affect the value and the resolution of thedutycycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents oftheOCRx register must
be greater than the contents of the ARR register.

The maximum available resolution for the PWMx
duty cycle is:

Resolution = 1 / (256 - ARR)

Note: To get the maximum resolution (1/256), the
ARR register must be 0. With this maximum reso­lution, 0% and 100% can be obtained by changing
the polarity.

Figure 33. PWM Auto-reload Timer Function

Figure 34. PWM Signal from 0% to 100% Duty Cycle

DUTY CYCLE

REGISTER

AUTO-RELOAD

REGISTER

PWMx OUTPUT

t

255

000

WITH OEx=1
AND OPx=0

(ARR)

(DCRx)

WITH OEx=1
AND OPx=1

COUNTER

COUNTER

PWMx OUTPUT

t

WITH OEx=1

AND OPx=0

FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARR=FDh

f

COUNTER

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt

On overflow, the OVF flag of the CSR register is
set and an overflow interrupt request is generated
if theoverflow interrupt enablebit, OIE, in the CSR
register, is set. The OVF flag must be reset by the
user software. This interruptcanbe used as a time
base in the application.

External clock and event detector mode

Using the f

EXT

external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARR register is
used to select the n

EVENT

number of events to be

counted before setting the OVF flag.

n

EVENT

= 256 - ARR

When entering HALT mode while f

EXT

is selected,
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.

Figure 35. External Event Detector Example (3 counts)

COUNTER

t

FDh FEh FFh FDh

OVF

CSR READ

INTERRUPT

ARR=FDh

f

EXT=fCOUNTER

FEh FFh FDh

IF OIE=1

INTERRUPT

IF OIE=1

CSR READ

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)

5.4.3 Register Description
CONTROL / STATUS REGISTER (CSR)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7 = EXCL

External Clock

This bitisset and cleared by software. Itselectsthe
input clock for the 7-bit prescaler.
0: CPU clock.
1: External clock.

Bit 6:4 = CC[2:0]

Counter Clock Control

These bits are set and cleared by software. They
determine the prescaler division ratio from f

INPUT

.

Bit 3 = TCE

Timer Counter Enable

This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counterstopped(prescalerandcounterfrozen).
1: Counter running.

Bit 2 = FCRL

Force Counter Re-Load

This bit is write-only and any attempt to read it will
yielda logicalzero.When set,it causesthecontents
of ARR register to be loaded into the counter, and
the contentofthe prescalerregisterto be clearedin
order toinitialize the timerbefore starting to count.

Bit 1 = OIE

Overflow Interrupt Enable

This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.

Bit 0 = OVF

Overflow Flag

This bit is set byhardwareand cleared by software
reading theCSR register. It indicates the transition
of the counter from FFh to the ARR value.
0: New transition not yet reached
1: Transition reached

COUNTER ACCESS REGISTER (CAR)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = CA[7:0]

Counter Access Data

These bits can be set and cleared either by hard­ware or by software. The CAR register is used to
read or write the auto-reload counter “on the fly”
(while it is counting).

AUTO-RELOAD REGISTER (ARR)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = AR[7:0]

Counter Auto-Reload Data

These bits are set and cleared by software. They
are used toholdthe auto-reload value which isau­tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.

This register has two PWM management func­tions:

– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution

PWM Frequency vs. Resolution:

70

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

f

COUNTER

With f

INPUT

=8 MHz CC2 CC1 CC0

f

INPUT

f

INPUT

/2

f

INPUT

/4

f

INPUT

/8

f

INPUT

/16

f

INPUT

/32

f

INPUT

/64

f

INPUT

/ 128

8 MHz
4 MHz
2 MHz

1 MHz
500 KHz
250 KHz
125 KHz

62.5 KHz

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

70

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

70

AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

ARR value Resolution

f

PWM

Min Max

0 8-bit ~0.244-KHz 31.25-KHz

[ 0..127 ] > 7-bit ~0.244-KHz 62.5-KHz
[ 128..191 ] > 6-bit ~0.488-KHz 125-KHz
[ 192..223 ] > 5-bit ~0.977-KHz 250-KHz
[ 224..239 ] > 4-bit ~1.953-KHz 500-KHz

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:4 = OE[3:0]

PWM Output Enable

These bits are set and cleared by software. They
enable or disable the PWM output channels inde­pendently acting on the correspondingI/O pin.
0: PWM outputdisabled.
1: PWM outputenabled.

Bit 3:0 = OP[3:0]

PWM Output Polarity

These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.

Note: When an OPx bit is modified, the PWMxout­put signal polarity is immediately reversed.

DUTY CYCLE REGISTERS (DCRx)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = DC[7:0]

Duty Cycle Data

These bits are set and cleared by software.
A DCRxregister is associated with the OCRx reg-

ister of each PWM channel to determine the sec­ond edge location of the PWM signal (the first
edge locationis commonto all channels andgiven
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.

70

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

PWMx output level

OPx

Counter <= OCRx Counter > OCRx

100
011

70

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

ST72311R, ST72511R, ST72512R, ST72532R

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PWM AUTO-RELOAD TIMER (Cont’d)
Table 16. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

0072h

PWMDCR3

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0073h

PWMDCR2

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0074h

PWMDCR1

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0075h

PWMDCR0

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0076h

PWMCR

Reset Value

OE3

0

OE2

0

OE1

0

OE0

0

OP3

0

OP2

0

OP1

0

OP0

0

0077h

ARTCSR

Reset Value

EXCL

0

CC2

0

CC1

0

CC0

0

TCE

0

FCRL

0

OIE

0

OVF

0

0078h

ARTCAR

Reset Value

CA7

0

CA6

0

CA5

0

CA4

0

CA3

0

CA2

0

CA1

0

CA0

0

0079h

ARTARR

Reset Value

AR7

0

AR6

0

AR5

0

AR4

0

AR3

0

AR2

0

AR1

0

AR0

0

ST72311R, ST72511R, ST72512R, ST72532R

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5.5 16-BIT TIMER

5.5.1 Introduction

The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.

It may be used fora variety of purposes, including
pulse length measurement of up to two input sig­nals (

input capture

) or generation of up to two out-

put waveforms (

output compare

and

PWM

).

Pulse lengths and waveform periods can be mod­ulated from a few microseconds to several milli­seconds using the timer prescaler and the CPU
clock prescaler.

5.5.2 Main Features

■ Programmableprescaler:f

CPU

dividedby2,4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower thantheCPUclock speed)withthechoice
of active edge

■ Output compare functions with

– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

■ Input capturefunctions with

– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternatefunctionson I/Oports (ICAP1,ICAP2,

OCMP1, OCMP2,EXTCLK)*

The Block Diagram is shown in Figure 36.
*Note: Some external pins are not available on all

devices. Refer to the device pin out description.
When reading an input signal which is not availa-

ble on an external pin, the value will always be ‘1’.

5.5.3 Functional Description

5.5.3.1 Counter

The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as­sociated 16-bit registers:

Counter Registers

– Counter High Register (CHR) is the most sig-

nificant byte (MSB).

– Counter Low Register (CLR) is the least sig-

nificant byte (LSB).

Alternate Counter Registers

– Alternate Counter HighRegister (ACHR)is the

most significant byte(MSB).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LSB).

These two read-only 16-bit registers contain the
same value but with thedifferencethat reading the
ACLR register does not clear the TOF bit(overflow
flag), (see note at the end of paragraph titled16-bit
read sequence).

Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.

The timer clock depends on the clock control bits
of the CR2 register,as illustrated in Table 17 Clock
Control Bits. The value in the counter register re­peats every 131.072, 262.144 or 524.288 internal
processorclock cycles depending on the CC1 and
CC0 bits.

ST72311R, ST72511R, ST72512R, ST72532R

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16-BIT TIMER (Cont’d)
Figure 36. Timer Block Diagram

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE
REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2
1/4

1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

EXTCLK

f

CPU

TIMER INTERRUPT

ICF2ICF1 000OCF2OCF1 TOF

PWMOC1E EXEDGIEDG2CC0CC1

OC2E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

ICAP2

LATCH2

OCMP2

8

8

8 low

16

8 high

16 16

16

16

CR1

CR2

SR

6

16

888

888

high

low

high

high

high

low

low

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

1

OUTPUT

COMPARE
REGISTER

2

INPUT

CAPTURE

REGISTER

1

INPUT

CAPTURE

REGISTER

2

CC1 CC0

16 BIT

FREE RUNNING

COUNTER

ST72311R, ST72511R, ST72512R, ST72532R

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16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter

Register or the Alternate CounterRegister).

The user must read the MSB first, then the LSB
value is buffered automatically.

This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.

After a complete reading sequence, if only the
CLR register or ACLR register are read, they re­turn the LSB of the count value at the time of the
read.

Whatever thetimermodeused(input capture, out­put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:

– The TOF bit of the SR register is set.
– A timer interrupt is generated if:

– TOIE bit of the CR1 register isset and
– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re­mains pending to be issued as soon as they are
both true.

Clearing the overflow interrupt request is done in
two steps:

1.Reading theSR register whilethe TOF bit is set.

2.An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to

ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.

The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).

5.5.3.2 External Clock

The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT­CLK that will trigger the free running counter.

The counter is synchronised with the falling edge
of the internal CPU clock.

At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thusthe external clockfrequen­cy must be less than a quarter of the CPU clock
frequency.

LSB is buffered

Read MSB

At t0

Read LSB

Returns the buffered

LSB value at t0

At t0 +∆t

Other

instructions

Beginning of the sequence

Sequence completed

ST72311R, ST72511R, ST72512R, ST72532R

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16-BIT TIMER (Cont’d)
Figure 37. Counter Timing Diagram, internal clock divided by 2

Figure 38. Counter Timing Diagram, internal clock divided by 4

Figure 39. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMERCLOCK

COUNTER REGISTER

OVERFLOW FLAGTOF

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMERCLOCK

COUNTER REGISTER

OVERFLOW FLAG TOF

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

OVERFLOW FLAG TOF

FFFC FFFD

0000

ST72311R, ST72511R, ST72512R, ST72532R

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16-BIT TIMER (Cont’d)

5.5.3.3 Input Capture

In this section, the index,i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run­ning counter after a transition detected by the
ICAPipin (see figure 5).

ICiregister is a read-only register.
The active transition is software programmable

through theIEDGibitofthe ControlRegister(CRi).
Timing resolution is one count of the free running

counter: (f

CPU

/(CC1.CC0)).

Procedure:

To use the input capture function select the follow­ing in the CR2 register:

– Select the timer clock (CC1-CC0) (see Table 17

Clock ControlBits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an

input capture coming from both the ICAP1 pin or

the ICAP2 pin
– Select the edge of the active transition on the

ICAP1 pin with theIEDG1 bit(the ICAP1pinmust

be configured as floating input).

When an input capture occurs:
– ICFibit is set.
– The ICiR register contains the value of the free

running counter on the active transition on the
ICAPipin (see Figure 41).

– A timer interrupt is generated if the ICIEbit is set

and the I bit is clearedin the CC register. Other­wise, the interrupt remains pending until both
conditions become true.

Clearing the Input Capture interrupt request is
done in two steps:

1.Reading the SR register while the ICFibitis set.

2.An access (read or write) to the ICiLR register.

Notes:

1.After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR
register is also read.

2.The ICiR register always contains the free run­ning counter value which corresponds to the
most recent input capture.

3.The 2 input capture functions can be used
together even if the timer also uses the output
compare mode.

4.In One pulse Mode and PWM mode only the
input capture 2 can be used.

5.The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap­ture process.

6.Moreover if one of the ICAPipin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.

7.The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).

MS Byte LS Byte

ICiR IC

i

HR ICiLR

ST72311R, ST72511R, ST72512R, ST72532R

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16-BIT TIMER (Cont’d)
Figure 40. Input Capture Block Diagram

Figure 41. Input Capture Timing Diagram

ICIE

CC0

CC1

16-BIT FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

16-BIT

IC1R RegisterIC2R Register

EDGE DETECT

CIRCUIT1

pin

pin

FF01 FF02 FF03

FF03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: A

ctive edge is rising edge.

ST72311R, ST72511R, ST72512R, ST72532R

65/159

16-BIT TIMER (Cont’d)

5.5.3.4 Output Compare

In this section, the index,i, may be 1 or 2.
This function can be used to control an output

waveform or indicating when a period of time has
elapsed.

When a match is found between the Output Com­pare register andthe freerunning counter, the out­put compare function:

– Assigns pinswith a programmable valueif the

OCIE bit is set
– Sets a flag in thestatus register
– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run­ning counter each timer clock cycle.

These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.

Timing resolution is one count of the free running
counter: (f

CPU/(CC1.CC0)

).

Procedure:

To use the output compare function, select the fol­lowing in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPipin is dedicated to the output compare

i

function.

– Select the timer clock (CC1-CC0) (see Table 17

Clock ControlBits).
And select the following in the CR1 register:
– SelecttheOLVLibittoappliedto theOCMPipins

after the match occurs.
– Set the OCIE bit to generate an interrupt if it is

needed.
When a match is found:
– OCFibit is set.
– The OCMPipin takes OLVLibit value (OCMP

i

pin latch is forced low during reset and stays low

until valid compares change it to a high level).
– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).
The OCiR register value required for a specifictim-

ing application can be calculated using thefollow­ing formula:

Where:

∆t = Desired output compare period (in sec-

onds)

f

CPU

= Internal clock frequency

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC1-CC0 bits, see Table 17
Clock Control Bits)

Clearing the output compare interrupt request is
done by:

1.Reading the SR register while the OCFibit is
set.

2.An access (read or write) to the OCiLR register.

The following procedure is recommended to pre­vent the OCFibit from being set between the time
it is read and the write to the OCiR register:

– Write to the OCiHR register (further compares

are inhibited).

– Readthe SR register (first step of the clearance

of the OCFibit, which may be already set).

– Write to the OCiLR register (enables the output

compare function and clears the OCFibit).

Notes:

1.After a processor write cycle to the OCiHR reg­ister, the output compare function is inhibited
until the OCiLR register is also written.

2.If the OCiE bit is not set, the OCMPipin is a
general I/O port and the OLVLibit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.

3.When the clock is divided by 2, OCFiand
OCMPiare set while the counter value equals
the OCiR register value (see Figure 43 on page

66). This behaviour is the same in OPM or
PWM mode.
When the clock is divided by 4, 8 or in external
clock mode, OCFiand OCMPiare set while the
counter value equals the OCiR register value
plus 1 (see Figure 44 on page 66).

4.The output compare functions can be used both
for generating external events on the OCMP

i

pins even if the input capture mode is also
used.

5.The value in the 16-bit OCiR register and the
OLVibit should be changed after each suc­cessful comparison in orderto control an output
waveform or establish a new elapsed timeout.

MS Byte LS Byte

OC

i

ROC

i

HR OCiLR

∆OC

i

R=

∆t*f

CPU

PRESC

ST72311R, ST72511R, ST72512R, ST72532R

66/159

16-BIT TIMER (Cont’d)
Figure 42. Output Compare Block Diagram

Figure 43. Output Compare Timing Diagram, InternalClock Dividedby 2

Figure 44. Output Compare Timing Diagram, InternalClock Dividedby 4

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

16-bit

16-bit

OCMP1

OCMP2

Latch

1

Latch

2

OC2R Register

Pin

Pin

INTERNAL CPU CLOCK

TIMERCLOCK

COUNTER

OUTPUT COMPARE REGISTER

OUTPUT COMPAREFLAG (OCFi)

OCMPi PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

INTERNAL CPU CLOCK

TIMERCLOCK

COUNTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

ST72311R, ST72511R, ST72512R, ST72532R

67/159

16-BIT TIMER (Cont’d)

5.5.3.5 Forced Compare

In this sectionimay represent 1 or 2.
The following bits of the CR1 register are used:

When the FOLVibit is set by software, the OLVL

i

bit iscopied to the OCMPipin. The OLVibithas to
be toggled in order to toggle the OCMPipin when
it isenabled (OCiE bit=1). The OCFibitis then not
set by hardware, and thus no interrupt request is
generated.

FOLVLibitshaveno effect in both one pulse mode
and PWM mode.

5.5.3.6 One PulseMode

One Pulse mode enables the generation of a
pulse when an external event occurs. This modeis
selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1
function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre­sponding to the length of the pulse (see the for­mula in Section 5.5.3.7).

2. Select the following in the CR1 register:
– Using the OLVL1 bit, selectthe level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, selectthe level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transitionon the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).

3. Select the following in the CR2 register:
– Set the OC1Ebit, the OCMP1 pinis then ded-

icated to the Output Compare 1 function.
– Set the OPMbit.
– Select thetimer clockCC1-CC0 (see Table17

Clock Control Bits).

Then, on a valid event on the ICAP1pin, the coun­ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and theval­ue FFFDh is loaded in the IC1R register.

When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 45).

Notes:

1.The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.

2.The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is
set.

3.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the onlyactive one.

4.If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.

5.The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture(ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.

6.When the one pulse mode is used OC1R is
dedicated to this mode. Nevertheless OC2R
and OCF2 can be used to indicate a period of
time has been elapsed but cannot generate an
output waveform because the level OLVL2 is
dedicated to the one pulse mode.

FOLV2 FOLV1 OLVL2 OLVL1

event occurs

Counter
= OC1R

OCMP1 = OLVL1

When

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ST72311R, ST72511R, ST72512R, ST72532R

68/159

Figure 45. One Pulse Mode Timing Example

Figure 46. Pulse Width Modulation Mode Timing Example

COUNTER

....

FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

COUNTER

34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OLVL2

OLVL2OLVL1

OCMP1

compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

ST72311R, ST72511R, ST72512R, ST72532R

69/159

16-BIT TIMER (Cont’d)

5.5.3.7 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.

The pulse width modulation mode uses the com­plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre­sponding to the period of the signal.

2. Load the OC1R register with the value corre­sponding to thelength of the pulse if (OLVL1=0
and OLVL2=1).

3. Select the following in the CR1 register:
– Using the OLVL1 bit, selectthe level to be ap-

plied to the OCMP1 pin after a successful
comparison with OC1R register.

– Using the OLVL2 bit, selectthe level to be ap-

plied to the OCMP1 pin after a successful
comparison with OC2R register.

4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see Table

17 Clock Control Bits).

If OLVL1=1 and OLVL2=0 the length of the posi­tive pulse is the difference betweenthe OC2R and
OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.

The OCiR register value required for a specifictim­ing application can be calculated using thefollow­ing formula:

Where:
t = Desired output compare period (in sec-

onds)

f

CPU

= Internal clock frequency

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC1-CC0 bits, seeTable 17
Clock Control Bits)

The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 46).

Notes:

1.After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
Therefore the Input Capture 1 function is inhib­ited but the Input Capture2 is available.

2.The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.

3.The ICF1 bit is set by hardware when the coun­ter reaches the OC2R value and can produce a
timer interruptif the ICIE bit is setand the I bit is
cleared.

4.In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon­nected to the timer.The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIEis set.

5.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the onlyactive one.

OCiR Value =

t*f

CPU

PRESC

-5

Counter

OCMP1 = OLVL2

Counter
= OC2R

OCMP1 = OLVL1

When

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

ST72311R, ST72511R, ST72512R, ST72532R

70/159

16-BIT TIMER (Cont’d)

5.5.4 Low Power Modes

5.5.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).

Mode Description

WAIT

No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Haltmode is exited. Counting resumes from the previous

count when the MCU is woken upby an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

i

pin, the input capture detection circuitry isarmed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF

i

bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

i

R register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode ICF1

ICIE

Yes No
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1

OCIE

Yes No
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No

ST72311R, ST72511R, ST72512R, ST72532R

71/159

16-BIT TIMER (Cont’d)

5.5.6 Register Description

Each Timer is associated with three control and
status registers, and with six pairsofdata registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al­ternate counter.

CONTROL REGISTER 1 (CR1)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7 = ICIE

Input CaptureInterrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE

Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set andcleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.

Bit 3 = FOLV1

Forced Output Compare 1.

This bit is set andcleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1to becopied to theOCMP1 pin,if

the OC1E bit is set and even if there is no suc­cessful comparison.

Bit 2 = OLVL2

Output Level 2.

This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg­ister and OCxE is set in the CR2 register. This val­ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 1 = IEDG1

Input Edge 1.

This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when­ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

70

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

ST72311R, ST72511R, ST72512R, ST72532R

72/159

16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com­pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode).Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re­mains active.
0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Enable.

This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com­pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re­mains active.
0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active.
1: One Pulse Mode isactive, theICAP1pin can be

used totrigger one pulse on the OCMP1 pin;the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.

Bit 4 = PWM

Pulse Width Modulation.

0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis­ter.

Bit 3, 2 = CC1-CC0

Clock Control.

The value of the timer clock depends on these bits:

Table 17. Clock Control Bits

Bit 1 = IEDG2

Input Edge 2.

This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free runningcounter.
0: A falling edge triggers the freerunning counter.
1: A rising edge triggers the free running counter.

70

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Timer Clock CC1 CC0

f

CPU

/4 0 0

f

CPU

/2 0 1

f

CPU

/8 1 0

External Clock (where

available)

11

ST72311R, ST72511R, ST72512R, ST72532R

73/159

16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)

Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value).
1: An input capture has occurred or the counter

has reached the OC2R value in PWM mode. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the IC1R (IC1LR) regis­ter.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC1R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC1R (OC1LR) reg­ister.

Bit 5 = TOF

Timer Overflow.

0: No timer overflow (reset value).
1:The freerunning counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SRreg­ister, then read or write the low byte of the CR
(CLR) register.

Note: Reading or writing the ACLR register does
not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value).
1: An input capture has occurred.To clear this bit,

first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC2R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC2R (OC2LR) reg­ister.

Bit 2-0 = Reserved, forced by hardware to 0.

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register thatcontains the
high part of the counter value (transferred by the
input capture 1 event).

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register thatcontains the
low part of the counter value (transferred by the in­put capture 1 event).

OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)

Read/Write
Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.

OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)

Read/Write
Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.

70

ICF1 OCF1 TOF ICF2 OCF2 0 0 0

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

ST72311R, ST72511R, ST72512R, ST72532R

74/159

16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write
Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.

OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)

Read/Write
Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of
the value tobe compared to the CLR register.

COUNTER HIGH REGISTER (CHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

COUNTER LOW REGISTER (CLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the countervalue. A write to thisregisterresets the
counter. An access to this register after accessing
the SR register clears the TOF bit.

ALTERNATE COUNTER HIGH REGISTER
(ACHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

ALTERNATE COUNTER LOW REGISTER
(ACLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the counter value. A write to thisregister resets the
counter. An access to this register after anaccess
to SR register does not clear the TOF bit in SR
register.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register thatcontains the
high part of the counter value (transferred by the
Input Capture2 event).

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register thatcontains the
low part of the counter value(transferredby the In­put Capture 2 event).

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

70

MSB LSB

ST72311R, ST72511R, ST72512R, ST72532R

75/159

16-BIT TIMER (Cont’d)
Table 18. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

Timer A: 32
Timer B: 42

CR1

Reset Value

ICIE

0

OCIE

0

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

0

Timer A: 31
Timer B: 41

CR2

Reset Value

OC1E

0

OC2E

0

OPM

0

PWM

0

CC1

0

CC0

0

IEDG20EXEDG

0

Timer A: 33
Timer B: 43SRReset Value

ICF1

0

OCF1

0

TOF

0

ICF2

0

OCF2

0

-

0

-

0

-

0

Timer A: 34
Timer B: 44

ICHR1

Reset Value

MSB

-

------

LSB

-

Timer A: 35
Timer B: 45

ICLR1

Reset Value

MSB

-

------

LSB

-

Timer A: 36
Timer B: 46

OCHR1

Reset Value

MSB

-

------

LSB

-

Timer A: 37
Timer B: 47

OCLR1

Reset Value

MSB

-

------

LSB

-

Timer A: 3E
Timer B: 4E

OCHR2

Reset Value

MSB

-

------

LSB

-

Timer A: 3F
Timer B: 4F

OCLR2

Reset Value

MSB

-

------

LSB

-

Timer A: 38
Timer B: 48

CHR

Reset Value

MSB

1111111

LSB

1

Timer A: 39
Timer B: 49

CLR

Reset Value

MSB

1111110

LSB

0

Timer A: 3A
Timer B: 4A

ACHR

Reset Value

MSB

1111111

LSB

1

Timer A: 3B
Timer B: 4B

ACLR

Reset Value

MSB

1111110

LSB

0

Timer A: 3C
Timer B: 4C

ICHR2

Reset Value

MSB

-

------

LSB

-

Timer A: 3D
Timer B: 4D

ICLR2

Reset Value

MSB

-

------

LSB

-

ST72311R, ST72511R, ST72512R, ST72532R

76/159

5.6 SERIAL PERIPHERAL INTERFACE (SPI)

5.6.1 Introduction

The Serial Peripheral Interface (SPI) allows full­duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.

The SPI is normally used for communication be­tween themicrocontroller and external peripherals
or another microcontroller.

Refer to the Pin Description chapter for the device­specific pin-out.

5.6.2 Main Features

■ Full duplex, three-wiresynchronous transfers

■ Master or slave operation

■ Four master mode frequencies

■ Maximum slave mode frequency = fCPU/2.

■ Four programmable master bit rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collision flag protection

■ Master mode fault protection capability.

5.6.3 General description

The SPI is connected to external devices through
4 alternate pins:

– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin

A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 47.

The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).

When the master device transmits data to a slave
device via MOSIpin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de­vice via the SCK pin).

Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com­plete.

Four possible data/clock timing relationships may
be chosen (see Figure 50) but master and slave
must be programmed with the same timing mode.

Figure 47. Serial Peripheral Interface Master/Slave

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MOSI

MISO

SCK

SCK

SLAVE

MASTER

SS

SS

+5V

MSBit LSBit MSBit LSBit

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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 48. Serial Peripheral Interface Block Diagram

DR

Read Buffer

8-Bit Shift Register

Write

Read

Internal Bus

SPI

SPIE SPE SPR2 MSTR CPHA SPR0SPR1CPOL

SPIF

WCOL

MODF

SERIAL
CLOCK
GENERATOR

MOSI

MISO

SS

SCK

CONTROL

STATE

CR

SR

-

--

--

IT

request

MASTER

CONTROL

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4 Functional Description

Figure 47 shows the serial peripheral interface
(SPI) block diagram.

This interface contains 3 dedicated registers:

– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)

Refer to the CR, SR and DR registers in Section

5.6.7for the bit definitions.

5.6.4.1 Master Configuration

In a masterconfiguration, theserial clockisgener­ated on the SCK pin.

Procedure

– Select theSPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

– Select the CPOL and CPHA bits to define one

of the four relationships between the data
transfer and the serial clock (see Figure 50).

– The SSpin must be connected to a high level

signal during the complete byte transmit se­quence.

– The MSTRand SPE bits must be set (they re-

main set only if the SS pin is connected to a
high level signal).

In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.

Transmit sequence

The transmit sequencebegins when a byte is writ­ten the DR register.

The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shiftedout serially to the MOSI pin most
significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. WhentheDR register is read,
the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following
software sequence:

1.An access to the SR register while the SPIF bit
is set

2.A write or a read of the DR register.

Note: While theSPIF bit is set, all writes to the DR

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.2 Slave Configuration

In slave configuration, the serial clock is received
on the SCK pin from the master device.

The valueof the SPR0& SPR1 bits is not used for
the data transfer.

Procedure

– For correct data transfer, the slave device

must be in the same timing mode as the mas­ter device (CPOL and CPHA bits).See Figure

50.

– The SS pin must be connected to a low level

signal during the complete byte transmit se­quence.

– Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

In this configuration the MOSI pin is a data input
and the MISO pin is a data output.

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.

The transmit sequence begins when the slave de­vice receives the clock signal andthe most signifi­cant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. WhentheDR register is read,
the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following
software sequence:

1.An access to the SR register while the SPIF bit
is set.

2.A write or a read of the DR register.

Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.

The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 5.6.4.6).

Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section

5.6.4.4).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.3 Data Transfer Format

During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used tosyn­chronize the data transfer during a sequence of
eight clock pulses.

The SS pin allows individual selection of a slave
device; theother slave devices that are notselect­ed do not interfere with the SPI transfer.

Clock Phase and Clock Polarity

Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.

The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.

The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.

Figure 50, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di­agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.

The SSpin is the slave device select input and can
be driven by the master device.

The master device applies data to its MOSI pin­clock edge before the capture clock edge.

CPHA bitis set

The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.

No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 49).

CPHA bitis reset

The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc­currence of the second clock transition.

This pin must be toggled high and low between
each byte transmitted (see Figure 49).

To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.

Figure 49. CPHA / SS Timing Diagram

MOSI/MISO

Master

SS

Slave SS

(CPHA=0)

Slave

SS

(CPHA=1)

Byte 1 Byte 2

Byte 3

VR02131A

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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 50. Data Clock Timing Diagram

CPOL = 1

CPOL = 0

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =1

CPOL = 1

CPOL = 0

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

SS

(to slave)

CAPTURE STROBE

CPHA =0

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

VR02131B

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.4 Write Collision Error

A write collision occurs when the software tries to
write tothe DR register while a data transfer is tak­ing place with an external device. When this hap­pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.

Write collisionscan occur both inmaster andslave
mode.

Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is alwayssynchronous with the MCU oper­ation.

In Slave mode

When the CPHA bit is set:
The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter­nal MISO pin of the slave device.

The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.

When the CPHA bit is reset:
Data is latched on the occurrence of the first clock

transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.

For this reason, the SS pin mustbe high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli­sion.

In Master mode

Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.

The SS pin signal must be always high on the
master device.

WCOL bit

The WCOL bit in the SR register is set if a write
collision occurs.

No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software
sequence (see Figure 51).

Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SR

Read DR Write DR

2nd Step

SPIF =0
WCOL=0

SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

before the 2nd step

Read SR

Read DR

Note: Writing in DR register in­stead of reading in it do not reset
WCOL bit

Read SR

OR

THEN

THEN

THEN

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.5 Master Mode Fault

Master mode fault occurs when the master device
has itsSS pin pulled low, then the MODF bit isset.

Master modefault affects theSPI peripheral in the
following ways:

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph­eral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software
sequence:

1. A read or write access to the SR register while
the MODF bit is set.

2. A write to the CR register.

Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se­quence of the MODF bit. The SPE and MSTR bits

may be restored to their original state during or af­ter this clearing sequence.

Hardware does not allow the user to set the SPE
and MSTR bits while the MODFbit is set except in
the MODF bit clearing sequence.

In a slave device the MODF bit can not be set, but
in a multi master configuration the device canbe in
slave mode with this MODF bit set.

The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from system operation to a re­set or default system state using an interrupt rou­tine.

5.6.4.6 Overrun Condition

An overrun condition occurs, when the master de­vice has sent several data bytes and the slavede­vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.

In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.

This condition is not detected by the SPI peripher­al.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems:
– Single Master System
– Multimaster System

Single Master System

A typical single master systemmay be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 52).

The master device selects the individual slave de­vices byusing four pins of a parallel port to control
the four SS pins of the slave devices.

The SS pinsare pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line
the master allows only one slave device during a
transmission.

For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte backfrom the
slave device if all MISO and MOSI pins are con­nected and the slave has not written its DR regis­ter.

Other transmission security methods can use
ports for handshake lines or data bytes with com­mand fields.

Multi-master System

A multi-master system may also be configured by
the user. Transfer of master control could be im­plemented using a handshake methodthrough the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.

The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.

Figure 52. Single Master Configuration

MISO

MOSI

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS

SS

SS

SS

SS

SCK SCK

SCK

SCK

SCK

5V

Ports

Slave

MCU

Slave

MCU

Slave
MCU

Slave

MCU

Master
MCU

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.5 Low Power Modes

5.6.6 Interrupts

Note: The SPI interrupt events are connected to

the sameinterrupt vector(see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and the I-bit intheCCreg­ister is reset (RIM instruction).

Mode Description

WAIT

No effect on SPI.
SPI interrupt events cause the device to exit fromWAIT mode.

HALT

SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of Transfer Event SPIF

SPIE

Yes No

Master Mode Fault Event MODF Yes No

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SERIAL PERIPHERAL INTERFACE (Cont’d)

5.6.7 Register Description

CONTROL REGISTER (CR)

Read/Write
Reset Value: 0000xxxx (0xh)

Bit 7 = SPIE

Serial peripheral interrupt enable.

This bit is set and cleared bysoftware.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 6 = SPE

Serial peripheral output enable.

This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 5.6.4.5 Master Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins

The SPEbit is cleared by reset, so the SPI periph­eral is not initially connected to the external pins.

Bit 5 = SPR2

Divider Enable

.

this bit is set and cleared by software and it is
cleared by reset. It is usedwith the SPR[1:0] bits to
set the baud rate. Refer to Table 19.
0: Divider by 2 enabled
1: Divider by 2 disabled

Bit 4 = MSTR

Master.

This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 5.6.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the

SCK pin changes from an input to an output and
the functions of the MISO and MOSI pinsare re­versed.

Bit 3 = CPOL

Clock polarity.

This bit is set and cleared by software. This bit de­termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady stateis a high value at the SCK pin.

Bit 2 = CPHA

Clock phase.

This bit is set andcleared by software.
0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 1:0 = SPR[1:0]

Serial peripheral rate.

These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.

These 2 bits have no effect in slave mode.

Table 19. Serial Peripheral Baud Rate

70

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Serial Clock SPR2 SPR1 SPR0

f

CPU

/2 1 0 0

f

CPU

/8 0 0 0

f

CPU

/16 0 0 1

f

CPU

/32 1 1 0

f

CPU

/64 0 1 0

f

CPU

/128 0 1 1

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SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)

Read Only
Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheraldata transfer flag.

This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft­ware sequence (an access to the SR register fol­lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

1: Data transfer between thedevice and an exter-

nal device has been completed.

Note: Whilethe SPIF bit isset, all writes to the DR
register are inhibited.

Bit 6 = WCOL

Write Collision status.

This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 51).
0: No write collision occurred
1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF

Mode Fault flag.

This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 5.6.4.5
Master Mode Fault). An SPI interrupt can be gen­erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected

Bits 3-0 = Unused.

DATA I/O REGISTER (DR)

Read/Write
Reset Value: Undefined

The DR register is used to transmit and receive
data on the serialbus. In the master device only a
write to this register will initiate transmission/re­ception of another byte.

Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serialperipheral data I/O register, the buffer is
actually being read.

Warning:

A write to the DR register places data directly into
the shift register fortransmission.

A write to the the DR register returns the value lo­cated inthe bufferand not the contents of the shift
register (See Figure 48 ).

70

SPIF WCOL - MODF - - - -

70

D7 D6 D5 D4 D3 D2 D1 D0

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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 20. SPI Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

0021h

SPIDR

Reset Value

MSB

xxxxxxx

LSB

x

0022h

SPICR

Reset Value

SPIE

0

SPE

0

SPR20MSTR

0

CPOL

x

CPHA

x

SPR1

x

SPR0

x

0023h

SPISR

Reset Value

SPIF

0

WCOL

00

MODF

00000

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5.7 SERIAL COMMUNICATIONSINTERFACE (SCI)

5.7.1 Introduction

The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serialdata format.The SCI of­fers a very wide range of baud rates using two
baud rate generator systems.

5.7.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

■ Independently programmable transmit and

receive baud rates up to 250K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)
– Idle line

■ Mutingfunctionformultiprocessorconfigurations

■ Separate enable bits for Transmitter and

Receiver

■ Three error detection flags:

– Overrun error
– Noise error
– Frame error

■ Five interrupt sources with flags:

– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected

5.7.3 General Description

The interface is externally connected to another
device by two pins (see Figure 54):

– TDO: TransmitData Output.When the transmit-

ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena­bled and nothing is to be transmitted, the TDO
pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re­covery by discriminating between valid incoming
data and noise.

Through this pins, serialdata is transmittedand re­ceived as frames comprising:

– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– A conventional type for commonly-used baud

rates,

– An extended typewitha prescaler offeringa very

wide rangeofbaudrates even withnon-standard
oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 53. SCI Block Diagram

WAKE

UP

UNIT

RECEIVER

CONTROL

SR

TRANSMIT

CONTROL

TDRE TC RDRF

IDLE OR NF FE -

SCI

CONTROL

INTERRUPT

CR1

R8

T8

-

M

WAKE

-

--

Received Data Register (RDR)

Received Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER)DR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

BRR

SCP1

f

CPU

CONTROL

CONTROL

SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0

/2 /PR

/16

CONVENTIONAL BAUD RATE GENERATOR

SBKRWURETEILIERIETCIETIE

CR2

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.4 Functional Description

The block diagram of the Serial Control Interface,
is shown in Figure 53. It contains 6 dedicated reg­isters:

– Two control registers (CR1 & CR2)
– A status register (SR)
– A baud rate register (BRR)
– An extended prescaler receiver register (ERPR)
– Anextendedprescalertransmitterregister(ETPR)
Refer to the register descriptions in Section

5.7.7for the definitions of each bit.

5.7.4.1 Serial Data Format

Word lengthmay be selected as being either 8or 9
bits by programming the M bit in the CR1 register
(see Figure 53).

The TDOpin is in low state during the start bit.
The TDOpin is in high state during the stop bit.
An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame
which contains data.

A Break character is interpreted on receiving “0”s
for some multiple of theframe period.At the end of
the last break frame the transmitter inserts an ex­tra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their
own baud rate generator.

Figure 54. Word length programming

Bit0 Bit1

Bit2

Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

Start

Bit

Stop

Bit

Next

Start

Bit

Idle Frame

Bit0 Bit1

Bit2

Bit3 Bit4

Bit5 Bit6

Bit7

Start

Bit

Stop

Bit

Next

Start

Bit

Start

Bit

Idle Frame

Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame

Start

Bit

Extra

’1’

Data Frame

Break Frame

Start

Bit

Extra

’1’

Data Frame

Next Data Frame

Next Data Frame

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.4.2 Transmitter

The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) hasto be stored in the T8 bit in the CR1 reg­ister.

Character Transmission

During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DRregister consists of abuffer (TDR) between
the internal bus and the transmit shift register (see
Figure 53).

Procedure

– Select the M bit to define the word length.
– Select the desiredbaud rate using theBRR and

the ETPR registers.

– Set the TE bit to assign the TDO pinto the alter-

nate function and to send a idle frame as first
transmission.

– Access the SR register and write the data to

send in theDR register (this sequence clears the
TDRE bit).Repeat thissequencefor each datato
be transmitted.

Clearing the TDRE bit is always performed by the
following software sequence:

1. An access to the SR register

2. A write to the DR register

The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register

without overwriting the previous data.

This flag generates an interruptif the TIE bit is set
and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in­struction to the DR register stores the data in the
TDR register and which is copied in the shift regis­ter at the end of the current transmission.

When no transmission is taking place, a write in­struction tothe DRregister places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.

When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if theTCIE is set and
the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following
software sequence:

1. An access to the SR register

2. A write to the DR register
Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 54).

As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle
frame before the first data frame.

Clearing and then settingthe TE bit during a trans­mission sends an idle frame after thecurrent word.

Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte inthe DR.

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.4.3 Receiver

The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB isstored in the R8 bit in the CR1 reg­ister.

Character reception

During a SCI reception, data shifts in least signifi­cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in­ternal bus and the received shift register (see Fig­ure 53).

Procedure

– Select the M bit to define the word length.
– Select the desiredbaud rate using theBRR and

the ERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise

or anoverrun errorhas been detected during re-

ception.
Clearing theRDRF bit isperformed by thefollowing

software sequence done by:

1. An access to the SR register

2. A read to the DR register.
The RDRFbit mustbe cleared beforetheendofthe

reception of the next character to avoid anoverrun
error.

Break Character

When a break character is received, the SPI han­dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same
procedure as a data received character plus an in­terrupt if theILIE bit is set and the I bit is cleared in
the CCR register.

Overrun Error

An overrun error occurs when a character is re­ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.

When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– Aninterrupt is generated ifthe RIE bitis set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to theSR register
followed by a DR register read operation.

Noise Error

Oversampling techniques are used for data recov­ery by discriminating between valid incoming data
and noise.

When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shiftregister to the

DR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself
generates an interrupt.

The NF bitis reset by a SR register read operation
followed by a DR register read operation.

Framing Error

A framing error is detected when:
– Thestop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shiftregister to the

DR register.
– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.
The FE bit is reset by a SR register read operation

followed by a DR register read operation.

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER

RECEIVER

ETPR

ERPR

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTERRATE CONTROL

EXTENDED PRESCALER

CLOCK

CLOCK

RECEIVER RATE

TRANSMITTER RATE

BRR

SCP1

f

CPU

CONTROL

CONTROL

SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0

/2 /PR

/16

CONVENTIONAL BAUD RATE GENERATOR

EXTENDEDRECEIVER PRESCALER REGISTER

EXTENDEDTRANSMITTER PRESCALERREGISTER

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:

with:
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f

CPU

is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.

Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiverisen­abled.

5.7.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine
tuning onthe baud rate, using a 255 value prescal­er, whereas the conventional Baud Rate Genera­tor retains industry standard software compatibili­ty.

The extended baud rate generator block diagram
is described in the Figure 55.

The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided bya factor ranging from 1 to 255 set in the
ERPR or theETPR register.

Note: the extended prescaler is activated by set­ting the ETPR or ERPR register to a value other

than zero. The baud rates are calculated as fol­lows:

with:
ETPR = 1,..,255 (see ETPR register)
ERPR = 1,.. 255 (see ERPR register)

5.7.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira­ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.

The non addressed devices may be placed in
sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in
sleep mode:

All the reception status bits can not be set.
All the receive interrupt are inhibited.
A mutedreceiver may be awakened by one of the

following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by AddressMark detectionif the WAKEbitisset.
Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.

Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating thatthe message is an ad­dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows thereceiver to receive this
word normally and to use it as an addressword.

Tx =

(32*PR)*TR

f

CPU

Rx =

(32*PR)*RR

f

CPU

Tx =

16*ETPR

f

CPU

Rx =

16*ERPR

f

CPU

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.5 Low Power Modes

5.7.6 Interrupts

The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corre­sponding Enable Control Bit is set and the I-bit in
the CC register is reset (RIM instruction).

Mode Description

WAIT

No effect on SCI.
SCI interrupts cause the device to exitfrom Wait mode.

HALT

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Transmit Data Register Empty TDRE TIE Yes No
Transmission Complete TC TCIE Yes No
Received Data Ready to be Read RDRF

RIE

Yes No
Overrrun Error Detected OR Yes No
Idle Line Detected IDLE ILIE Yes No

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.7.7 Register Description
STATUS REGISTER (SR)

Read Only
Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se­quence (an access to the SR register followed by a
write to the DR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register

Note: data will not be transferred to the shift regis­ter as long as the TDRE bit is not reset.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se­quence (an access to the SR register followed by a
write to the DR register).
0: Transmission is not complete
1: Transmission is complete

Bit 5 = RDRF

Received data ready flag.

This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 orbya software sequence (an access to the
SR register followed by a readto the DR register).
0: Data is not received
1: Received data is ready to be read

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a Idle Line is de­tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a readto the DR register).
0: No Idle Line is detected
1: Idle Lineis detected

Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc­curs). This bit isnotset by an idle line whenthe re­ceiver wakes up from wake-up mode.

Bit 3 = OR

Overrun error.

This bit is set by hardware whenthe wordcurrently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg­ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
1: Overrun error is detected

Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed bya read to theDR regis­ter).
0: No noise is detected
1: Noise is detected

Note: This bit does not generate interrupt as it ap­pears at the same time as the RDRF bit which it­self generates an interrupt.

Bit 1 = FE

Framing error.

This bit isset by hardware whena de-synchroniza­tion, excessive noise or a break character is de­tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Framing error is detected
1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap­pears at the same time as the RDRF bit which it­self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only theOR
bit will be set.

Bit 0 = Unused.

70

TDRE TC RDRF IDLE OR NF FE -

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)

Read/Write
Reset Value: Undefined

Bit 7 = R8

Receive data bit 8.

This bit is used to store the 9th bit of the received
word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store the 9th bit of the transmit­ted word when M=1.

Bit 4 = M

Word length.

This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark

CONTROL REGISTER 2 (CR2)

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7 = TIE

Transmitter interrupt enable

.
This bit is set and cleared bysoftware.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever

TDRE=1 in the SR register.

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared bysoftware.
0: interrupt is inhibited

1: AnSCI interruptis generated whenever TC=1 in

the SR register

Bit 5 = RIE

Receiver interrupt enable

.
This bit is set andcleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set andcleared by software.
0: interrupt is inhibited
1: An SCIinterrupt is generated whenever IDLE=1

in the SR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to

the I/O port configuration.

1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the
current word.

Bit 2 = RE

Receiver enable.

This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of theSR register.

1: Receiver is enabled and begins searching for a

start bit.

Bit 1 = RWU

Receiver wake-up.

This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode

Bit 0 = SBK

Send break.

This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted

Note: If the SBK bit issetto “1”and thento“0”, the
transmitter will send a BREAK word at the end of
the current word.

70

R8 T8 - M WAKE - -

-

70

TIE TCIE RIE ILIE TE RE RWU

SBK

ST72311R, ST72511R, ST72512R, ST72532R

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)

Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-

acter, depending onwhether it is read from or writ­ten to.

The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg­ister (see Figure 53).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure53).

BAUD RATE REGISTER (BRR)

Read/Write
Reset Value: 00xx xxxx (XXh)

Bit 7:6= SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard
clock division ranges:

Bit 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1& SCP0
bits define the total division applied to the bus
clock to yield thetransmit rate clock inconvention­al Baud Rate Generator mode.

Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.

Bit 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP1& SCP0
bits define the total division applied to the bus
clock to yield thereceive rate clock in conventional
Baud Rate Generator mode.

Note: this RR factor is used only when the ERPR
fine tuningfactor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.

70

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

70

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

PR Prescaling factor SCP1 SCP0

100
301
410

13 1 1

TR dividingfactor SCT2 SCT1 SCT0

1 000
2 001
4 010

8 011
16 100
32 101
64 110

128 1 1 1

RR dividingfactor SCR2 SCR1 SCR0

1 000

2 001

4 010

8 011
16 100
32 101
64 110

128 1 1 1

ST72311R, ST72511R, ST72512R, ST72532R

100/159

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION

REGISTER (ERPR)

Read/Write
Reset Value: 0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-

sion factor for the receive circuit.

Bit 7:1 = ERPR[7:0]

8-bit Extended ReceivePres-

caler Register.

The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 55) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).

The extended baud rate generator is not used af­ter a reset.

EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)

Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate divi-

sion factor for the transmit circuit.

Bit 7:1 = ETPR[7:0]

8-bit ExtendedTransmitPres-

caler Register.

The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 55) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).

The extended baud rate generator is not used af­ter a reset.

Table 21. SCI Register Map and Reset Values

70

ERPR7ERPR6ERPR5ERPR4ERPR3ERPR2ERPR1ERPR

0

70

ETPR7ETPR6ETPR5ETPR4ETPR3ETPR2ETPR1ETPR

0

Address

(Hex.)

Register

Label

76543210

0050h

SCISR

Reset Value

TDRE

1

TC

1

RDRF

0

IDLE

0

OR

0

NF

0

FE

00

0051h

SCIDR

Reset Value

MSB

xxxxxxx

LSB

x

0052h

SCIBRR

Reset Value

SCP1

0

SCP0

0

SCT2

0

SCT1

0

SCT0

0

SCR2

0

SCR1

0

SCR0

0

0053h

SCICR1

Reset Value

R8

x

T8

x0

M

x

WAKE

x000

0054h

SCICR2

Reset Value

TIE

0

TCIE

0

RIE

0

ILIE

0

TE

0

RE

0

RWU

0

SBK

0

0055h

SCIERPR

Reset Value

MSB

0000000

LSB

0

0057h

SCIETPR

Reset Value

MSB

0000000

LSB

0