Datasheet ST72C104G2, ST72C104G1, ST72C254G2, ST72C254G1, ST72C216G1 Datasheet (SGS Thomson Microelectronics)
...
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, I
■ Memories
– 4K or 8K bytes Program memory (ROM and
single voltage FLASH) with read-out protection and in-situ programming (remote ISP)
– 256 bytes RAM
■ Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– Clock-out capability
– 3 Power SavingModes: Halt, Wait and Slow
■ Interrupt Management
– 7 interrupt vectors plus TRAP and RESET
– 22 external interrupt lines (on 2 vectors)
■ 22 I/O Ports
– 22 multifunctional bidirectional I/O lines
– 14 alternate function lines
– 8 high sink outputs
■ 3 Timers
– Configurable watchdog timer
– Two 16-bittimers with: 2 input captures, 2out-
put compares,externalclock inputonone tim-
er, PWM and Pulse generator modes
(one only on ST72104Gx and ST72216G1)
■ 2 Communications Interfaces
– SPI synchronous serial interface
– I2C multimaster interface
(only on ST72254Gx)
■ 1 Analog peripheral
– 8-bit ADC with 6 input channels
(except on ST72104Gx)
ST72104G, ST72215G,
ST72216G, ST72254G
2
C INTERFACES
PRELIMINARY DATA
SDIP32
SO28
■ InstructionSet
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■ Development Tools
– Full hardware/softwaredevelopment package
Device Summary
Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2
Program memory - bytes 4K 8K 4K 8K 4K 8K
RAM (stack) - bytes 256 (128)
Peripherals
Operating Sup ply 3.0V to 5.5V
CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz)
Operating Temp erature -40°C to +85°C (-40°C to +105/125°C optional)
Packages SO28 / SDIP 32
Watchdog timer,
One 16-bit timer,
SPI
Watchdog timer,
One 16-bit timer,
SPI, ADC
Watchdog timer,
Two 16-bit timers,
SPI, ADC
Watchdog timer,
Two 16-bit timers,
SPI, I C, ADC
Rev. 2.2
February 2000 1/135
This ispreliminary information on anew product in development or undergoing evaluation. Details are subject tochange without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . ......................................... 6
2 PIN DESCRIPTION . . . . . . . . . . . . ................................................ 7
3 REGISTER & MEMORY MAP . . . ................................................10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . ................................. 13
4.1 INTRODUCTION . ...................................................... 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 13
4.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . ........................... 13
4.4 IN-SITU PROGRAMMING (ISP) MODE . .................................... 13
4.5 MEMORY READ-OUT PROTECTION . . . . . ................................. 13
5 CENTRAL PROCESSING UNIT . . ............................................... 14
5.1 INTRODUCTION . ...................................................... 14
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 14
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . ................................. 14
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . ................................17
6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . .................................18
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . ................................19
6.2.1 Introduction . . . .................................................... 19
6.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 20
6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . ........20
6.2.4 Internal Watchdog RESET . . . . . . . . . . .................................. 20
6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . ................................21
6.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . ................................22
6.4.1 Clock Filter Control . . ...............................................22
6.4.2 Safe Oscillator Control . . . . ...........................................22
6.4.3 Low Power Modes . . ............................................... 22
6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 22
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . ........ 23
6.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . ........................... 24
7 INTERRUPTS . . ............................................................. 25
7.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . ........................... 25
7.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . .................................. 25
7.3 PERIPHERAL INTERRUPTS . . ........................................... 25
8 POWER SAVING MODES . . . . . . . . . . ...........................................27
8.1 INTRODUCTION . ...................................................... 27
8.2 SLOW MODE . . . . . . . . . . . . . . ...........................................27
8.3 WAIT MODE . . . . . . . . . . . ............................................... 28
8.4 HALT MODE . . . . . . . . . . . ...............................................29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................ 30
9.1 INTRODUCTION . ...................................................... 30
9.2 FUNCTIONAL DESCRIPTION . . . . ........................................30
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . ................................. 30
9.2.2 Output Modes . . . . . . ............................................... 30
9.2.3 Alternate Functions . . ...............................................30
9.3 I/O PORT IMPLEMENTATION . . . . ........................................33
135
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Table of Contents
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . ................................. 34
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . ................................. 34
9.6 REGISTER DESCRIPTION . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 36
10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . ................................36
10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . .................................. 36
10.3 MISCELLANEOUS REGISTERDESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 ON-CHIP PERIPHERALS . . . . . . ............................................... 39
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . ........................... 39
11.1.1Introduction . . . . ................................................... 39
11.1.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 39
11.1.3Functional Description . . . . . . . ........................................ 39
11.1.4Hardware Watchdog Option . . . . . . . . . . . ................................40
11.1.5Low Power Modes . . . ...............................................40
11.1.6Interrupts . . . . . . .. . . . . . .. . . . . . . . . . . ................................ 40
11.1.7Register Description . . . . . . . . . ........................................ 40
11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 42
11.2.1Introduction . . . . ................................................... 42
11.2.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 42
11.2.3Functional Description . . . . . . . ........................................ 42
11.2.4Low Power Modes . . ............................................... 54
11.2.5Interrupts . . . . . ....................................................54
11.2.6Summary of Timer modes . . . . . . . . . . . . . . . . . ........................... 54
11.2.7Register Description . . . . . . . . . ........................................ 55
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . .................................. 60
11.3.1Introduction . . . . ................................................... 60
11.3.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 60
11.3.3General description . . . . . . ...........................................60
11.3.4Functional Description . . . . . . . ........................................ 62
11.3.5Low Power Modes . . . ...............................................69
11.3.6Interrupts . . . . . ....................................................69
11.3.7Register Description . . . . . . . . . ........................................ 70
11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . ....................................73
11.4.1Introduction . . . . ................................................... 73
11.4.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 73
11.4.3General Description . . . . . . . . . ........................................73
11.4.4Functional Description . . . . . . . ........................................ 75
11.4.5Low Power Modes . . . ...............................................79
11.4.6Interrupts . . . . . . .. . . . . . .. . . . . . . . . . . ................................ 79
11.4.7Register Description . . . . . . . . . ........................................ 80
11.5 8-BIT A/D CONVERTER (ADC) ........................................... 86
11.5.1Introduction . . . . ................................................... 86
11.5.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 86
11.5.3Functional Description . . . . . . . ........................................ 86
11.5.4Low Power Modes . . ............................................... 87
11.5.5Interrupts . . . . . . .. . . . . . .. . . . . . . . . . . ................................ 87
11.5.6Register Description . . . . . . . . . ........................................ 88
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ST72104G, ST72215G, ST72216G, ST72254G
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . .................................90
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.1Inherent . . . . .. . . . . . . . . . . . . . . . . . . . ................................. 91
12.1.2Immediate . . ...................................................... 91
12.1.3Direct . ........................................................... 91
12.1.4Indexed (No Offset, Short,Long) . . . . . .................................. 91
12.1.5Indirect (Short, Long) . . . . . ...........................................91
12.1.6Indirect Indexed (Short, Long) . ........................................92
12.1.7Relative mode (Direct, Indirect) . . . . ....................................92
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . .............................. 93
13 ELECTRICAL CHARACTERISTICS . . . . ......................................... 96
13.1 PARAMETER CONDITIONS . . . . . . . . .. . . . . . . .............................. 96
13.1.1Minimum and Maximum values ........................................96
13.1.2Typical values . . . . . . . . . . ...........................................96
13.1.3Typical curves . . . . . . . . . . . . . ........................................96
13.1.4Loading capacitor . . . . . . . . . . . . . . . . . .................................. 96
13.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.1Voltage Characteristics . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.2Current Characteristics . . . . . . . . . . . . . . . . .............................. 97
13.2.3Thermal Characteristics . . . . . . . . . .................................... 97
13.3 OPERATING CONDITIONS . . . . . . . . . . .................................... 98
13.3.1General Operating Conditions . . . . .................................... 98
13.3.2Operating Conditions with Low Voltage Detector (LVD) . .................... 99
13.4 SUPPLY CURRENT CHARACTERISTICS . . . ...............................101
13.4.1RUN and SLOW Modes . . . . . .......................................101
13.4.2WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 102
13.4.3HALT Mode . . . . . . . . .............................................. 103
13.4.4Supply and Clock Managers . ........................................ 103
13.4.5On-Chip Peripherals . . . . . ..........................................103
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . ..........104
13.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.2External Clock Source . . . . . . .......................................104
13.5.3Crystal and Ceramic Resonator Oscillators . . . . .......................... 105
13.5.4RC Oscillators . . . . . . . . . . ..........................................106
13.5.5Clock Security System (CSS) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.6 MEMORY CHARACTERISTICS . . . .......................................108
13.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . .............. 108
13.6.2FLASH Program Memory . . . . .......................................108
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . 109
13.7.1Functional EMS . . . . . .............................................. 109
13.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . .......................... 110
13.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.8 I/O PORT PIN CHARACTERISTICS .......................................114
13.8.1General Characteristics . . . . . . . . . . . . ................................. 114
13.8.2Output Driving Current . . . . .......................................... 115
13.9 CONTROL PIN CHARACTERISTICS . . . . . ................................. 117
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ST72104G, ST72215G, ST72216G, ST72254G
13.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . .......................... 117
13.9.2ISPSEL Pin ...................................................... 119
13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 120
13.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 120
13.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . ................................ 120
13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . ................... 121
13.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . ..........................121
13.11.2I2C - Inter IC ControlInterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........123
13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . ................................. 124
14 PACKAGE CHARACTERISTICS . . . . . . ........................................ 126
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . ............................. 126
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . .. . ................... 127
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . .. . . . . . . . . . . . . . . . . ....... 128
14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . ................... 128
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 129
15.1 OPTION BYTES . . . ................................................... 129
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 130
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . .......................... 132
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . .................................133
15.5 TO GET MORE INFORMATION . . . .......................................133
16 SUMMARY OF CHANGES . ..................................................134
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ST72104G, ST72215G, ST72216G, ST72254G
1 INTRODUCTION
The ST72104G, ST72215G, ST72216G and
ST72254G devices are members of the ST7 microcontroller family. They can be grouped as follows:
– ST72254G devices are designed for mid-range
applications with ADC and I C interface capabilities.
– ST72215/6G devices target the same range of
applications but without I C interface.
– ST72104G devices are for applications that do
not need ADC and I C peripherals.
All devices are based on a c ommon industrystandard 8-bit core, featuringan enhanced instruction set.
The ST72C104G, ST72C215G, ST72C216G and
ST72C254G versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Programming (ISP) capability.
Figure 1. General Block Diagram
Internal
OSC1
OSC2
V
DD
V
RESE T
SS
MULTI O SC
+
CLOCK FILTE R
LVD
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
PROGRAM
MEMORY
(4 or 8K Bytes)
CLOCK
Under software control, all devices can be placed
in WAIT, SLOW, or HALT mode, reducing power
consumption when the application is in idle or
standby state.
The enhanced instruction set and a ddressing
modes of the ST7 offer both power and flexibilityto
software developers, enabling the design ofhighly
efficient andcompact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in Section 13 on page 96.
I2C
PA7:0
(8 bits)
PB7:0
(8 bits)
PC5:0
(6 bits)
ADDRESS AND DATABUS
PORT A
SPI
PORT B
16-BIT TIMER A
PORT C
8-BIT AD C
16-BIT TIMER B
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4
RAM
(256 Bytes)
WA TCHDOG
2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
ST72104G, ST72215G, ST72216G, ST72254G
RESET
OSC1
OSC2
SS/PB7
ISPCLK/SCK/PB6
ISPDATA/MISO/PB5
MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
Figure 3. 32-Pin SDIP Package Pinout
RESET
OSC1
OSC2
SS/PB7
ISPCLK/SCK/PB6
ISPDATA/MISO/PB5
MOSI/PB4
NC
NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ei1 ei0
ei0 or ei1
ei0
ei1
ei0
ei1
ei0or ei1
V
28
DD
V
27
SS
ISPSEL
26
PA0 (HS)
25
PA1 (HS)
24
PA2 (HS)
23
PA3 (HS)
22
PA4 (HS)/SCLI
21
20
PA5 (HS)
19
PA6 (HS)/SDAI
PA7 (HS)
18
PC0/ICAP1_B/AIN0
17
PC1/OCMP1_B/AIN1
16
PC2/MCO/AIN2
15
(HS) 20mA highsink capability
eiX associated external interruptvector
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DD
V
SS
ISPSEL
PA0 (HS)
PA1 (HS)
PA2 (HS)
PA3 (HS)
NC
NC
PA4 (HS)/SCLI
PA5 (HS)
PA6 (HS)/SDAI
PA7 (HS)
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/MCO/AIN2
(HS) 20mA highsink capability
eiX associated external interruptvector
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ST72104G, ST72215G, ST72216G, ST72254G
PIN DESCRIPTION (Cont’d)
For externalpin connection guidelines, refer to Section 13 ”ELECTRICAL CHARACTERISTICS” on page
96.
Legend / Abbreviationsfor Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDDwith input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt1), ana = analog
– Output: OD = open drain2), PP = push-pull
Refer toSection 9 ”I/O PORTS” on page 30 for more details on the softwareconfiguration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as thedevice is
in reset state.
Table 1. Device Pin Description
Pin n°
Pin Name
SO28
SDIP32
1 1 RESET I/O C
2 2 OSC1
3 3 OSC2
4 4 PB7/SS I/O C
5 5 PB6/SCK/ISPCLK I/O C
6 6 PB5/MISO/ISPDATA I/O C
7 7 PB4/MOSI I/O C
8NC
9NC
10 8 PB3/OCMP2_A I/O C
11 9 PB2/ICAP2_A I/O C
12 10 PB1 /OCMP1_A I/O C
13 11 PB0 /ICAP1_A I/O C
14 12 PC5/EXTCLK_A/AIN5 I/O C
15 13 PC4/OCMP2_B/AIN4 I/O C
16 14 PC3/ ICAP2_B/AIN3 I/O C
17 15 PC2/MCO/AIN2 I/O C
3)
3)
Level Port / Control
Type
T
I
O
Input
T
T
T
T
T
T
T
T
T
T
T
T
Input Output
Output
float
X ei1 X X Port B7 SPI Slave Select (active low)
X ei1 X X Port B6 SPI Serial Clock or ISP Clock
X ei1 X X Port B5
X ei1 X X Port B4 SPI Master Out / Slave In Data
X ei1 X X Port B3 Timer A Output Compare 2
X ei1 X X Port B2 Timer A Input Capture 2
X ei1 X X Port B1 Timer A Output Compare 1
X ei1 X X Port B0 Timer A Input Capture 1
X ei0/ei1 X X Port C5
X ei0/ei1 X X Port C4
X ei0/ei1 X X X Port C3
X ei0/ei1 X X X Port C2
int
wpu
X X Toppriority nonmaskable interrupt (active low)
ana
OD
Not Connected
Main
Function
(after reset)
PP
External clock input or Resonator oscillator inverter input or resistor input for RC oscillator
Resonator oscillator inverter output or capacitor input for RC oscillator
Alternate Function
SPI Master In/ Slave OutData
or ISP Data
Timer A Input Clock or ADC
Analog Input 5
Timer B Output Compare 2 or
ADC Analog Input 4
Timer B Input Capture 2 or
ADC Analog Input 3
Main clock output (f
ADC Analog Input 2
CPU
)or
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ST72104G, ST72215G, ST72216G, ST72254G
Pin n°
Level Port / Control
Pin Name
Type
SO28
SDIP32
18 16 PC1/OCMP1_B/AIN1 I/O C
19 17 PC0/ICAP1_B/AIN0 I/O C
20 18 PA7 I/O C
21 19 PA6 /SDAI I/O C
22 20 PA5 I/O C
23 21 PA4 /SCLI I/O C
Input
Output
T
T
HS X ei0 X X Port A7
T
HS X ei0 T Port A6 I2C Data
T
HS X ei0 X X Port A5
T
HS X ei0 T Port A4 I2C Clock
T
24 NC
25 NC
26 22 PA3 I/O C
27 23 PA2 I/O C
28 24 PA1 I/O C
29 25 PA0 I/O C
HS X ei0 X X Port A3
T
HS X ei0 X X Port A2
T
HS X ei0 X X Port A1
T
HS X ei0 X X Port A0
T
30 26 ISPSEL I C X
31 27 V
32 28 V
SS
DD
S Ground
S Main power supply
Input Output
Function
(after reset)
Main
float
wpu
int
ana
OD
PP
X ei0/ei1 X X X Port C1
X ei0/ei1 X X X Port C0
Not Connected
In situ programming selection (Should be tied
low in standard user mode).
Alternate Function
Timer B Output Compare 1 or
ADC Analog Input 1
Timer B Input Capture 1 or
ADC Analog Input 0
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu)is merged with theinterruptcolumn (int), then the I/O configuration is pull-up interruptinput,
else the configuration is floating interrupt input.
2. Inthe open drain output column, “T” defines a true open drain I/O(P-Buffer and protection diode to V
are not implemented). See Section 9 ”I/O PORTS” on page 30 and Section 13.8 ”I/O PORT PIN CHAR-
DD
ACTERISTICS” on page 114 for more details.
3. OSC1 andOSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chiposcillatorsee Section 2 ”PIN DESCRIPTION” onpage 7 and Section 13.5 ”CLOCK AND TIMING CHARACTERISTICS” on page 104 for more details.
9/135
ST72104G, ST72215G, ST72216G, ST72254G
3 REGISTER & MEMORY MAP
As shown in the Figure 4, the MCU is capable of
addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register location, 256 bytes of RAM and
up to 8Kbytes of user program memory. The RAM
space includes up to 128 bytes for the stack from
0100h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0000h
007Fh
0080h
017Fh
0180h
DFFFh
E000h
FFDFh
FFE0h
FFFFh
HW Registers
(see Table 2)
256 Bytes RAM
Reserved
Program Memory
(4K, 8 KBytes)
Interrupt & Reset Vectors
(see Table 5 on page 26)
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredicable effects on the
device.
0080h
00FFh
0100h
017Fh
E000h
F000h
FFFFh
Short Addressing RAM
Zero page
(128 Bytes)
Stack or
16-bit Addressing RAM
(128 Bytes)
8 KBytes
4 KBytes
10/135
Table 2. Hardware Register Map
ST72104G, ST72215G, ST72216G, ST72254G
Address Block
0000h
0001h
Port C
0002h
Register
Label
PCDR
PCDDR
PCOR
Register Name
Port C Data Register
Port C Data Direction Register
Port C Option Register
Reset
Status
00h
00h
00h
1)
0003h Reserved (1 Byte)
0004h
0005h
0006h
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
00h
00h
1)
0007h Reserved (1 Byte)
0008h
0009h
000Ah
Port A
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
1)
000Bh
to
Reserved (21 Bytes)
001Fh
0020h MISCR1 Miscellaneous Register 1 00h R/W
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W
Remarks
2)
R/W
2)
R/W
2)
R/W
R/W
R/W
R/W.
R/W
R/W
R/W
R/W
R/W
Read Only
0025h CRSR Clock, Reset, Supply Control /Status Register 000x 000x R/W
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2CCR
I2CSR1
2
C
I
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
Reserved (2 bytes)
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
002Fh
to
Reserved (4 Bytes)
0030h
11/135
ST72104G, ST72215G, ST72216G, ST72254G
Address Block
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h MISCR2 Miscellaneous Register 2 00h R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TIMER A
TIMER B
Register
Label
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Register Name
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
Reset
Status
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Remarks
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
0050h
to
006Fh
0070h
0071h
0072h
to
007Fh
ADC
ADCDR
ADCCSR
Data Register
Control/Status Register
Reserved (32 Bytes)
Reserved (14 Bytes)
00h
00h
Read Only
R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contentsof the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returnedinstead of the DR register contents.
2. The bits associated withunavailable pins must always keep their reset value.
12/135
4 FLASH PROGRAM MEMORY
ST72104G, ST72215G, ST72216G, ST72254G
4.1 INTRODUCTION
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-bybyte basis.
4.2 MAIN FEATURES
■ Remote In-Situ Programming (ISP) mode
■ Up to 16 bytes programmedin the same cycle
■ MTP memory (Multiple Time Programmable)
■ Read-out memory protection against piracy
4.3 STRUCTURAL ORGANISATION
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
The FLASH program memory is mappedin the upper part ofthe ST7 addressing space and includes
the reset and interrupt user vector area .
4.4 IN-SITU PROGRAMMING (ISP) MODE
The FLASH program memory canbe programmed
using Remote ISP mode. This ISP mode allows
the contentsoftheST7program memory to be updated usingastandard ST7 programming tools after the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area impact.
An exampleRemote ISP hardware interface to the
standard ST7 programming tool is described below. For more details on ISP programming, refer to
the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP mode is initiatedby a specific sequence on the dedicated ISPSEL pin.
The Remote ISP is performedin three steps:
– Selection of the RAM execution mode
– Download of Remote ISP codein RAM
– Execution ofRemote ISP code in RAM to pro-
gram the user program into the FLASH
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
with power (VDDand VSS) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the VDDsignal
if necessary) to be connected to the programming
tool. This signals are:
– RESET: device reset
–VSS: device ground power supply
– ISPCLK: ISP outputserial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP modeselection. Thispin
must be connected to VSSon the application
board through a pull-down resistor.
If any of thesepins areused for other purposeson
the application, a serial resistor has to be implemented to avoid a conflict ifthe other deviceforces
the signal level.
Figure 5 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout description.
Figure 5. Typical Remote ISP Interface
HE10 CONNECTOR TYPE
TO PROGRAMMINGTOOL
ISPSEL
DD
V
V
RESET
ISPCLK
ISPDATA
10KΩ
SS
APPLICATION
1
47KΩ
C
XTAL
L0
OSC2
ST7
C
L1
OSC1
4.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an option bit.
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memory are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased. However, the E2PROM
data memory (when available) can be protected
only with ROM devices.
13/135
ST72104G, ST72215G, ST72216G, ST72254G
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 6. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE= XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bitregisters
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y registeris not affectedby the interrupt automatic procedures (notpushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) andPCH
(Program CounterHigh which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
15 8
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACKHIGHER ADDRESS
14/135
PCH
RESET VALUE =
7
70
1C11HI NZ
1X11X1XX
87 0
PCL
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
ST72104G, ST72215G, ST72216G, ST72254G
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
70
the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
111HINZC
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result ofthe instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H
Half carry
.
This bit is set by hardware whena carryoccursbetween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I
Interrupt mask
.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlledby the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you enter it and resetby the IRETinstruction at the endof
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0:Theresultof the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit isaccessed bythe JRMI andJRPL instructions.
Bit 1 = Z
Zero
.
This bit is set and cleared by hardware. Thisbit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow hasoccurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
th
15/135
ST72104G, ST72215G, ST72216G, ST72254G
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 7Fh
15 8
00000001
70
0 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is always pointingto the next free location in the stack.
It isthen decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
Since the stack is 128 bytes deep, the 9th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits areset) which is the
stack higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wrapsin case of anunderflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by meansof the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from thestack.
A subroutine call occupies twolocations and an interrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
@ 0100h
SP
@ 017Fh
CALL
Subroutine
SP
PCH
PCL
Stack Higher Address = 017Fh
Stack Lower Address =
Interrupt
Event
SP
CC
A
X
PCH
PCL
PCH
PCL
0100h
PUSH Y POP Y IRET
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
RET
or RSP
SP
16/135
ST72104G, ST72215G, ST72216G, ST72254G
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72104G, ST72215G, ST72216G and
ST72254G microcontrollers include arange of utility features for securing the application in critical
situations (for example in case of a power brownout), and reducing the number of external components. An overview is shown in Figure 8.
See Section 13 ”ELECTRICAL CHARACTERISTICS” on page 96 for more details.
Main Features
■ Supply Manager with main supply low voltage
detection (LVD)
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
■ Clock Security System (CSS)
– Clock Filter
– Backup Safe Oscillator
Figure 8. Clock, Reset and Supply Block Diagram
MCO
OSC2
OSC1
RESET
VDD
VSS
MULTI-
OSCILLATOR
(MO)
RESET SEQUENCE
MANAGER
(RSM)
LOW VOLTAGE
DETECTOR
(LVD)
CLOCK SECURITYSYSTEM
CLOCK
FILTER
(CSS)
CRSR
SAFE
OSC
WATCHDOG
PERIPHERAL
FROM
f
OSC
MAIN CLOCK
CONTROLLER
(MCC)
LVD
f
CPU
CSS WDG
IE D00 0 0 RF RF
CSS INTERRUPT
17/135
ST72104G, ST72215G, ST72216G, ST72254G
6.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detector function (LVD) generates a static reset when
the VDDsupply voltage is below a V
value. This means that it secures the power-up as
reference
IT-
well as the power-down keeping the ST7 in reset.
The V
than the V
referencevalue fora voltage drop is lower
IT-
referencevalue forpower-on in order
IT+
to avoid a parasitic reset when theMCUstarts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDDis below:
–V
when VDDis rising
IT+
–V
when VDDis falling
IT-
The LVD function is illustrated in the Figure 9.
Provided the minimum VDDvalue (guaranteed for
the oscillator frequency) is below V
, the MCU
IT-
can only be in two modes:
– under full software control
– in static safe reset
Figure 9. Low Voltage Detector vs Reset
V
DD
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During aLow Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to the application requirement.
LVD application note
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
V
IT+
V
IT-
RESET
V
hyst
18/135
6.2 RESET SEQUENCE MANAGER (RSM)
ST72104G, ST72215G, ST72216G, ST72254G
6.2.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 11:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 10:
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
Figure 11. Reset Block Diagram
V
RESET
DD
R
ON
f
CPU
The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 10. RESET Sequence Phases
RESET
DELAY
INTERNAL RESET
4096 CLOCK CYCLES
COUNTER
FETCH
VECTOR
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
19/135
ST72104G, ST72215G, ST72216G, ST72254G
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESETpin is both an input andan open-drain
output with integrated RONweak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).
Starting from the external RESET pulse recognition, the device RESET pin acts as an output that
is pulled low during at least t
w(RSTL)out
.
Figure 12. RESET Sequences
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<V
VDD<V
(falling edge) as shown in Figure 12.
IT-
The LVD filters spikes on VDDlarger than t
(rising edge) or
IT+
g(VDD)
to
avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
V
DD
V
IT+
V
IT-
SHORT EXT.
RESET
DELAY
LONG EXT.
RESET
RUN RUN
DELAY
t
h(RSTL)in
WATCHDOG UNDERFLOW
WATCHDOG
RESET
RUN
DELAY
t
w(RSTL)out
INTERNAL RESET (4096T
FETCH VECTOR
CPU
)
RUN
LVD
RESET
DELAY
RUN
t
w(RSTL)out
t
h(RSTL)in
20/135
6.3 MULTI-OSCILLATOR (MO)
ST72104G, ST72215G, ST72216G, ST72254G
The main clock of the ST7 can be generated by
four different source types coming from the multioscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an external RC oscillator
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square,
sinus ortriangle) with~50% duty cycle has todrive
the OSC1 pinwhile theOSC2 pinis tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has theadvantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonatorand the
load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 3. ST7 Clock Sources
Hardware Configuration
ST7
ST7
LOAD
CAPACITORS
ST7
External ClockCrystal/Ceramic ResonatorsExternal RC OscillatorInternal RC Oscillator
OSC1 OSC2
EXTERNAL
SOURCE
OSC1 OSC2
C
L1
OSC1 OSC2
R
EX
C
L2
C
EX
External RC Oscillator
This oscillator allows a low cost solution for the
main clockof the ST7 using only an external resistor and anexternal capacitor.The frequencyof the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground.
ST7
OSC1 OSC2
21/135
ST72104G, ST72215G, ST72216G, ST72254G
6.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the integration of the security features in the applications, itis based on a clock filter control and anInternal safe oscillator. The CSS can be enabled or
disabled by option byte.
6.4.1 Clock Filter Control
The clock filter is based on a clock frequency limitation function.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the
current active oscillator clock can be totally filtered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7
clock.
6.4.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 13).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signalwhich allows the ST7 to perform some
rescue operations.
Automatically, theST7 clock sourceswitches back
from the safe oscillator if the original clock source
recovers.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CSSIE bit has been previously set.
These two bits are described in the CRSR register
description.
6.4.3 Low Power Modes
Mode Description
WAIT
HALT
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until
HALT mode is exited.The previous CSS
configuration resumes when the MCU is
woken up by aninterrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
6.4.4 Interrupts
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event
CSS event detection
(safe oscillator activated as main clock)
Flag
Enable
Control
Bit
Event
CSSD CSSIE Yes No
Exit
from
Wait
Exit
from
Halt
Figure 13. Clock Filter Function and Safe Oscillator Function
f
/2
OSC
f
FUNCTION
CPU
CLOCK FILTER
f
/2
OSC
f
SFOSC
FUNCTION
f
CPU
SAFE OSCILLATOR
22/135
ST72104G, ST72215G, ST72216G, ST72254G
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)
Read/Write
Reset Value: 000x 000x (XXh)
70
000
LVD
RF
CSSIECSSDWDG
0
RF
Bit 1 = CSSD
Clock security system detection
This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
signal (f
). It is set by hardware and cleared by
OSC
reading the CRSR register when the originaloscillator recovers.
0: Safe oscillator is not active
Bit 7:5 = Reserved, always read as 0.
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 4 = LVDRF
This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.
LVD reset flag
Bit 0 = WDGRF
Watchdog reset flag
This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the
CPU starts).
Bit 3 = Reserved, always read as 0.
Bit 2 = CSSIE
Clock security syst.interrupt enable
This bit enables the interrupt when a disturbance
is detected bythe clock security system (CSSD bit
set). It is set and cleared by software.
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources LVDRF WDGRF
External RESET pin 0 0
Watchdog 0 1
LVD 1 X
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt Mapping,” on page 26
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flagremains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
0025h
Register
Label
CRSR
Reset Value 0 0 0
76543210
LVDRF
x0
CSSIE0CSSD0WDGRF
x
23/135
ST72104G, ST72215G, ST72216G, ST72254G
6.6 MAIN CLOCK CONTROLLER (MCC)
The Main Clock Controller (MCC) supplies the
clock for the ST7 CPU and its internal peripherals.
It allows SLOW power saving mode to be managed by the application.
All functions are managed by the Miscellaneous
register 1 (MISCR1).
The MCC block consists of:
■ A programmable CPU clock prescaler
■ A clock-out signal to supply external devices
The prescaler allows the selection of the main
clock frequency and is controlled by three bits of
the MISCR1: CP1, CP0 and SMS.
The clock-out capability consists of a dedicated
I/O port pin configurable as an f
drive external devices. It is controlled by the MCO
bit in the MISCR1 register.
See Section 10 ”MISCELLANEOUS REGISTERS” on page 36 for more details.
Figure 14. Main Clock Controller (MCC) Block Diagram
PORT
ALTERNATE
f
OSC
/2
MISCR1
FUNCTION
MCO ----
clockoutput to
CPU
CLOCK TO CAN
PERIPHERAL
MCO
SMSCP1 CP0
f
OSC
DIV2,4,8,16DIV 2
f
CPU
CPU CLOCK
TO CPU AND
PERIPHERALS
24/135
7 INTERRUPTS
ST72104G, ST72215G, ST72216G, ST72254G
The ST7 core may be interruptedby one oftwo different methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 15.
The maskableinterrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsection).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– ThePC isthenloaded with the interrupt vectorof
the interruptto service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Tablefor vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from thestack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when severalinterrupts are simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low power mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Table).
7.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the stateof theI bit.
It will be serviced according to the flowchart on
Figure 15.
7.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. Theseinterrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt serviceroutine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed beforeentering the edge/
level detection block.
Caution:The type of sensitivitydefinedin the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDedsource
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt requesteven in case of risingedge sensitivity.
7.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– Thecorresponding enable bit is setin thecontrol
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access tothe status registerwhile the flag isset
followed by a read or write of an associated register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost ifthe clear sequence is
executed.
25/135
ST72104G, ST72215G, ST72216G, ST72254G
INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
FROM RES ET
N
N
INTE RRUPT
PENDING?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTO R
EXECU TE INSTRUCTION
RESTORE P C, X, A, CC FROM STACK
I BIT SET?
Y
FETCH NEXT INSTR UCTION
N
THIS CLEA RS I BIT BY DEFAULT
IRET?
Y
Table 5. Interrupt Mapping
N°
Source
Block
Description
RESET Reset
TRAP Software Interrupt no FFFCh-FFFDh
0 ei0 External Interrupt Port A7..0 (C5..0
1 ei1 External Interrupt Port B7..0 (C5..0
1
)
1
) FFF8h-FFF9h
Register
Label
N/A
Priority
Order
Highest
Priority
2 CSS Clock Filter Interrupt CRSR
3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h
4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh
7 Not used FFECh-FFEDh
8 Not used FFEAh-FFEBh
9 Not used FFE8h-FFE9h
10 Not used FFE6h-FFE7h
11 I C I C Peripheral I nterrupt I2CSRx no FFE4h-FFE 5h
12 Not Used FFE2h-FFE 3h
13 Not Used FFE0h-FFE 1h
Lowest
Priority
Exit
from
HALT
Address
Vector
yes FFFEh-FFFFh
yes
FFFAh-FFFBh
FFF6h-FFF7h
no
Note
1. Configurable by option byte.
26/135
8 POWER SAVING MODES
ST72104G, ST72215G, ST72216G, ST72254G
8.1 INTRODUCTION
To give a large measure of flexibilitytotheapplication in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 16).
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
CPU
).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscillator status.
Figure 16. Power Saving Mode Transitions
High
RUN
SLOW
WAIT
8.2 SLOW MODE
This mode has two targets:
– To reduce powerconsumption bydecreasingthe
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
CPU
)to
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits whichselect
the internal slow frequency (f
CPU
).
In this mode, the oscillator frequency can bedivided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT modeis activated when enterring the WAIT mode while the device is already in
SLOW mode.
Figure 17. SLOW Mode Clock Transitions
f
f
CPU
f
OSC
CP1:0
/2
/4 f
OSC
00 01
OSC
/8 f
OSC
/2
SLOW WAIT
HALT
Low
POWER CONSUMPTION
SMS
MISCR1
NEW SLOW
FREQUENCY
REQUEST
NORMAL RUN MODE
REQUEST
27/135
ST72104G, ST72215G, ST72216G, ST72254G
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selectedby calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of theCC register is forced to 0, to enable
all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting
address of the interrupt or Reset serviceroutine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure18.
Figure 18. WAIT Mode Flow-chart
OSCILLATOR
WFI INSTRUCTION
N
INTERRUPT
Y
PERIPHERALS
CPU
IBIT
N
RESET
Y
OSCILLATOR
PERIPHERALS
CPU
IBIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
ON
OFF
ON
1
ON
ON
ON
X
1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on thestack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
28/135
POWER SAVING MODES (Cont’d)
ST72104G, ST72215G, ST72216G, ST72254G
8.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 19).
When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immediately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 15.1 ”OPTION BYTES” on page 129 for
more details).
Figure 19. HALT Mode Timing Overview
HALTRUN RUN
4096 CPU CYCLE
DELAY
Figure 20. HALT Mode Flow-chart
HALT INSTRUCTION
WDGHALT
1
WATCHDOG
RESET
N
INTERRUPT
Y
1)
ENABLE
0
OSCILLATOR
PERIPHERALS
CPU
IBIT
N
3)
OSCILLATOR
PERIPHERALS
CPU
IBIT
4096 CPU CLOCK CYCLE
OSCILLATOR
PERIPHERALS
CPU
IBIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
WATCHDOG
RESET
Y
DELAY
DISABLE
OFF
2)
OFF
OFF
0
ON
OFF
ON
1
ON
ON
ON
4)
X
HALT
INSTRUCTION
INTERRUPT
RESET
OR
FETCH
VECTOR
Notes:
1.WDGHALTis anoption bit. See option byte section for more details.
2.Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer toTable 5, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on thestack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
29/135
ST72104G, ST72215G, ST72216G, ST72254G
9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
– transferofdatathrough digitalinputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins.Each pin can be
programmed independently as digital input(with or
without interrupt generation)or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/Opin may be programmed using thecorre-
sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 21
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can beselected bysoftware
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate anexternal interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Miscellaneous register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (seepinout description
and interrupt section). If several input pins are selected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configuration, special care must be taken when changing
the configuration (see Figure 22).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application)is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellaneous register must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then readingthe DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR Push-pull Open-drain
0V
1V
SS
DD
Vss
Floating
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming.
When the signal is coming froman on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is alsodigitally readableby
addressing theDR register.
Note: Input pull-up configuration can cause unexpected value attheinput ofthealternateperipheral
input. Whenan on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
30/135
I/O PORTS (Cont’d)
Figure 21. I/O Port General Block Diagram
ST72104G, ST72215G, ST72216G, ST72254G
REGISTER
ACCESS
DATA BUS
DDR SEL
DR
DDR
OR
OR SEL
DR SEL
ALTERNATE
OUTPUT
ALTERNATE
ENABLE
If implemented
1
1
0
PULL-UP
CONDITION
N-BUFFER
V
DD
CMOS
SCHMITT
TRIGGER
P-BUFFER
(see table below)
PULL-UP
(see table below)
V
DD
PAD
DIODES
(see table below)
ANALOG
INPUT
0
EXTERNAL
INTERRUPT
SOURCE (ei
)
x
POLARITY
SELECTION
Table 6. I/O Port Mode Options
Configuration Mode Pull-Up P-Buffer
Input
Output
Floating with/without Interrupt Off
Pull-up with/without Interrupt On
Push-pull
Open Drain (logic level) Off
True Open Drain NI NI NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
FROM
OTHER
BITS
ALTERNATE
INPUT
Diodes
to V
Off
Off
On
to V
On
DD
Note: The diode to VDDis not implemented in the
true open drain pads. A local protection between
the pad and VSSis implemented to protect the device against positive stress.
SS
On
31/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN
TRUEOPEN DRAIN
I/O PORTS
1)
INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
2)
I/O PORTS
OPEN-DRAIN OUTPUT
PAD
PAD
V
DD
R
PU
V
DD
R
PU
PULL-UP
CONDITION
FROM
OTHER
PINS
INTERRUPT
CONDITION
DR REGISTER ACCESS
DR
REGISTER
ENABLE OUTPUT
W
R
POLARITY
SELECTION
DR REGISTER ACCESS
DR
REGISTER
ALTERNATEALTERNATE
ALTERNATEINPUT
EXTERNAL INTERRUPT
SOURCE (ei
ANALOG INPUT
R/W
DATABUS
)
x
DATA BUS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
2)
I/O PORTS
PUSH-PULL OUTPUT
PAD
V
DD
R
PU
ENABLE OUTPUT
DR REGISTER ACCESS
DR
REGISTER
ALTERNATEALTERNATE
R/W
DATA BUS
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in outputconfiguration and the associated alternate functionisenabledas an input,
the alternate function reads the pin status given by the DR register content.
32/135
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in ordertoavoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pinto thecommon analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
9.3 I/O PORT IMPLEMENTATION
ST72104G, ST72215G, ST72216G, ST72254G
Figure 22. Interrupt I/O Port State Transitions
01
INPUT
floating/pull-up
interrupt
The I/O port register configurations are summarized as follows.
Interrupt Ports
PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
floating input 0 0
pull-up interrupt input 0 1
open drain output 1 0
push-pull output 1 1
00
INPUT
floating
(reset state)
MODE DDR OR
10
OUTPUT
open-drain
XX
11
OUTPUT
push-pull
= DDR, OR
The hardware implementation on each I/O port depends onthe settings in theDDRandORregisters
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state toanother shouldbe done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 22 Other transitions
True Open Drain Interrupt Ports
PA6, PA4(without pull-up)
MODE DDR OR
floating input 0 0
floating interrupt input 0 1
open drain (high sink ports) 1 X
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Table 8. Port Configuration
Port Pin name
PA7 floating pull-up interrupt open drain push-pull
PA6 floating floating interrupt true open-drain
Port A
Port B PB7:0 floating pull-up interrupt open drain push-pull
Port C PC7:0 floating pull-up interrupt open drain push-pull
PA5 floating pull-up interrupt open drain push-pull
PA4 floating floating interrupt true open-drain
PA3:0 floating pull-up interrupt open drain push-pull
Input (DDR = 0) Output (DDR = 1)
OR = 0 OR = 1 OR = 0 OR = 1 High-Sink
Yes
No
33/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
9.4 LOW POWER MODES
Mode Description
WAIT
HALT
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
9.5 INTERRUPTS
The external interrupt event generates aninterrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
Interrupt Event
External interrupt on
selected external
event
Event
Flag
-
Enable
Control
Bit
DDRx
ORx
Exit
from
Wait
Yes Yes
Exit
from
Halt
9.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR withx = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
70
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
Bit 7:0 = DD[7:0]
Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
70
O7 O6 O5 O4 O3 O2 O1 O0
70
Bit 7:0 = O[7:0]
Option register 8 bits.
For specific I/O pins, this register is not implement-
D7 D6 D5 D4 D3 D2 D1 D0
ed. In this case the DDR register is enough to select the I/O pin configuration.
The OR register allows to distinguish: in input
Bit 7:0 = D[7:0]
The DR register has a specific behaviour accord-
ing to the selectedinput/output configuration. Writing the DR register is always taken into account
even ifthe pinis configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured asoutput) or the digital value applied to
the I/O pin (pin configured as input).
Data register 8 bits.
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drainconfigurationis
selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer unactivated)
1: Output push-pull (when available)
34/135
I/O PORTS (Cont’d)
Table 9. I/O Port Register Map andReset Values
ST72104G, ST72215G, ST72216G, ST72254G
Address
(Hex.)
Reset Value
of all I/O port registers
0000h PCDR
0002h PCOR
0004h PBDR
0006h PBOR
0008h PADR
000Ah PAOR
Register
Label
76543210
00000000
MSB LSB0001h PCDDR
MSB LSB0005h PBDDR
MSB LSB0009h PADDR
35/135
ST72104G, ST72215G, ST72216G, ST72254G
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external interrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two fully independent external interrupt source sensitivities with configurable sources (using EXTIT option
bit) as shownin Figure 23 and Figure 24.
Each external interrupt source can be generated
on four different events onthe pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous registerdescriptions for moredetails on the
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCRregisters manage four I/O port miscellaneous alternate functions:
■ Main clock signal (f
■ SPI pin configuration:
) output on PC2
CPU
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
– Master output capability on MOSI pin (PB4)
deactivated while the SPI is active.
– Slave output capability onMISO pin (PB5) de-
activated while the SPI is active.
These functions are described in detail in the Section 10.3 ”MISCELLANEOUS REGISTER DESCRIPTION” on page 37.
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
PA7
PA0
PC5
PC0
PB7
PB0
ei0
INTERRUPT
SOURCE
ei1
INTERRUPT
SOURCE
MISCR1
IS00 IS01
SENSITIVITY
CONTROL
MISCR1
IS10 IS11
SENSITIVITY
CONTROL
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1
IS00 IS01
SENSITIVITY
CONTROL
MISCR1
IS10 IS11
SENSITIVITY
CONTROL
PA7
PA0
PB7
PB0
PC5
PC0
ei0
INTERRUPT
SOURCE
ei1
INTERRUPT
SOURCE
36/135
ST72104G, ST72215G, ST72216G, ST72254G
MISCELLANEOUS REGISTERS (Cont’d)
10.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 2:1 = CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
70
in SLOW mode CP1 CP0
f
CPU
IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS
Bit 7:6 = IS1[1:0]
ei1 sensitivity
The interruptsensitivity, definedusing the IS1[1:0]
/4 0 0
f
OSC
/8 1 0
f
OSC
/16 0 1
f
OSC
/32 1 1
f
OSC
bits, isapplied to the ei1 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1(interrupt masked).
ei1: Port B (C optional)
External Interrupt Sensitivity IS11 IS10
Falling edge & low level 0 0
Rising edge only 0 1
Falling edge only 1 0
Rising and falling edge 1 1
Bit 5 = MCO
Main clock out selection
Bit 0 = SMS
Slow mode select
This bit is set andcleared by software.
0: Normal mode. f
1: Slow mode. f
CPU
= f
CPU
OSC
is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.
This bit enablesthe MCO alternatefunction on the
PC2 I/O port. It is set and cleared by software.
0: MCOalternatefunctiondisabled(I/Opinfree for
general-purpose I/O)
1: MCO alternate function enabled (f
CPU
on I/O
port)
/2
Bit 4:3 = IS0[1:0]
ei0 sensitivity
The interruptsensitivity, definedusing the IS0[1:0]
bits, isapplied to the ei0 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1(interrupt masked).
ei0: Port A (C optional)
External Interrupt Sensitivity IS01 IS00
Falling edge & low level 0 0
Rising edge only 0 1
Falling edge only 1 0
Rising and falling edge 1 1
37/135
ST72104G, ST72215G, ST72216G, ST72254G
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
70
0 0 0 0 MOD SOD SSM SSI
Bit 7:4 = Reserved
Bit 5 = MOD
SPI Master Output Disable
always read as 0
This bit is set and cleared by software. Whenset, it
disables the SPI Master (MOSI) output signal.
0: SPI Master Output enabled.
1: SPI Master Output disabled.
Bit 4 = SOD
SPI Slave Output Disable
This bit is set and cleared by software. When set it
disable the SPI Slave (MISO) output signal.
0: SPI Slave Output enabled.
1: SPI Slave Output disabled.
Bit 1 = SSM
SS mode selection
This bit is set and cleared bysoftware.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 0 = SSI
SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
Address
(Hex.)
0020h
0040h
38/135
Register
Label
MISCR1
Reset Value
MISCR2
Reset Value 0 0 0 0
76543210
IS11
0
IS10
0
MCO
0
IS01
IS00
0
0
MOD
0
CP1
0
SOD
0
CP0
0
SSM
0
SMS
0
SSI
0
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
ST72104G, ST72215G, ST72216G, ST72254G
11.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usuallygenerated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed timeperiod, unless theprogram refreshes the counter’s contents before the T6 bit becomes cleared.
11.1.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Optional reset on HALT instruction
(configurable by option byte)
■ Hardware Watchdog selectable by optionbyte.
11.1.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
Figure 25. Watchdog Block Diagram
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The applicationprogram must write in the CR register at regular intervalsduring normaloperationto
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11 . Watchdog Timing (fCPU = 8
MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating animme-
diate reset
– TheT5:T0 bits contain thenumber ofincrements
which represents the time delay before the
watchdog produces a reset.
f
CPU
RESET
WDGA
WATCHDOG CONTROL REGISTER (CR)
T5
T6
T4
7-BIT DOWNCOUNTER
CLOCK DIVIDER
÷12288
T3
T2
T1
T0
39/135
ST72104G, ST72215G, ST72216G, ST72254G
WATCHDOG TIMER (Cont’d)
Table 11. Watchdog Timing (f
CR Register
initialvalue
Max FFh 98.304
Min C0h 1.536
= 8 MHz)
CPU
WDG timeout period
(ms)
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannotbe disabled, except
by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdogis always active and the WDGA bit in
the CR is not used.
Refer to the device-specific Option Byte description.
11.1.5 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
If the Watchdog reset on HALT option is selected
by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set).
11.1.5.1 Using Halt Modewith the WDG (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALTinstruction stops the oscillator. Whenthe oscillator isstopped, the WDG stops
counting and is no longer able to generate a reset
until the microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is
generated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event isavailable to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDGcounter, to avoidan unexpected WDG
reset immediately after waking up the microcontroller.
– When using an external interruptto wake up the
microcontroller, reinitializethecorresponding I/O
as “InputPull-up withInterrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configuredduetoexternal interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precautionary measure.
– Theopcode for the HALT instruction is 0x8E.To
avoid an unexpected HALT instruction due to a
program counter failure,it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in
ROM with the value 0x8E.
– Asthe HALT instruction clears the I bit inthe CC
register to allow interrupts, the user maychoose
to clear all pending interrupt bits before executing the HALT instruction. This avoids entering
other peripheralinterruptroutines afterexecuting
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
11.1.6 Interrupts
None.
11.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
70
WDGA T6 T5 T4 T3 T2 T1 T0
Bit 7 = WDGA
Activation bit
.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
40/135
ST72104G, ST72215G, ST72216G, ST72254G
WATCHDOG TIMER (Cond’t)
Table 12. Watchdog Timer RegisterMap and Reset Values
Address
(Hex.)
0024h
Register
Label
WDGCR
Reset Value
76543210
WDGA
0
T6
T5
1
1
T4
T3
1
1
T2
T1
1
1
T0
1
41/135
ST72104G, ST72215G, ST72216G, ST72254G
11.2 16-BIT TIMER
11.2.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used fora variety of purposes, including
pulse length measurement of up to two input signals (
input capture
put waveforms (
) or generation of up to two out-
output compare
and
PWM
).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bittimers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers oneor two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
11.2.2 Main Features
■ Programmableprescaler:f
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
dividedby2,4or8.
CPU
slower thantheCPUclock speed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capturefunctions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternatefunctionson I/Oports (ICAP1,ICAP2,
OCMP1, OCMP2,EXTCLK)*
11.2.3 Functional Description
11.2.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte(MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with thedifferencethat reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Statusregister, (SR),
(see note atthe end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register,as illustrated in Table 13 Clock
Control Bits. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
CPU
/2, f
CPU
/4, f
CPU
/8
or an external frequency.
The Block Diagram is shown in Figure 26.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
42/135
16-BIT TIMER (Cont’d)
Figure 26. Timer Block Diagram
f
CPU
ST72104G, ST72215G, ST72216G, ST72254G
ST7 INTERNAL BUS
MCU-PERIPHERAL INTERFACE
EXTCLK
pin
1/2
1/4
1/8
CC[1:0]
8high
EXEDG
OVERFLOW
DETECT
CIRCUIT
8 low
8-bit
buffer
16
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
OUTPUT COMPARE
16
high
low
OUTPUT
COMPARE
REGISTER
1
TIMER INTERNAL BUS
16 16
CIRCUIT
6
8
low
high
OUTPUT
COMPARE
REGISTER
2
888
8
high
INPUT
CAPTURE
REGISTER
EDGE DETECT
CIRCUIT1
EDGE DETECT
CIRCUIT2
888
low
1
high
INPUT
CAPTURE
REGISTER
2
16
low
16
ICAP1
pin
ICAP2
pin
(See note)
TIMER INTERRUPT
ICF2ICF1 000OCF2OCF1 TOF
(Status Register) SR
(Control Register 1) CR1
LATCH1
LATCH2
PWMOC1E EXEDGIEDG2CC0CC1
OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE
OC2E
(Control Register 2) CR2
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
OCMP1
pin
OCMP2
pin
43/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate CounterRegister).
Beginning of the sequence
Read
At t0
MS Byte
Other
instructions
Read
At t0 +∆t
LS Byte
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever thetimermodeused(input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register isset and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
LS Byte
is buffered
Returns the buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in
two steps:
1.Reading theSR register whilethe TOF bit is set.
2.An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather thanthe CLR register is that
it allowssimultaneous use ofthe overflow function
and reading the free running counter at random
times (forexample, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
11.2.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that willtrigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur betweentwo consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
44/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 27. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMERCLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFD FFFE FFFF 0000 0001 0002 0003
Figure 28. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMERCLOCK
COUNTER REGISTER
TIMER OVERFLOWFLAG (TOF)
FFFC FFFD 0000 0001
Figure 29. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD
0000
Note: The MCU is in reset state when the internal reset signal ishigh, when it is low the MCU is running.
45/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.3 Input Capture
In this section, the index,i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition detected by the
ICAPipin (see figure 5).
MS Byte LS Byte
ICiR IC
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGibit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (f
CPU
/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 13
Clock ControlBits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or theICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with theIEDG1 bit(the ICAP1pinmust
be configured as floating input).
i
HR ICiLR
When an input capture occurs:
– ICFibit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPipin (see Figure 31).
– A timer interrupt is generated if the ICIEbit is set
and the I bit is clearedin the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFibit) is done in two steps:
1.Reading the SR register while the ICFibitis set.
2.An access (read or write) to the ICiLR register.
Notes:
1.After reading the ICiHR register, transfer of
input capture data is inhibited and ICFiwill
never be set until the ICiLR register is also
read.
2.The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3.The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4.In One pulse Mode and PWM mode only the
input capture 2 can be used.
5.The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover if one of the ICAPipin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture functioniis disabledby readingthe ICiHR (see note
1).
6.The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
46/135
16-BIT TIMER (Cont’d)
Figure 30. Input Capture Block Diagram
ST72104G, ST72215G, ST72216G, ST72254G
ICAP1
pin
ICAP2
pin
EDGE DETECT
CIRCUIT2
16-BIT
EDGE DETECT
CIRCUIT1
IC1R RegisterIC2R Register
16-BIT FREE RUNNING
COUNTER
Figure 31. Input Capture Timing Diagram
TIMER CLOCK
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR
ICF2ICF1 000
(Control Register 2) CR2
IEDG2
CC0
CC1
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: A
ctive edge is rising edge.
FF01 FF02 FF03
FF03
47/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.4 Output Compare
In this section, the index,i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register andthe freerunning counter, the output compare function:
– Assigns pinswith a programmable valueif the
OCIE bit is set
– Sets a flag in thestatus register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
MS Byte LS Byte
OC
i
ROC
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (f
CPU/
CC[1:0]
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPipin is dedicated to the output compare
signal.
– Select the timer clock (CC[1:0]) (see Table 13
Clock ControlBits).
And select the following in the CR1 register:
– SelecttheOLVLibittoappliedto theOCMPipins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFibit is set.
i
HR OCiLR
).
i
– The OCMPipin takes OLVLibit value (OCMP
i
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆t*f
∆OC
i
R=
CPU
PRESC
Where:
∆t = Output compare period (in seconds)
f
CPU
PRESC
If the timer clock is an external clock, the formula
is:
Where:
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 13
Clock Control Bits)
∆OC
i
R=∆t
*fEXT
∆t = Output compare period (in seconds)
f
EXT
Clearing the output compare interrupt request (i.e.
clearing the OCFibit) is done by:
1.Reading the SR register while the OCFibit is
2.An access (read or write) to the OCiLR register.
The following procedure is recommended to pre-
vent the OCFibit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
– Readthe SR register (first step of the clearance
– Write to the OCiLR register (enables the output
= External timerclockfrequency(inhertz)
set.
are inhibited).
of the OCFibit, which may be already set).
compare function and clears the OCFibit).
48/135
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPipin is a
general I/O port and the OLVLibit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFiand
CPU
OCMPiare set while the counter value equals
theOCiR register value (see Figure 33 onpage
49). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
CPU
/4, f
CPU
/8 or in
external clock mode, OCFiand OCMPiare set
while the counter value equals the OCiR register value plus 1 (see Figure 34 on page 49).
4. The output compare functions can be used both
for generating external events on the OCMP
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVibit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
ST72104G, ST72215G, ST72216G, ST72254G
Forced Compare Output capability
When the FOLVibit is set by software, the OLVL
bit is copiedto theOCMPipin. TheOLVibit has to
be toggled in order to toggle the OCMPipin when
it isenabled (OCiE bit=1).The OCFibit is thennot
set by hardware, and thus no interrupt request is
generated.
FOLVLibits have no effect in both one pulsemode
and PWM mode.
i
i
Figure 32. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R Register
16-bit
OC2R Register
OC1E CC0CC1
OC2E
(Control Register 2) CR2
(Control Register 1) CR1
FOLV2 FOLV1
(Status Register) SR
OLVL1OLVL2OCIE
000OCF2OCF1
Latch
1
Latch
2
OCMP1
Pin
OCMP2
Pin
49/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 33. Output Compare Timing Diagram, f
INTERNAL CPU CLOCK
TIMERCLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER
OUTPUT COMPARE FLAG
OCMP
i
i
(OCRi)
i
(OCFi)
PIN (OLVLi=1)
Figure 34. Output Compare Timing Diagram, f
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
TIMER=fCPU
2ED0 2ED1 2ED2 2ED3 2ED42ECF
TIMER=fCPU
2ED0 2ED1 2ED2
/2
/4
2ED3
2ED3
2ED42ECF
OUTPUT COMPARE REGISTER
COMPARE REGISTER
OUTPUT COMPARE FLAG
OCMP
i
PIN (OLVLi=1)
i
(OCRi)
i
LATCH
i
(OCFi)
2ED3
50/135
16-BIT TIMER (Cont’d)
11.2.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This modeis
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, selectthe level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, selectthe level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transitionon the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1Ebit, the OCMP1 pinis then ded-
icated to the Output Compare 1 function.
– Set the OPMbit.
– Select the timer clock CC[1:0] (see Table 13
Clock Control Bits).
ST72104G, ST72215G, ST72216G, ST72254G
Clearing the Input Capture interrupt request (i.e.
clearing the ICFibit) is done in two steps:
1.Reading the SR register while the ICFibitis set.
2.An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
t*f
OCiR Value=
CPU
PRESC
Where:
t = Pulse period (in seconds)
f
CPU
PRESC
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8depend-
ing on the CC[1:0] bits, see Table 13
Clock Control Bits)
If the timer clock is an external clock theformulais:
OCiR=t
*fEXT
-5
Where:
t = Pulse period (in seconds)
f
EXT
= External timerclockfrequency(inhertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 35).
-5
One pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
Notes:
1.The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the onlyactive one.
3.If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4.The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture(ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5.When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
51/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 35. One Pulse Mode Timing Example
COUNTER
ICAP1
OCMP1
FFFC FFFD FFFE 2ED0 2ED1 2ED2
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 36. Pulse Width Modulation Mode Timing Example
COUNTER
OCMP1
FFFC FFFD FFFE
34E2
OLVL2
2ED0 2ED1 2ED2
compare2 compare1 compare2
FFFC FFFD
2ED3
OLVL2OLVL1
34E2 FFFC
OLVL2OLVL1
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
52/135
16-BIT TIMER (Cont’d)
11.2.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, selectthe level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, selectthe level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference betweenthe OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
OCMP1 = OLVL1
= OC1R
ST72104G, ST72215G, ST72216G, ST72254G
The OCiR register value required for a specific timing application can be calculated using the following formula:
t*f
OCiR Value=
CPU
PRESC
Where:
t = Signal or pulse period (in seconds)
f
CPU
PRESC
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8depend-
ing on CC[1:0] bits, see Table 13 Clock
Control Bits)
If the timer clock is an external clock theformulais:
OCiR=t
*fEXT
-5
Where:
t = Signal or pulse period (in seconds)
f
EXT
= External timerclockfrequency(inhertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 36)
Notes:
1.After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2.The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3.The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interruptif the ICIE bit is setand the I bit is
cleared.
4.In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer.The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIEis set.
5.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the onlyactive one.
-5
When
Counter
= OC2R
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
53/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.4 Low Power Modes
Mode Description
WAIT
HALT
11.2.5 Interrupts
Input Capture 1 event/Counter reset in PWM mode ICF1
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Haltmode is exited. Counting resumes from the previous
count when the MCU is woken upby an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
i
If an input capture event occurs on the ICAP
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF
the counter value present when exiting from HALT mode is captured into the IC
Interrupt Event
pin, the input capture detection circuitry isarmed. Consequent-
i
bit is set, and
i
R register.
Event
Flag
Enable
Control
Bit
ICIE
OCIE
Exit
from
Wait
Yes No
Yes No
Exit
from
Halt
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.2.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2) Yes Yes Yes Yes
Output Compare (1 and/or 2) Yes Yes Yes Yes
One Pulse Mode No Not Recommended
PWM Mode No Not Recommended
1)
See note 4 in Section 11.2.3.5 ”One Pulse Mode” on page 50
2)
See note 5 in Section 11.2.3.5 ”One Pulse Mode” on page 50
3)
See note 4 in Section 11.2.3.6 ”Pulse Width Modulation Mode” on page 52
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
AVAILABLE RESOURCES
1)
3)
No Partially
No No
2)
54/135
16-BIT TIMER (Cont’d)
11.2.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairsofdata registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
ST72104G, ST72215G, ST72216G, ST72254G
Bit 4 = FOLV2
This bit is set andcleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Forced Output Compare 2.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
70
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 3 = FOLV1
This bit is set andcleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1to becopied to theOCMP1 pin,if
the OC1E bit is set and even if there is no successful comparison.
Bit 2 = OLVL2
Bit 7 = ICIE
Input CaptureInterrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1
Bit 6 = OCIE
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Output Compare Interrupt Enable.
Timer Overflow Interrupt Enable.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
Forced Output Compare 1.
Output Level 2.
Input Edge 1.
Output Level 1.
register.
55/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
70
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 7 = OC1E
Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode).Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E
Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM
One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode isactive, theICAP1pin can be
used totrigger one pulse on the OCMP1 pin;the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 3, 2 = CC[1:0]
Clock Control.
The timer clock mode depends on these bits:
Table 13. Clock Control Bits
Timer Clock CC1 CC0
f
/4 0 0
CPU
f
/2 0 1
CPU
f
/8 1 0
CPU
External Clock (where
available)
11
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2
Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counterregister.
1: A rising edge triggers the counter register.
56/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
70
ICF1 OCF1 TOF ICF2 OCF2 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register thatcontains the
high part of the counter value (transferred by the
input capture 1 event).
70
Bit 7 = ICF1
Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on theICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1
Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF
Timer OverflowFlag.
0: No timer overflow (reset value).
1:The freerunning counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SRregister, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2
Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2
Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC2R (OC2LR) register.
Bit 2-0 = Reserved, forced by hardwareto 0.
MSB LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register thatcontains the
low part of the counter value (transferred by the input capture 1 event).
70
MSB LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
70
MSB LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
70
MSB LSB
57/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
70
MSB LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value tobe compared to the CLR register.
70
70
MSB LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to thisregister resets the
counter. An access to this register after anaccess
to SR register does not clear the TOF bit in SR
register.
MSB LSB
COUNTER HIGH REGISTER (CHR)
70
MSB LSB
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
70
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register thatcontains the
high part of the counter value (transferred by the
MSB LSB
Input Capture2 event).
70
COUNTER LOW REGISTER (CLR)
MSB LSB
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the countervalue. A write to thisregisterresets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
70
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register thatcontains the
low part of the counter value(transferredby the Input Capture 2 event).
MSB LSB
58/135
70
MSB LSB
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Table 14. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Timer A: 32
Timer B: 42
Timer A: 31
Timer B: 41
Timer A: 33
Timer B: 43SRReset Value
Timer A: 34
Timer B: 44
Timer A: 35
Timer B: 45
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer A: 3E
Timer B: 4E
Timer A: 3F
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Register
Label
CR1
Reset Value
CR2
Reset Value
ICHR1
Reset Value
ICLR1
Reset Value
OCHR1
Reset Value
OCLR1
Reset Value
OCHR2
Reset Value
OCLR2
Reset Value
CHR
Reset Value
CLR
Reset Value
76543210
ICIE
0
OC1E
0
ICF1
0
MSB
-
MSB
-
MSB
-
MSB
-
MSB
-
MSB
-
MSB
1111111
MSB
1111110
OCIE
0
OC2E
0
OCF1
0
------
------
------
------
------
------
TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1
OPM
0
TOF
0
PWM
0
ICF2
0
CC1
0
OCF2
0
CC0
0
-
0
IEDG20EXEDG
-
0
0
0
-
0
LSB
-
LSB
-
LSB
-
LSB
-
LSB
-
LSB
-
LSB
1
LSB
0
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer A: 3C
Timer B: 4C
Timer A: 3D
Timer B: 4D
ACHR
Reset Value
ACLR
Reset Value
ICHR2
Reset Value
ICLR2
Reset Value
MSB
1111111
MSB
1111110
MSB
-
MSB
-
------
------
LSB
1
LSB
0
LSB
-
LSB
-
59/135
ST72104G, ST72215G, ST72216G, ST72254G
11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication between themicrocontroller and external peripherals
or another microcontroller.
Refer to the Pin Description chapter for the devicespecific pin-out.
11.3.2 Main Features
■ Full duplex, three-wiresynchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
11.3.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 37.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSIpin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is complete.
Four possible data/clock timing relationships may
be chosen (see Figure 40) but master and slave
must be programmed with the same timing mode.
Figure 37. Serial Peripheral Interface Master/Slave
MASTER
MSBit LSBit MSBit LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
60/135
MISO
MOSI
SCK
SS
+5V
MISO
MOSI
SCK
SS
SLAVE
8-BIT SHIFT REGISTER
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 38. Serial Peripheral Interface Block Diagram
Internal Bus
MOSI
MISO
SCK
SS
Read
Read Buffer
8-Bit Shift Register
Write
MASTER
CONTROL
DR
WCOL
SPIF
SPIE SPE SPR2 MSTR CPHA SPR0SPR1CPOL
MODF
-
SPI
STATE
CONTROL
--
IT
request
SR
--
CR
SERIAL
CLOCK
GENERATOR
61/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Functional Description
Figure 37 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
11.3.7for the bit definitions.
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequencebegins when a byte is written the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shiftedout serially to the MOSI pin most
significant bit first.
11.3.4.1 Master Configuration
In a masterconfiguration, theserial clockisgenerated on the SCK pin.
Procedure
– Select theSPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 40).
– The SSpin must be connected to a high level
signal during the complete byte transmit sequence.
– The MSTRand SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. WhentheDR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1.An access to the SR register while the SPIF bit
is set
2.A write or a read of the DR register.
Note: While theSPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
62/135
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The valueof the SPR0& SPR1 bits is not used for
the data transfer.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the master device (CPOL and CPHA bits).See Figure
40.
– The SS pin must be connected to a low level
signal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave device receives the clock signal andthe most significant bit of the data on its MOSI pin.
ST72104G, ST72215G, ST72216G, ST72254G
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. WhentheDR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1.An access to the SR register while the SPIF bit
is set.
2.A write or a read of the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 11.3.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
11.3.4.4).
63/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used tosynchronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; theother slave devices that are notselected do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 40, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISOpin,
the MOSI pin are directly connected between the
master and the slave device.
The SSpin istheslavedevice selectinput andcan
be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge.
CPHA bitis set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 39).
CPHA bitis reset
The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
The SS pin must be toggledhigh and low between
each byte transmitted (see Figure 39).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 39. CPHA / SS Timing Diagram
MOSI/MISO
Master
SS
Slave SS
(CPHA=0)
Slave
SS
(CPHA=1)
64/135
Byte 1 Byte 2
Byte 3
VR02131A
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 40. Data Clock Timing Diagram
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
ST72104G, ST72215G, ST72216G, ST72254G
CPHA =1
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPOL = 1
CPOL = 0
MISO
(from master)
MSBit Bit 6 Bit 5
MSBit Bit 6 Bit 5
MSBit Bit 6 Bit 5
Bit 4 Bit3 Bit 2 Bit 1 LSBit
Bit 4 Bit3 Bit 2 Bit 1 LSBit
CPHA =0
Bit 4 Bit3 Bit 2 Bit 1 LSBit
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
VR02131B
65/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.4 Write Collision Error
A write collision occurs when the software tries to
write tothe DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisionscan occur both inmaster andslave
mode.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is alwayssynchronous with the MCU operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the external MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin mustbe high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write collision.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 41).
Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
2nd Step
Read SR
OR
THEN
Read DR Write DR
SPIF =0
WCOL=0
Read SR
THEN
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SR
Read DR
THEN
WCOL=0
Note: Writing in DR register instead of reading in it do not reset
WCOL bit
66/135
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.5 Master Mode Fault
Master mode fault occurs when the master device
has itsSS pin pulled low, then theMODF bit is set.
Master modefault affects theSPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
ST72104G, ST72215G, ST72216G, ST72254G
may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODFbit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device canbe in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from system operation to a reset or default system state using an interrupt routine.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
11.3.4.6 Overrun Condition
An overrun condition occurs when the master device has sent several data bytes and the slavedevice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripheral.
67/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
– Multimaster System
Single Master System
A typical single master systemmay be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 42).
The master device selects the individual slave devices byusing four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pinsare pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte backfrom the
slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
Multi-master System
A multi-master system may also be configured by
the user. Transfer of master control could be implemented using a handshake methodthrough the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Figure 42. Single Master Configuration
SS
SCK
SCK
Slave
MCU
MOSI
MOSI
MISO
MOSI MOSI MOSIMISO MISO MISOMISO
SCK
Master
5V
MCU
SS
Ports
Slave
MCU
SS
SS
SCK SCK
Slave
MCU
MCU
SS
Slave
68/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Low Power Modes
Mode Description
WAIT
HALT
11.3.6 Interrupts
No effect on SPI.
SPI interrupt events cause the device to exit fromWAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
Interrupt Event
SPI End of Transfer Event SPIF
Master Mode Fault Event MODF Yes No
Event
Flag
Enable
Control
Bit
SPIE
Exit
from
Wait
Yes No
Note: The SPI interrupt events are connected to
the sameinterrupt vector(see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and the interrupt mask in
the CC register is reset (RIM instruction).
Exit
from
Halt
69/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
70
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE
Serial peripheral interrupt enable.
This bit is set and cleared bysoftware.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE
Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPEbit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
Bit 5 = SPR2
Divider Enable
.
this bit is set and cleared by software and it is
cleared by reset. It is usedwith the SPR[1:0] bits to
set the baud rate. Refer to Table 15.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pinsare reversed.
Bit 3 = CPOL
Clock polarity.
This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady stateis a high value at the SCK pin.
Bit 2 = CPHA
Clock phase.
This bit is set andcleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0]
Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 15. Serial Peripheral Baud Rate
Serial Clock SPR2 SPR1 SPR0
/2 1 0 0
f
CPU
/8 0 0 0
f
CPU
/16 0 0 1
f
CPU
/32 1 1 0
f
CPU
/64 0 1 0
f
CPU
/128 0 1 1
f
CPU
70/135
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
ST72104G, ST72215G, ST72216G, ST72254G
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
70
SPIF WCOL - MODF - - - -
Bit 7 = SPIF
Serial Peripheraldata transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between thedevice and an exter-
nal device has been completed.
Note: Whilethe SPIF bit isset, all writes to the DR
register are inhibited.
Bit 6 = WCOL
Write Collision status.
This bit is set by hardware when a write to the DR
70
D7 D6 D5 D4 D3 D2 D1 D0
The DR register is used to transmit and receive
data on the serialbus. In the master device only a
write to this register will initiate transmission/reception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serialperipheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register fortransmission.
A write to the the DR register returns the value located inthe bufferand notthe contents of the shift
register (See Figure 38 ).
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 41).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF
Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.3.4.5
”Master ModeFault” onpage66). An SPIinterrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence(An access to the SR register while MODF=1followedby
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
71/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 16. SPI Register Map and Reset Values
Address
(Hex.)
0021h
0022h
0023h
Register
Label
SPIDR
Reset Value
SPICR
Reset Value
SPISR
Reset Value
76543210
MSB
xxxxxxx
SPIE
0
SPIF
0
SPE
0
WCOL
00
SPR20MSTR
CPOL
0
MODF
00000
x
CPHA
x
SPR1
x
LSB
x
SPR0
x
72/135
11.4 I2C BUS INTERFACE (I2C)
ST72104G, ST72215G, ST72216G, ST72254G
11.4.1 Introduction
The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It
provides both multimaster and slave functions,
and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C
mode (400kHz).
11.4.2 Main Features
■ Parallel-bus/I
■ Multi-master capability
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
2
C protocol converter
I2C Master Features:
■ Clock generation
2
■ I
C bus busy flag
■ Arbitration Lost Flag
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
I2C Slave Features:
■ Stop bit detection
2
■ I
C bus busy flag
■ Detection of misplaced start or stop condition
■ Programmable I
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
2
C Address detection
11.4.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled ordisabled
by software. The interface is connected to the I2C
bus by a data pin (SDAI) and by a clock pin(SCLI).
It can be connected both with a standard I2C bus
and a FastI2C bus.This selection is madeby soft-
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interfaceautomatically switches from slave to
master after it generates a START condition and
from master toslave in case of arbitrationloss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start conditionand ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The addressis always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledgebit to the transmitter. Referto Fig-
ure 43.
Figure 43. I2C BUS Protocol
SDA
SCL
START
CONDITION
MSB
ACK
12 89
STOP
CONDITION
VR02119B
73/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The I2C interface address and/or general call address can be selected by software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the microcontroller to write the byte in theData Register.
Receiver mode: the interface holds the clock line
low after reception to wait forthe microcontroller to
read the byte in the Data Register.
Figure 44. I2C Interface Block Diagram
The SCL frequency (F
) is controlled by a pro-
scl
grammable clock divider which depends on the
I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O portpins.
DATA REGISTER(DR)
SDA or SDAI
SCL or SCLI
DATA CONTROL
CLOCK CONTROL
CLOCK CONTROLREGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CONTROL LOGIC
74/135
INTERRUPT
I2C BUS INTERFACE (Cont’d)
11.4.4 Functional Description
Refer tothe CR, SR1 and SR2 registersin Section
11.4.7. for the bit definitions.
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2register.
11.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparision
includes theheader sequence (11110xx0) andthe
two most significant bits of the address.
Header matched (10-bit mode only):the interface
generates an acknowledge pulse if the ACK bit is
set.
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the interface generates in sequence:
– Acknowledge pulse ifthe ACK bit is set.
– EVFand ADSL bits aresetwith an interrupt if the
ITE bit is set.
Then theinterface waits fora read of the SR1 register, holding the SCL line low (see Figure 45
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction
Bit) ifthe slave must enterReceiver or Transmitter
mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from theSDA lineinto the DRregister via the internal shift register. Aftereachbyte the interface generates in sequence:
– Acknowledge pulse ifthe ACK bit is set
ST72104G, ST72215G, ST72216G, ST72254G
– EVF and BTFbits areset withan interrupt ifthe
ITE bit is set.
Then the interfacewaits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV2).
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register totheSDA line via the internal shift
register.
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Then the interfacewaits for a read of the SR2 reg-
ister (see Figure 45 Transfer sequencing EV4).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer.In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards thedata,
released the lines and waits for another Start
condition.
If it is a Start then the interfacediscards thedata
and waits for the next slave address on the bus.
– AF: Detectionof anon-acknowledge bit. In this
case, the EVF and AF bits are set with an interrupt if the ITE bit is set.
Note: In both cases, SCLline is not held low; how-
ever, SDAline canremain low due to possible«0»
bits transmitted last. It is then necessary to release
both lines by software.
75/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
11.4.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
After completion of this transfer (andacknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low(see Fig-
ure 45 Transfer sequencing EV6).
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 45 Transfer sequencing EV5).
Slave address transmission
Then the slave address issent tothe SDA line via
the internal shift register.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the following event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bitis set.
Then the master waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 45 Transfer sequencing EV9).
Then the second address byte is sent by the interface.
Next the master must enter Receiver or Transmitter mode.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver
Following the address transmission and after SR1
and CR registershave been accessed, the master
receives bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVFand BTFbitsare setby hardware withan in-
terrupt if the ITE bitis set.
Then the interfacewaits for a read of the SR1 register followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer sequencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after thelast received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
76/135
I2C BUS INTERFACE (Cont’d)
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the internal shiftregister.
The master waitsfor a read of the SR1 register followed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a bytetransfer. In this case, the EVF and
ST72104G, ST72215G, ST72216G, ST72254G
BERR bits are set by hardware with an interrupt
if ITE is set.
– AF: Detectionof anon-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
– ARLO: Detection of an arbitrationlost condition.
In this case theARLO bitis set byhardware (with
an interrupt if the ITE bit is set and the interface
goes automaticallybacktoslavemode (theM/SL
bit is cleared).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmittedlast. It is then necessary to release both lines by software.
77/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
Figure 45. Transfer Sequencing
7-bit Slave receiver:
S Address A Data1 A Data2 A
EV1 EV2 EV2 EV2 EV4
7-bit Slave transmitter:
S Address A Data1 A Data2 A
EV1 EV3 EV3 EV3 EV3-1 EV4
7-bit Master receiver:
S Address A Data1 A Data2 A
EV5 EV6 EV7 EV7 EV7
7-bit Master transmitter:
S Address A Data1 A Data2 A
EV5 EV6 EV8 EV8 EV8 EV8
10-bit Slave receiver:
S Header A Address A Data1 A
EV1 EV2 EV2 EV4
.....
DataN A P
.....
DataN NA P
.....
DataN NA P
.....
DataN A P
.....
DataN A P
10-bit Slave transmitter:
Header A Data1 A
S
r
EV1 EV3 EV3 EV3-1 EV4
DataN A P
....
.
10-bit Master transmitter
S Header A Address A Data1 A
EV5 EV9 EV6 EV8 EV8 EV8
DataN A P
.....
10-bit Master receiver:
S
r
Header A Data1 A
EV5 EV6 EV7 EV7
DataN A P
.....
Legend: S=Start, Sr= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1;AF is cleared by readingSR1 register. BTF is clearedby releasing the
lines (STOP=1, STOP=0) or by writingDR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, clearedby reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
78/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
11.4.5 Low Power Modes
Mode Description
WAIT
HALT
No effect on I
2
C interrupts cause the device to exit from WAIT mode.
I
2
I
C registers are frozen.
In HALT mode, the I
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.4.6 Interrupts
Figure 46. Event Flags and Interrupt Generation
2
C interface.
2
C interface is inactive and does not acknowledge data on the bus. TheI2C interface
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
ITE
INTERRUPT
EVF
*
*
EVF can also be set by EV6 or an error from the SR2 register.
Interrupt Event
10-bit Address Sent Event (Master mode) ADD10
End of Byte Transfer Event BTF Yes No
Address Matched Event (Slave mode) ADSEL Yes No
Start Bit Generation Event (Master mode) SB Yes No
Acknowledge Failure Event AF Yes No
Stop Detection Event (Slave mode) STOPF Yes No
Arbitration Lost Event (Multimaster configuration) ARLO Yes No
Bus Error Event BERR Yes No
Event
Flag
Enable
Control
Bit
ITE
Exit
from
Wait
Yes No
Note: The I2C interrupt events are connected to
the sameinterrupt vector(see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and the I-bit intheCCregister is reset (RIM instruction).
Exit
from
Halt
79/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
11.4.7 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
70
Bit 2 = ACK
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after anaddress byte or
0 0 PE ENGC START ACK STOP ITE
a data byte is received
Acknowledge enable.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE
Peripheral enable.
This bit is set and cleared bysoftware.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– Toenablethe I2C interface, writethe CRregister
TWICEwith PE=1 asthe first write onlyactivates
the interface (only PE is set).
Bit 4 = ENGC
Enable General Call.
This bit is set and cleared bysoftware. It is also
cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: GeneralCall disabled
1: GeneralCall enabled
Bit 3 = START
Generation of a Start condition
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 1 = STOP
Generation of a Stop condition
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
– In master mode:
0: No stop generation
1: Stopgeneration after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In slave mode:
0: No stop generation
1: Release theSCL and SDA lines after the current byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 0 = ITE
Interrupt enable.
This bit is set and cleared bysoftware and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer toFigure46for the relationship betweenthe
events and the interrupt.
.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 45) is detected.
.
80/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
70
EVF ADD10 TRA BUSY BTF ADSL M/SL SB
Bit 7 = EVF
Event flag.
This bit issetby hardware as soon as an event occurs. Itisclearedby software reading SR2 register
in caseof error event or as described in Figure 45.
It isalso cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Mas-
ter mode.
arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY
Bus busy
.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus.This information is still updated when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF
Byte transfer finished.
This bit isset by hardwareas soon asa byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading
SR1 register followedbya read or write of DR register. It isalso cleared by hardware when the interface is disabled (PE=0).
– Followinga byte transmission,thisbitissetafter
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 45). BTF is
cleared by reading SR1 register followed by writing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared byreading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10
10-bit addressing in Master mode
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by awrite intheDR register of the second address
byte. It is also cleared by hardware when the peripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA
Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus
.
Bit 2 = ADSL
Address matched (Slave mode).
This bit isset byhardware as soon as the received
slave address matchedwith the OAR registercontent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
81/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
Bit 1 = M/SL
This bit isset byhardware as soon asthe interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB
This bit is set by hardware as soon as the Start
condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing theaddress byte in DRregister. It is also
cleared by hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
I2C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
70
0 0 0 AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Master/Slave.
Start bit (Master mode).
Acknowledge failure
.
Bit 2 = ARLO
Arbitration lost
This bit is set by hardware when the interface loses the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1 = BERR
Bus error.
This bit is set by hardware when the interface detects a misplacedStart or Stop condition. An interrupt is generated if ITE=1. Itis cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 0 = GCAL
General Call (Slave mode).
This bit is set by hardware when a general calladdress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0: No general call address detected on bus
1: general call address detected on bus
.
Bit 3 = STOPF
Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
82/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
I2C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
70
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
Bit 7 = FM/SM
Fast/Standard I2C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC6-CC0
These bits select the speed of the bus (F
7-bit clock divider.
SCL
) depending on the I2C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
F
SCL=FCPU
– Fast mode (FM/SM=1): F
F
SCL=FCPU
Note: The programmed F
/(2x([CC6..CC0]+2))
SCL
/(3x([CC6..CC0]+2))
SCL
<= 100kHz
SCL
> 100kHz
assumes no load on
SCL and SDA lines.
I2C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
70
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7:0 = D7-D0
8-bit Data Register.
These bits contain the byte tobe receivedortransmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when thesoftware writesin the DR register.
– Receivermode:the first data byte is received au-
tomatically in the DR register using the least significant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
83/135
ST72104G, ST72215G, ST72216G, ST72254G
I2C BUS INTERFACE (Cont’d)
I2C OWN ADDRESS REGISTER (OAR1)
Read / Write
Reset Value: 0000 0000 (00h)
70
I2C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0100 0000 (40h)
70
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
7-bit Addressing Mode
Bit 7:1 = ADD7-ADD1
Interface address
.
These bits define the I2C bus address of theinterface. They are not cleared when the interface is
disabled (PE=0).
Bit 0 = ADD0
Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0
Interface address
.
These are the least significant bits of the I2C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
FR1 FR0 0 0 0 ADD9 ADD8 0
Bit 7:6 = FR1-FR0
Frequency bits.
These bits are set by software only when the interface is disabled(PE=0). To configure the interface
to I2C specifed delays select the value corresponding to the microcontroller frequency F
F
Range (MHz) FR1 FR0
CPU
2.5 - 6 0 0
6 -10 0 1
10 - 14 1 0
14 - 24 1 1
CPU
.
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8
Interface address
.
These are the most significant bits of the I2C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 0 = Reserved.
84/135
I C BUS INTERFACE (Cont’d)
Table 17. I2C Register Map and Reset Values
ST72104G, ST72215G, ST72216G, ST72254G
Address
(Hex.)
0028h
0029h
002Ah
02Bh
02Ch
002Dh
002Eh
Regist er
Label
I2CCR
Reset Value 0 0
I2CSR1
Reset Value
I2CSR2
Reset Value 0 0 0
I2CCCR
Reset Value
I2COA R1
Reset Value
I2COA R2
Reset Value
I2CDR
Reset Value
7654 3210
EVF
0
FM/SM
0
ADD7
0
FR1
0
MSB
0000000
ADD10
0
CC6
0
ADD6
0
FR0
1000
TRA
CC5
ADD5
PE
0
0
0
0
ENGC0START
0
BUSY
0
AF
0
CC4
0
ADD4
0
BTF
0
STO PF0ARLO
CC3
0
ADD3
0
ACK
0
ADSL
0
0
CC2
0
ADD2
0
ADD9
0
STOP
0
M/SL
0
BERR0GCAL
CC1
0
ADD1
0
ADD8
00
ITE
0
SB
0
0
CC0
0
ADD0
0
LSB
0
85/135
ST72104G, ST72215G, ST72216G, ST72254G
11.5 8-BIT A/D CONVERTER (ADC)
11.5.1 Introduction
The on-chipAnalogto Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
11.5.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 47.
Figure 47. ADC Block Diagram
f
CPU
11.5.3 Functional Description
11.5.3.1 Analog Power Supply
V
DDA
and V
are the high and low level refer-
SSA
ence voltage pins. In somedevices (refer to device
pin out description) they are internally connected
to the VDDand VSSpins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
See electrical characteristics section for more details.
f
DIV 2
ADC
86/135
AIN0
AIN1
AINx
ANALOG
MUX
4
R
ADC
ADCDR
CH2 CH1CH3COCO 0 ADON 0 CH0
HOLD CONTROL
C
ADC
ADCCSR
ANALOG TO DIGITAL
CONVERTER
D2 D1D3D7 D6 D5 D4 D0
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.3.2 Digital A/D Conversion Result
The conversionis monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
(high-level voltage reference) then the
DDA
) is greater than or equal
AIN
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
(low-level voltage reference) then the con-
SSA
) is lower than or equal to
AIN
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.5.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 48:
■ Sample capacitor loading [duration: t
During this phase, the V
measured is loaded into the C
input voltage to be
AIN
ADC
LOAD
]
sample
capacitor.
■ A/D conversion [duration: t
CONV
]
During this phase, the A/D conversion is
computed (8successive approximations cycles)
and the C
from the analog input pin to get the optimum
sample capacitor is disconnected
ADC
analog to digital conversion accuracy.
While theADC is on, these two phasesare continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
11.5.3.4 Software Procedure
Refer tothe control/status register(CSR) and data
register (DR) in Section 11.5.6 for the bit definitions and toFigure 48 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
ADC
=2/f
CPU
).
ST72104G, ST72215G, ST72216G, ST72254G
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port tobe read as
a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable theA/D converter
and to start the first conversion. From thistime
on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt isgenerated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to theCSR register (with ADON set)aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 48. ADC Conversion Timings
ADON
HOLD
CONTROL
t
LOAD
t
CONV
11.5.4 Low Power Modes
Mode Description
WAIT No effect on A/D Converter
A/D Converter disabled.
HALT
After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note:TheA/D convertermay be disabled byresetting the ADON bit. This feature allows reduced
power consumptionwhennoconversionis needed
and between single shot conversions.
11.5.5 Interrupts
None
ADCCSR WRITE
OPERATION
COCO BIT SET
87/135
ST72104G, ST72215G, ST72216G, ST72254G
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUSREGISTER (CSR)
Read/Write
Reset Value: 0000 0000(00h)
70
COCO 0 ADON 0 CH3 CH2 CH1 CH0
Bit 7 = COCO
Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from theDR register
Bit 6 = Reserved.
Bit 5 = ADON
must always be cleared.
A/D Converter On
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
70
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7:0 = D[7:0]
Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
This bit is set and cleared bysoftware.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved.
must always be cleared.
Bit 3:0 = CH[3:0]
Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin* CH3 CH2 CH1 CH0
AIN0 0 0 0 0
AIN1 0 0 0 1
AIN2 0 0 1 0
AIN3 0 0 1 1
AIN4 0 1 0 0
AIN5 0 1 0 1
AIN6 0 1 1 0
AIN7 0 1 1 1
AIN8 1 0 0 0
AIN9 1 0 0 1
AIN10 1 0 1 0
AIN11 1 0 1 1
AIN12 1 1 0 0
AIN13 1 1 0 1
AIN14 1 1 1 0
AIN15 1 1 1 1
*Note: Thenumber of pins AND the channel selection varies accordingto the device.Referto thedevice pinout.
88/135
8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 18. ADCRegister Map and Reset Values
ST72104G, ST72215G, ST72216G, ST72254G
Address
(Hex.)
0070h
0071h
Register
Label
ADCDR
Reset Value
ADCCSR
Reset Value
76543210
D7
0
COCO
00
D6
0
D5
0
ADON
00
D4
0
D3
0
CH3
0
D2
0
CH2
0
D1
0
CH1
0
D0
0
CH0
0
89/135
ST72104G, ST72215G, ST72216G, ST72254G
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
Addressing Mode Example
Inherent nop
Immediate ld A,#$55
Direct ld A,$55
Indexed ld A,($55,X)
Indirect ld A,([$55],X)
Relative jrne loop
Bit operation bset byte,#5
The ST7 Instruction set is designed to minimize
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful be-
cause itcan usethe full64Kbyte address space,
however it uses more bytes and moreCPU cycles.
– Short addressing modeisless powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size ismore
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7Assembler optimizes the use of long and
short addressing modes.
the numberof bytes requiredper instruction: Todo
Table 19. ST7 Addressing Mode Overview
Mode Syntax
Inherent nop + 0
Immediate ld A,#$55 + 1
Short Direct ld A,$10 00..FF + 1
Long Direct ld A,$1000 0000..FFFF + 2
No Offset Direct Indexed ld A,(X) 00..FF
Short Direct Indexed ld A,($10,X) 00..1FE + 1
Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2
Short Indirect ldA,[$10] 00..FF 00..FF byte + 2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2
Relative Direct jrne loop PC-128/PC+127
Relative Indirect jrne [$10] PC-128/PC+127
Bit Direct bset $10,#7 00..FF + 1
Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2
Bit Direct Relative btjt $10,#7,skip 00..FF + 2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3
Destination/
Source
Pointer
Address
(Hex.)
1)
1)
00..FF byte + 2
Pointer
Size
(Hex.)
Length
(Bytes)
+ 0 (with X register)
+ 1 (with Y register)
+1
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
90/135
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fullyspecifies all the required information for the CPU to process the operation.
Inherent Instruction Function
NOP No operation
TRAP S/W Interrupt
WFI
HALT
RET Sub-routine Return
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
RIM Reset Interrupt Mask
SCF Set Carry Flag
RCF Reset Carry Flag
RSP Reset Stack Pointer
LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
MUL Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
SWAP Swap Nibbles
Wait For Interrupt (Low Power
Mode)
Halt Oscillator (Lowest Power
Mode)
Shift and Rotate Operations
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction Function
LD Load
CP Compare
BCP Bit Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC Arithmetic Operations
ST72104G, ST72215G, ST72216G, ST72254G
12.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The addressis a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The addressis a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
12.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, whichis defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byteafter theopcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset isabyte, thus requires only one byteafter the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FFaddressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
91/135
ST72104G, ST72215G, ST72216G, ST72254G
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
12.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative Direct/
Indirect Instructions
JRxx Conditional Jump
CALLR Call Relative
Function
The relative addressing mode consists oftwo submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
Longand Short
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC
BCP Bit Compare
Short Instructions Only Function
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
Arithmetic Addition/subtraction operations
Bit Test and Jump Operations
Shift and Rotate Operations
Function
92/135
12.2 INSTRUCTION GROUPS
ST72104G, ST72215G, ST72216G, ST72254G
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Code Condition Flagmodification SIM RIM SCF RCF
be subdivided into 13 main groups as illustrated in
the following table:
Using a pre-byte
The instructions are described with one to four
bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC opcode
PC+1 Additional word (0 to 2) according
to the number of bytesrequired tocompute the effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precedethe opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to aninstruction using indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
93/135
ST72104G, ST72215G, ST72216G, ST72254G
INSTRUCTION GROUPS (Cont’d)
Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A = A + M + C A M H N Z C
ADD Addition A = A + M A M H N Z C
AND Logical And A = A . M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H = 1 ?
JRNH Jump if H = 0 H = 0 ?
JRM Jump if I = 1 I = 1 ?
JRNM Jump if I = 0 I = 0 ?
JRMI Jump if N = 1 (minus) N = 1 ?
JRPL Jump if N = 0 (plus) N = 0 ?
JREQ Jump if Z = 1 (equal) Z = 1 ?
JRNE Jump if Z = 0 (not equal) Z = 0 ?
JRC Jump if C = 1 C = 1 ?
JRNC Jump if C = 0 C = 0 ?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >
94/135
ST72104G, ST72215G, ST72216G, ST72254G
INSTRUCTION GROUPS (Cont’d)
Mnemo Description Function/Example Dst Src H I N Z C
JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A =X * A A, X, Y X, Y, A 0 0
NEG Negate (2’s compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A = A + M A M N Z
POP Pop from the Stack pop reg reg M
pop CC CC M H I N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C = 0 0
RET Subroutine Return
RIM Enable Interrupts I = 0 0
RLC Rotate left true C C <= Dst <= C reg, M N Z C
RRC Rotate right true C C => Dst => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Subtract with Carry A = A - M - C A M N Z C
SCF Set carry flag C = 1 1
SIM Disable Interrupts I = 1 1
SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C
SLL Shift left Logic C <= Dst <= 0 reg, M N Z C
SRL Shift right Logic 0 => Dst => C reg, M 0 Z C
SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C
SUB Subtraction A = A - M A M N Z C
SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1
WFI Wait for Interrupt 0
XOR Exclusive OR A = A XOR M A M N Z
95/135
ST72104G, ST72215G, ST72216G, ST72254G
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to VSS.
13.1.1 Minimum and Maximum values
Unless otherwisespecifiedthe minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the minimum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
13.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range)and VDD=3.3V (for the 3V≤VDD≤4V
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and arenottested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 49.
13.1.5 Pin input voltage
The input voltage measurement on a pin of thedevice is described in Figure 50.
Figure 50. Pin input voltage
ST7 PIN
V
IN
Figure 49. Pin loading conditions
C
L
96/135
ST7 PIN
13.2 ABSOLUTE MAXIMUM RATINGS
ST72104G, ST72215G, ST72216G, ST72254G
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these condi-
13.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
V
DD-VSS
V
IN
V
ESD(HBM)
V
ESD(MM)
Supply voltage 6.5
Input voltage on any pin
1) &2)
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
13.2.2 CurrentCharacteristics
Symbol Ratings Maximum value Unit
I
VDD
I
VSS
Total current into VDDpower lines (source)
Total current out of VSSground lines (sink)
Output current sunk by any standard I/O and control pin 25
I
IO
Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
Injected current on ISPSELpin ± 5
I
INJ(PIN)
2) & 4)
Injected current on RESET pin ± 5
Injected current on OSC1 and OSC2 pins ± 5
Injected current on any other pin
INJ(PIN)
2)
Total injected current (sum of all I/O and control pins)
ΣI
13.2.3 Thermal Characteristics
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
VSS-0.3 to VDD+0.3
see Section 13.7.2 ”Absolute Electrical Sensitivity” on page 110
3)
3)
5) & 6)
5)
80
80
± 5
± 20
V
mA
Symbol Ratings Value Unit
T
STG
T
J
Storage temperature range -65 to +150 °C
Maximum junction temperature
(see Section 14.2 ”THERMAL CHARACTERISTICS” on page 127 )
Notes:
1. Directly connecting the RESET and I/O pins to V
is generated or an unexpected change of theI/O configuration occurs (for example, due to a corrupted program counter).
or VSScould damage the device if an unintentional internal reset
DD
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pinsmust betied in the same way to V
2. When the current limitation is not possible, the V
I
3. All power (V
specification. A positive injection is induced by VIN>VDDwhile a negative injection is induced by VIN<VSS.
INJ(PIN)
) and ground (VSS) lines must always be connected to the external supply.
DD
absolute maximum rating must be respected, otherwise refer to
IN
orVSSaccording totheir reset configuration.
DD
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effectson the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Puredigital pins must have a negative injection less than1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
is the absolute sum of the positive
INJ(PIN)
INJ(PIN)
maxi-
6. True open drain I/O port pins do not accept positive injection.
97/135
ST72104G, ST72215G, ST72216G, ST72254G
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
Symbol Parameter Conditions Min Max Unit
V
f
OSC
T
DD
A
Supply voltage see Figure 51 and Figure 52 3.0 5.5 V
≥3.5V for ROM devices
External clock frequency
V
DD
≥4.5V for FLASH devices
V
DD
V
≥3.0V 0
DD
1)
0
1)
16
8
1 Suffix Version 0 70
Ambient temperature range
6 Suffix Version -40 85
7 Suffix Version -40 105
3 Suffix Version -40 125
MHz
°C
Figure 51. f
FUNCTIONALITY
NOT GUARANTEED
Figure 52. f
FUNCTIONALITY
NOT GUARANTEED
OSC
IN THIS AREA
OSC
IN THIS AREA
Maximum Operating Frequency Versus VDDSupply Voltage for ROM devices
f
[MHz]
OSC
16
8
4
1
0
2.5 3 3.5 4 4.5 5 5.5
FUNCTIONALITY
GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
WITH RESONATOR
SUPPLYVOLTAGE [V]
Maximum Operating Frequency Versus VDDSupply Voltage for FLASH devices
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
f
[MHz]
OSC
16
8
4
1
0
2.5 3 3.5 4 4.5 5 5.5
FOR TEMPERATURE HIGHER THAN 85°C
3.85
3)
FUNCTIONALITY
GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEE D
IN THIS AREA
WITH RESONATOR
SUPPLYVOLTAGE [V]
2)
1)
2)
3)
1)
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T
3. FLASH programming tested in production at maximum T
=3V, f
V
DD
CPU
=4MHz.
=-40 to +125°C.
A
with two different conditions: VDD=5.5V, f
A
=8MHz and
CPU
98/135
ST72104G, ST72215G, ST72216G, ST72254G
OPERATING CONDITIONS (Cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD,f
Symbol Parameter Conditions Min Typ
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
IT+-VIT-
Not detected by the LVD 40 ns
V
IT+
V
IT-
V
hyst
Vt
POR
t
g(VDD)
Reset release threshold
rise)
(V
DD
Reset generation threshold
fall)
(V
DD
LVD voltage threshold hysteresis V
VDDrise time rate
Filtered glitch delay on V
3)
2)
DD
Figure 53. High LVD Threshold Versus VDDand f
DEVICE UNDER
RESET
IN THIS AREA
f
OSC
[MHz]
FUNCTIONALITY AND RESET NOT GUARANTEED INTHIS AREA
16
8
FOR TEMPERATURES HIGHER THAN 85°C
, and TA.
OSC
for FLASH devices
OSC
2)
4.10
2)
3.75
2)
3.25
3.85
3.50
3.00
200 250 300 mV
0.2 50 V/ms
3)
1)
Max Unit
4.30
3.90
3.35
4.05
3.65
3.10
4.50
4.05
3.45
4.25
3.80
3.20
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
V
0
2.5 3 3.5 4 4.5 5 5.5
Figure 54. Medium LVD Threshold Versus VDDand f
DEVICE UNDER
RESET
IN THIS AREA
f
[MHz]
OSC
16
8
0
2.5 3 V
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
IT-
Figure 55. Low LVD Threshold Versus VDDand f
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
DEVICE UNDER
RESET
IN THIS AREA
f
OSC
[MHz]
16
8
0
2.5 V
≥3V 3.5 4 4.5 5 5.5
IT-
≥3.85
V
IT-
OSC
≥3.5V 4 4.5 5 5.5
for FLASH devices
OSC
Notes:
1. LVD typical data are based on T
=25°C. They are given only as design guidelines and are not tested.
A
2. Data based on characterization results, not tested in production.
3. The V
rise time rate condition isneeded to insurea correct device power-on and LVD reset. Not tested in production.
DD
for FLASH devices
2)
SUPPLYVOLTAGE [V]
3)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLYVOLTAGE [V]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLYVOLTAGE [V]
99/135
ST72104G, ST72215G, ST72216G, ST72254G
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
Figure 56. High LVD Threshold Versus VDDand f
f
[MHz]
OSC
DEVICE UNDER
RESET
IN THIS AREA
16
8
OSC
for ROM devices
2)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
0
2.5 3 3.5 4 4.5 5 5.5
V
≥3.85
IT-
Figure 57. Medium LVD Threshold Versus VDDand f
f
[MHz]
OSC
DEVICE UNDER
RESET
IN THIS AREA
Figure 58. Low LVD Threshold Versus VDDand f
DEVICE UNDER
RESET
IN THIS AREA
16
8
0
2.5 3 V
[MHz]
f
OSC
16
8
0
2.5 V
≥3.5V 4 4.5 5 5.5
IT-
OSC
≥3.00V 3.5 4 4.5 5 5.5
IT-
for ROM devices
OSC
for ROM devices
SUPPLYVOLTAGE [V]
2)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLYVOLTAGE [V]
2)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLYVOLTAGE [V]
Notes:
1. LVD typical data are based on T
2. The minimum V
rise time rateis needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
100/135
=25°C. They are given only as design guidelines and are not tested.
A
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