SGS Thomson Microelectronics ST70136G, ST70136B Datasheet
ST70136
CPE ADSL ANALOG FRONT END
■ WIDE TRANSMIT AND RECEIVE DYNAMIC
RANGE TO REDUCE EXTERNAL
FILTERING REQUIREMENTS
■ RECEIVE PROGRAMMABLE GAIN: 0 TO
31dB GAIN IN 1dB STEPS
■ RECEIVE PROGRAMMABLE ATTENUATOR
0,-4dB, -8dB, -12dB
■ 12-BIT A/D CONVERTER IN RECEIVE PATH
■ TRANSMIT PROGRAMMABLE GAIN: 0 TO
-15dB IN 1dB STEPS
■
14-BIT D/A CONVERTER IN TRANSM IT PATH
■ LOW POWE R MODE: 10mW IN LISTE NING
MODE, 250
µ
W IN POWER DOWN
■ TONE DETECTOR: ACTIVITY DETECTION
FOR WAKE-UP F UNCTION
■ 64-PIN TQFP PACKAGE
■ 64-PIN L FBGA PACKAGE
■ 0.50
µ
m, 5V BICMOS TECHNOLOGY
■ 3.3V DIGITA L I NTERFACE
■ 5V ANALOG IN TERFACE
INTRODUCTION
The ST70136 ADSL Analog Front End (AFE) chip
implements the analog transceiver functions
required in a Custome r Premise ADSL m odem. It
connects the digital modem chip with the loop
driver and hybrid balance circuits.
The AFE has been designed with high dynamic
range in order to greatly reduce the external filtering requirements at the front end.
The AFE chip and its companion digital chip along
with a loop driver, implement the complete
G.992.2 and G.992.1 DMT modem solution.
The AFE receive path contains a programmable
gain amplifier (RxPGA), a low pass anti-aliasing
filter, and a 12-bit A/D converter. The RxPGA is
digitally programmable from 0 to 31dB in 1dB
steps.
The AFE transmit path consists of a 14-bit D/A
converter, followed by a programmable gain
amplifier (TxPGA). The transmit gain is programmable from 0 to -15dB in 1dB steps.
TQFP64 Fu ll Pla st i c
(10 x 10 x 1.40 mm)
ORDER CODE: ST70136G
LFBGA64
(8 x 8 x 1.7 mm)
ORDER CODE: ST70136B
Figure 1 : Overall Application Block Diagram
Software for Control xDSL
PC
PCI
or
USB
PCI
or
USB
ST70137
DMT
xDSL
AFE
ST70136
LOOP
DRIVER
TS612/TS652
LINE
HYBRID
1/24September 2001
2/24
CTRLOUT
2
47
CTRLIN
1
48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 5 0 49
VDDOSC
XTALO
XTALI
VSSOSC
VSSESD
VSSA6
VCOCAP
IVCO
VCXOUT
TOP
TON
VDDA6
GC0
GC1
VDDA5
VSSA5
VSS
TEST
NRESET
VDD
PWD
SUSPEND
VDDA2
VSSA2
VSAD
VSRX
VSSA1
RXP
RXN
VDDA1
VDDA3
IREF50U
22 23 24 25 26 27 28 29 30 31 3217 18 19 20 21
TX0
16
33
TX1
15
34
TX2
14
35
TX3
13
36
VSSIO
12
37
RX0
11
38
RX1
10
39
RX3
RX2
8
9
ST70136G
41
40
ACTD
7
42
CLKM
6
43
CLKWD
5
44
VDDIO
4
45
R/W
3
46
ST70136 Pinout
ST70136
VSDA
VDDA4
PGAP
TXIN
TXP
TXN
TXIP
PGAN
VSSA4
VSSA3
V290DA
V125AD
V250AD
V375AD
VSBIAS
V3P75V
1 - PIN LIST
The following list gives the different PIN Types:
AI Analog Input
AIO Analog Input/Output
AO Analog Ouptut
DI Digital Input
DIO Digital Input/Output
DO Digital Output
VDDA Analog Power Supply
VDDD Digital Power Supply
VSSA Analog Ground
VSSD Digital Ground
Table 1 : Pin Assignment
Pins
Name Type Description
TQFP LFBGA
1 B2 CTRLIN DI Digital input for control interface
2 C3 CTRLOUT DO Digital output for control interface
3 C2 R/NW* DI Selection of read or write mode for control interface
4 B1 VDDIO VDDD I/O buffer supply voltage
5 A1 CLKWD DO 8.832MHz output clock. Used to synchronize RX/TX word data
6 C1 CLKM DO 35.328MHz Master Clock. Xtal buffer
7 D2 ACTD O Tone Detector Activation
8 D1 RX3 DO Received data output
9 E2 RX2 DO Received data output
10 E1 RX1 DO Received data output
11 F2 RX0 DO Received data output
12 G2 VSSIO VDDD I/O buffer ground voltage
13 F1 TX3 DI Transmit data input
14 G1 TX2 DI Transmit data input
15 H2 TX1 DI Transmit data input
16 H1 TX0 DI Transmit data input
17 E3 VSS VSSD Core digita l ground
18 G3 TEST DI Test mode is activated with TEST=1. Must be tied to ground in normal
19 E4 NRESET* DI Reset input. All digital circuitry is well defined after a negative pulse on
20 H3 VDD VSSD Core digital supply (3.3V)
21 F3 PWD DI Power Down pin
22 G4 SUSPEND DI Suspend Mode pin
23 F4 VDDA2 VDDA ADC supply voltage (5V)
24 H4 VSSA2 VSSA ADC ground voltage
25 G5 VSAD VSSA Substrate voltage for RX-AD path (Must be connected to VSSAx)
26 E5 VSRX VSSA Substrate voltage for RXPGA path (Must be connected to VSSAx)
27 H5 VSSA1 VSSA RXPGA ground voltage
28 H6 RXP AI Positive Analog Receive input
exchange, and master clock of register control interface
mode
this input
ST70136
3/24
ST70136
Table 1 : Pin Assignment (continued)
Pins
Name Type Description
TQFP LFBGA
29 H7 RXN AI Negative Analog Receive input
30 G6 VDDA1 VDDA RXPGA voltage supply (5v)
31 F5 VDDA3 VDDA Bias and References voltage supply (5v)
32 H8 IREF50U AI External resistor for bias current 50kΩ
33 G8 V3P75V AO 3.75v output from bandgap; 0.22µF decoupling
34 G7 VSBIAS VSSA Substrate voltage for biasing & reference cell (Must be connected to
35 F7 V375AD AO 3.75 volt reference voltage. Need decoupling 0.1µF
36 F8 V250AD AO 2.50 volt reference voltage. Need decoupling 0.1µF
37 F6 V125AD AO 1.25 volt reference voltage. Need decoupling 0.1µF
38 E7 V290DA AO 2.90 volt reference voltage. Need decoupling 0.1µF
39 E8 VSSA3 VSSA Biasing and References ground voltage
40 E6 VSSA4 VSSA Tx path ground voltage
41 D6 PGAN AO Negative TXPGA output
42 D8 TXIP AI Positive analog input for Tx external filtering
43 D7 TXN AO Negative analog transmit output
44 C7 TXP AO Positive analog transmit output
45 C8 TXIN AI Negative analog input for Tx external filtering
46 B7 PGAP AO Positive TXPGA output
47 B8 VDDA4 VDDA Tx analog supply voltage (5V)
48 A8 VSDA VSSA Substrate voltage for DAC path (Must be connected to VSSAx)
49 A7 VSSA5 VSSA DAC path ground voltage
50 C6 VDDA5 VDDA DAC analog supply voltage (5v)
51 A6 GC1 DO MSB for external gain control
52 B6 GC0 DO LSB for external gain control
53 D5 VDDA6 VDDA VCXO & Tone detector Input analog supply voltage (5v)
54 C5 TON AI Negative tone detector input
55 B5 TOP AI Positive tone detector input
56 D4 VCXOUT AIO VCXO output current
57 A5 IVCO AIO VCXO input current
58 C4 VCOCAP AO VCXO output filtering
59 A4 VSSA6 VSSA VCXO & Tone detector analog ground voltage
60 B4 VSSESD VSSD Ground voltage reference for ESD
61 D3 VSSOSC VSSD Ground voltage for Xtal oscillator
62 A3 XTALI DI Xtal oscillator input
63 B3 XTALO DO Xtal oscillator output
64 A2 VDDOSC VDDD Supply voltage for Xtal cell (3.3v)
VSSAx)
* A "N" me ans active low. Example: R/NW means write active low.
4/24
2 - PIN DESCRIPTION
ST70136
2.1 - Analog Power Supplies
These pins are the posit ive analog power supply
voltage for the DAC and the ADC section. It is not
internally connecte d to digital supply. In any case
the voltage on these pins m ust be hi gher or equa l
to the voltage of the Digital power supply.
2.2 - Digital Power Supplies
These pins are the power supply pins that are
used by the internal digital circuitry. All DVDD pins
must be connected together to a +3.3 V supply.
2.3 - Anal og Gr ound and Substr at e
These pins are the ground return of the analog
DAC and ADC blocks. The analog VDDA shoul d
be decoupled with respect to the analog ground.
Decoupling capacitors should be as close as pos sible to the supplies pins. All grounds must be tied
together.
2.4 - Digita l Ground
These pins are the ground ret urn of the di gital circuitry. The digital p ower supplies must shou ld be
decoupled with respect to the digital ground.
Decoupling capacitors should be as close as pos sible to the supplies pins. All grounds must be tied
together.
2.5 - Powerd own - PWD
When pin PWD =”1”, the chip is set in low power
mode.
2.6 - Suspend
The SUSPEND pin is used to control the output of
CLKM. When SUSPEND is low CLKM output is
enabled otherwise CLKM is disabled.
2.8.2 - V3P75V
This pin is the 3.75V Bandgap output and shoul d
be externally decoupled with an external capacitor
of 0.22uF.
2.8.3 - IREF50U
This pin is used for s etting the bias current and
must be externally connected to a resistor of
2.5V / 50
µ
A equals 50kΩ.
2.8.4 - V290DA
This pin is the 2.9V transmit DAC output reference
voltage and must be decoupled externally.
2.9 - Analog Transmit Output
2.9.1 - TXP
This pin is t he n on-invert ing out put of t he full y dif ferential analog amplifier.
2.9.2 - TXN
This pin is the inverting output of the fully differential analog amplifier.
2.9.3 - TXIP
This pin is the d ifferential non-inverting input for
external filtering.
2.9.4 - TXIN
This pin is the di fferential inverting input f or e xternal filtering.
2.9.5 - PGAP
This pin is the differential non-inverting PGA output.
2.9.6 - PGAN
This pin is the differential inverting PGA output.
2.10 - An alog Rece ive Input
2.7 - Reset
The reset function is implied when the NRESET
pin is at a low voltage input level. In this condition,
the reset function can be easily used f or power up
reset conditions. Reset is asynchronous, tenths of
ns are enough to put the IC in reset. After reset, all
registers are set to their default value.
2.8 - Reference Voltages
2.8.1 - V125AD, V250AD, V375AD
These pins are used to externally decouple the
internal reference voltages used for the ADC
(1.25V, 2.5V, 3.75V).
2.10.1 - RXN
This pin is the differential inverting receive input.
2.10.2 - RXP
This pin is the differential non-inverting receive
input.
2.11 - Tone Detector
The analog input differential signal must be less
than 8V peak to peak. These pins are used for
activity detection when in sleeping mode.
2.11.1 - TON
This pin is the differential inverting tone d etector
input.
5/24
ST70136
2.11.2 - TOP
This pin is the differential non-inverting tone
detector input.
2.11.3 - ACTD
This pin is active when t one 40 or 72 has been
detected in sleeping mode (see control register)
2.12 - CRYSTAL
These pins must be tied to an external crystal
(F = 35.328MHz).
2.12.1 - XTAL I
This pin is the crystal os cillat or input .
2.12.2 - XTAL O
This pin is the c r yst a l os c illa t or ou t pu t.
2.13 - VCXO
2.13.1 - IVCO
This pin is the current reference for the VCO DAC
2.13.2 - VCOCAP
This pin is used to introduce time constant. The
tuning is done by connecting an external capacitor
2.13.3 - VCXOUT
This pin is the output control current generated by
a 8 bit DAC.
2.14 - Control Serial Interface
Access to the cont rol register c an b e done only in
stable state fonctionality:
SUSPEND = "0".
2.14.1 - CTRLIN
This pin is used to program the internal registers.
The data burst is c omp osed of 16 bits sampled at
CLKM when CL KWD = 1. The first bit is used as
start bit (’0’), the three LSBs being used to identify
the data contained in the twelve remaining bits.
The start bit b15 (b5 = 0) is transmitted first followed by bits b[14:0]. At leas t 1 stop bit "1" need
to be provided to validate the data.
2.14.2 - CTRLOUT
This pin is the con trol register output. The burst
data on this pin is the value of the register
addressed by CTRLIN.
2.14.3 - CLKWD
This pin is the word clock used to sample the control information and equal to CLKM / 4.
2.14.4 - R/NW
This pin is used for the read and write operation
for the control interface and sampled at the s ame
time than bit b15 of CTRLIN.
2.14.5 - Digital Interface
The interface is a nibble serial interface running at
8.832MHz sampling frequency. The data are presented in 16bits format, and transferred in groups
of 4 bits (nibbles). The LSBs are transferred first.
Data is transmitted on the rising e dge of the m aster clock CL KM
2.14.6 - CLKM
This pin is the master c lock equal to 35.328MHz
and is the sampling clock of the input / output
data.
2.14.7 - TX0, TX1, TX2, TX3
These pins are the digital transmit data input.
2.14.8 - RX0, RX1, RX2, RX3
These pins are the digital receive data output.
2.15 - Test
This pin is dedicated to put the ST70136 i n test
mode.
6/24
3 - BLOCK DIAGRAM
XTALI XTALO
62
63
TEST
18
SUSPEND
22
PWD
21
V125AD
37
V250AD
36
V375AD
35
V290DA
38
ST70136
V3P75V IREF50U
33 32
TX0
TX1
TX2
TX3
CLKM
RX0
RX1
RX2
RX3
CLKWD
ACTD
CTRLIN
CTRLOUT
R/NW
NRES ET
16
15
14
13
6
11
10
9
8
5
7
1
2
3
19
INTERNAL
VCXO
CLOCK
GENERATOR
1
1
1
1
INTERFACE
1
1
1
1
CONTROL
INTERFACE
DATA
MANAGEMENT
16
16
8
POWER
14-BIT
DAC
8-BIT
DAC
12-BIT
ADC
AAF
TONE
DETECTOR
BANDGAP
REFERENCE
+-
PA
+-
TxPGA
RxPGA
ATT
42
43
44
45
41
46
29
28
54
55
52
51
56
TXIP
TXN
TXP
TXIN
PGAN
PGAP
RXN
RXP
TON
TOP
GC0
GC1
VCXOUT
58
VCOCAP IVCO
57
7/24
ST70136
4 - FUNCTIONAL DESCRIPTION
4.1 - General
The ST70136 consists of the following functional
blocks:
– Transmit Signal Path
– Receive Signal Path
– Bias Voltage and Current Generation
– Digital Data Interface
– Control Serial Interface
– Tone Detector
– Power Down m ode ma nagem ent
4.2 - Transmit Path Description
The transmit path contains the 14-bit digital to
analog converter (DAC) necessary to generate
the transmit signal from a 16-bit digital input word.
This transmit signal is then scaled by the on chip
programmable gain amplifier (TxPGA) from 0 to
-15dB in 1dB s teps. The scaled output signal is
then driven off chip to the external filters and
power amplifier (PA) which drives the DMT signal
to the subscriber loop. The transmit path is fully
differential.
4.3 - Receive Path Description
The receive path contains first an attenuator
(which allows the selection between 4 at tenuated
versions of the signal) followed by a program mable gain amplifier (RxPGA), a 1st order low pass
anti-aliasing filter, and a 12-bit analog to digital
converter (ADC). The RxPGA gain is digitally programmable from 0 to 31dB in 1dB steps. The
receive path is fully differential.
4.4 - VCXO
The ST70136 contains the circuits required to
construct an internal VCXO. It is divided in a crystal driver and an auxiliary 8 bits DAC for timing
recovery. The crystal driver is able to operate at
35.328MHz.
The DAC which is driven by the CTRLIN p in (the
input of the Serial Control Interface), provides a
current output with 8 bits resolution and can be
used to tune the crystal frequency with the help of
external components. A time constant between
DAC input and VCXOUT can be introduced (via
CTRLIN interface) and p rogram med with the hel p
of an external capacitor (on VCOCAP pin).
4.5 - Bias Voltage and Current Generation
The bias circuitry c ontains a bandgap voltage reference from which the converters references a nd
analog ground voltages are generat ed. This block
also generates a n a ccurate bias current us ing an
external resistor.
4.6 - Digital Data Interface
To facilitate data transfer between the ST70136
and the digital data pump, a 4-bit wide serial interface for the trans mit and receive path is incorporated into the AFE.
This interface consists of four transmit pins
(TX[0:3]), four receive pins (RX[0:3]), and the necessary control signals (CLKM, CLK WD) to transmit and receive the required data.
8/24
Loading...