SGS Thomson Microelectronics ST62T08CM6, ST62P20CM6, ST62P20CM3, ST62P20CM1, ST62P10CM6 Datasheet
...
April 1999 1/70
Rev. 2.7
ST62T08C/T09C
ST62T10C/T20C/E20C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHzMaximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 InterruptVectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 64bytes
■ User Programmable Options
■ 12 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62T08C)
■ 4 I/Olinescan sink up to 20mA todrive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
■ Digital Watchdog
■ Oscillator SafeGuard
■ Low Voltage Detector for Safe Reset
■ 8-bit A/D Converter with up to 8 analog inputs
■ On-chip Clockoscillatorcanbedrivenby Quartz
Crystal Ceramic resonator or RC network
■ Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
PDIP20
PSO20
CDIP20W
(See end of Datasheet for Ordering Information)
DEVICE
OTP
(Bytes)
EPROM
(Bytes)
I/O Pins
Analog
inputs
ST62T08C 1036 - 12 ST62T09C 1036 - 12 4
ST62T10C 1836 - 12 8
ST62T20C 3884 - 12 8
ST62E20C - 3884 12 8
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Table of Contents
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Document
Page
2
ST62T08C/T09C/ST62T10C/T20C/E20C . . ................1
1 GENERAL DESCRIPTION . . . . . . ................................................ 4
1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 4
1.2 PIN DESCRIPTIONS . . . . . . ................................................5
1.3 MEMORY MAP . . . . . . . . . . ................................................ 6
1.3.1 Introduction . . . ..................................................... 6
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . .................................7
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . ............................... 8
1.3.4 Stack Space . . . . . . . . . . . . ............................................ 8
1.3.5 Data Window Register (DWR) . .........................................9
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . .............................. 10
1.4.2 Program Memory . . . ................................................ 11
1.4.3 EPROM Erasing .................................................... 11
2 CENTRAL PROCESSING UNIT . . ............................................... 12
2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................12
2.2 CPU REGISTERS . . . .................................................... 12
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . ................... 14
3.1 CLOCK SYSTEM . . . . . .. . . . . . . ...........................................14
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . ................................. 14
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 15
3.1.3 Oscillator Safe Guard . . . . . ........................................... 15
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 RESET Input . . .................................................... 18
3.2.2 Power-on Reset .................................................... 18
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . ................................. 19
3.2.4 LVD Reset . . . . . . . . . ............................................... 19
3.2.5 Application Notes . . . ................................................ 19
3.2.6 MCU Initialization Sequence . . . . . . . . ..................................20
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . .................................. 22
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Application Notes . . . ................................................ 24
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Interrupt request . ................................................... 26
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . ................................. 27
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . ............... 28
3.4.4 Interrupt sources . . . . . . . . . . . ........................................ 28
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 30
3.5.1 WAIT Mode ....................................................... 30
3.5.2 STOP Mode . . . . . . . . ...............................................30
3.5.3 Exit from WAIT and STOP Modes . . . . ..................................31
4 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 32
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . ...........................................32
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . ........................... 33
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3 I/O Port Option Registers . . . . . . . . . . . .................................. 35
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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.5 I/O Port Data Registers . . . . . . ........................................ 35
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 37
4.2.1 Timer Operating Modes . . . . . . . . . . . . ..................................38
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . ................................ 38
4.2.3 Application Notes . . . ................................................ 39
4.2.4 Timer Registers . . . . . ............................................... 39
4.3 A/D CONVERTER (ADC) . . ............................................... 40
4.3.1 Application Notes . . . ................................................ 40
5 SOFTWARE . . . . . . . . . . . . . . . . . ............................................... 42
5.1 ST6 ARCHITECTURE . ................................................... 42
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . ..................................42
5.3 INSTRUCTION SET . . . . . . . ............................................... 43
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . .............................. 48
6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................ 48
6.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 49
6.3 DC ELECTRICAL CHARACTERISTICS .. . . . . . . . . . . . . . . . . . . . . . . . . . ...........50
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 TIMER CHARACTERISTICS . . . . ...........................................52
7 GENERAL INFORMATION . . . . . . . . . . ...........................................58
7.1 PACKAGE MECHANICAL DATA . . . . . . .. . . . . . . . . . ........................... 58
7.2 .ORDERING INFORMATION . . . . ...........................................59
ST62P08C/P09C/ST62P10C/P20C . . . . . . . . . . . . . . . . . . . . . . 61
1 GENERAL DESCRIPTION . . . . . . ............................................... 62
1.1 INTRODUCTION . . . . . . . . . . . . . ...........................................62
1.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 62
1.2.1 Transfer of Customer Code . . . . . . . . . . ................................. 62
1.2.2 Listing Generation and Verification . . . . ................................. 62
ST6208C/09C/ST6210C/20C ...........................65
1 GENERAL DESCRIPTION . . . . . . ............................................... 66
1.1 INTRODUCTION . . . . . . . . . . . . . ...........................................66
1.2 ROM READOUT PROTECTION .. . . . . . . . . . . ................................66
1.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 68
1.3.1 Transfer of Customer Code . . . . . . . . . . ................................. 68
1.3.2 Listing Generation and Verification . . . . ................................. 68
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ST62T08C/T09C ST62T10C/T20C/E20C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T08C,T09C,T10C,T20C and ST62E20C
devices are low cost members of the ST62xx 8-bit
HCMOS familyofmicrocontrollers, which is targeted at low to medium complexity applications. All
ST62xx devices are based on a building block approach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E20C is the erasable EPROM versionof
the ST62T08C,T09C,T10C and T20C device,
which may be used to emulate the
ST62T08C,T09C,T10C and T20C device, as well
as the respective ST6208C,09C,10C,20C ROM
devices.
OTP and EPROM devices are functionally identical. TheROM based versions offer the same func-
tionality selecting as ROM options the options defined in the programmable option bytes of the
OTP/EPROM versions.
OTP devices offer all the advantages of user programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit programmable prescaler,an 8-bit A/D Converter with up to
8 analog inputs and a Digital Watchdog timer,
making them well suited for a wide range of automotive, appliance and industrial applications.
Figure 1. Block Diagram
TEST
NMI
INTERRUPT
PROGRAM
1836 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
DIGITAL
8 BIT CORE
TEST/V
PP
3884 Bytes
(ST62T10C)
(ST62T20C, E20C)
8-BIT
A/D CONVERTER
PA0..PA3 (20mA Sink)
TIMER
V
DDVSS
OSCin OSCout RESET
WATCHDOG
:
MEMORY
PB0..PB7 / Ain (*)
1036 Bytes
(ST62T08C,T09C)
(*) Analog input availability depend on versions
4
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ST62T08C/T09C ST62T10C/T20C/E20C
1.2 PIN DESCRIPTIONS
VDDand VSS. Power is supplied to the MCU via
these two pins. VDDis the power connection and
VSSis the ground connection.
OSCin and OSCout. These pins are internally
connected tothe on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to restart the microcontroller. Internal pull-up is provided at this pin.
TEST/VPP. The TEST must be held at VSSfor nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.
NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. The user can select as option the availability of an on-chip pull-up at thispin.
TIMER. This is thetimer I/Opin. Ininput mode it is
connected to the prescaler and acts as external
timer clock input or as control gate input for the internal timer clock.Inoutputmode thetimer pin outputs the data bit when a time-out occurs. The user
can select as option the availability of an on-chip
pull-up at this pin.
PA0-PA3. These 4 lines are organized as one I/O
port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pull-
up resistors, open-drainor push-pull outputs. PA0PA3 can also sink 20mA for direct LED driving.
PB0-PB7. These 8 lines are organized as one I/O
port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drainor push-pull outputs. PB0PB3 can be used as analog input to the A/D converter on the ST62T10C, T20C and E20C, while
PB4-PB7 can be used as analog inputs fortheA/D
converter on the ST62T09C, T10C, T20C and
E20C.
Figure 2. ST62T08C,T09C, T10C, T20C and
E20C Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
DD
TIMER
OSCin
OSCout
NMI
V
PP
/TEST
RESET
Ain*/PB7
Ain*/PB6
Ain*/PB5
V
SS
PA0/20 mA Sink
PA1/20 mA Sink
PA2/20 mA Sink
PA3/20 mA Sink
PB0/Ain*
PB1/Ain*
PB2/Ain*
PB3/Ain*
PB4/Ain*
*Analog input availability depend on device
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ST62T08C/T09C ST62T10C/T20C/E20C
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operationin these threememory spacesis
described in the following paragraphs.
Briefly, Program space contains user program
code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for subroutine and interrupt service routine nesting.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS
ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA READ-ONLY
WINDOW
RAM / EEPROM
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
0-63
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY
MEMORY
DATA READ-ONLY
MEMORY
6
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ST62T08C/T09C ST62T10C/T20C/E20C
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate addressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register)Program Memory Protection.
The Program Memory in OTP or EPROM devices
can beprotectedagainst external readout of memory by selecting the READOUT PROTECTION option in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts witha protection set can therefore not be accepted.
Figure 4. Program Memory Map
(*) Reserved areas should be filled with 0FFh
0000h
0AFFh
0B00h
0B9Fh
NOT IMPLEMENTED
RESERVED
*
USER
PROGRAM MEMORY
(OTP)
1024 BYTES
0BA0h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED
*
RESERVED
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
0000h
07Fh
USER
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES
080h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED
*
RESERVED
*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
RESERVED
*
0000h
07FFh
0800h
087Fh
NOT IMPLEMENTED
RESERVED
*
USER
PROGRAM MEMORY
(OTP)
1824 BYTES
0880h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED
*
RESERVED
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
ST62T08C,T09C ST62T10C ST62T20C,E20C
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ST62T08C/T09C ST62T10C/T20C/E20C
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space comprises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently contains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants andlook-up tables are addressedby the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM
In ST6208C/09C/10C/20C devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. ST6208C/09C/10C/20C Data Memory
Space
RESERVED
000h
03Fh
DATA ROM WINDOW AREA
64 BYTES
040h
07Fh
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h
W REGISTER 083h
DATA RAM 60 BYTES
084h
0BFh
PORT A DATA REGISTE R 0C0h
PORT B DATA REGISTE R 0C1h
RESERVED 0C2h
RESERVED 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h
RESERVED 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h*
DATA ROM WINDOW REGISTER 0C9h*
RESERVED
0CAh
0CBh
PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh
RESERVED 0CEh
RESERVED 0CFh
A/D DATA REGISTER(except ST62T08C) 0D0h
A/D CONTROL REGISTER (except ST62T08C) 0D1h
TIMER PRESCALER REGISTER 0D2h
TIMER COUNTER REGISTER 0D3h
TIMER STATUS CONTROLREGISTER 0D4h
RESERVED
0D5h
0D6h
0D7h
WATCHDOG REGISTER 0D8h
RESERVED
0D9h
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
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ST62T08C/T09C ST62T10C/T20C/E20C
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
TheDataread-only memorywindowislocatedfrom
address 0040h toaddress 007Fh in Data space. It
allows direct reading of64consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program
memory can therefore be used to store either instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the program memorybywriting theappropriatecodeinthe
Data Window Register (DWR).
The DWR can beaddressedlike any RAM location
in the Data Space, it is however a write-only register and therefore cannot be accessedusing singlebit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register(asmost significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed inprogram memory is 00h. The DWRregister is not cleared on reset, therefore it must be
written to prior to the first access to the Data readonly memory window area.
Data Window Register (DWR)
Address: 0C9h — Write Only
Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0:
Data read-only memory
Window Register Bits.
These are the Data readonly memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution:
This register is undefined on reset. Neither read norsingle bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while executing an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writing to the DWR during the interruptserviceroutine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if aninterrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DATA ROM
WINDOW REGISTER
CONTENTS
DATA SPACE ADDRESS
40h-7Fh
IN INSTRUCTION
PROGRAM SPACE ADDRESS
765432 0
543210
543210
READ
1
67891011
01
VR01573C
12
1
0
DATA SPACE ADDRESS
:
:
59h
000
0
1
00
1
11
Example:
(DWR)
DWR=28h
1100000001
ROM
ADDRESS:A19h
11
13
0
1
9
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ST62T08C/T09C ST62T10C/T20C/E20C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
The two Option Bytes allow configurationcapability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING modeofthe programmer.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
EPROM Code Option Byte (MSB)
D15-D10. Reserved. Must be cleared
EXTCNTL.
External STOP MODE control.
. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one.. When
EXTCNTL is low, STOP mode is not availablewith
the watchdog active.
LVD.
LVDRESET enable.
When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
PROTECT.
Readout Protection.
This bit allowsthe
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
OSCIL.
Oscillator selection
. When this bit is low,
the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency.
When it is high, the oscillator must becontrolled by
an RC network, with only the resistor having to be
externally provided.
D5. Reserved. Must be cleared to zero.
D4. Reserved. Must be set to one.
NMI PULL.
NMI Pull-Up
. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
TIM PULL.
TIM Pull-Up
. This bit must be set high
to configure the TIMER pin with a pull-up resistor.
When it is low, no pull-up is provided.
WDACT. Thisbitcontrols the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
OSGEN.
Oscillator Safe Guard
. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byte is written during programming either by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
70
PROTECT
OSCIL - -
NMI
PULL
TIM
PULL
WDACT
OS-
GEN
15 8
------
EXTC-
NTL
LVD
10
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ST62T08C/T09C ST62T10C/T20C/E20C
PROGRAMMING MODES (Cont’d)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPPpin. The
programming flow of the
ST62T08C,T09C,T10C,T20C/E20C is described
in the User Manual of the EPROM Programming
Board.
Table 2.ST62T08C, T09C Program MemoryMap
Table 3. ST62T10C Program Memory Map
Table 4.ST62T20C,E20C Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from STMicroelectronics (ST62E2X-EPB or ST622X-KIT).
1.4.3 EPROM Erasing
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is exposed to light with a wave lengths shorterthan approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by anopaque label to
prevent unintentional erasure problems when testing the application in such an environment.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A.
The integrateddose (i.e.U.V. intensity x exposure
time) for erasure should be a minimum of 30Wsec/cm2. The erasure time with this dosage is ap-
Device Address Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
11
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ST62T08C/T09C ST62T10C/T20C/E20C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPUCoreof ST6devicesis independentofthe
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while thecore is linked to thededicatedon-chip peripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
TheST6FamilyCPUcorefeatures sixregistersand
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data
space asaRAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h(X) and 81h (Y). They can also be accessed with the direct, shortdirect, orbit direct addressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other register of the data space.
Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct registers as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE
FLAG
VALUES
2
CONTROLLER
FLAGS
ALU
A-DATA
B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTS TO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin
OSCout
ADDRESS
DECODER
256
12
Program Counter
and
6 LAYER STACK
0,01 TO 8MHz
VR01811
12
13/70
ST62T08C/T09C ST62T10C/T20C/E20C
CPU REGISTERS (Cont’d)
However, iftheprogram space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
The PC valueis incremented after reading the address of the current instruction.Toexecute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted backinto the PC.The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=Interrupt vector
- Reset PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation,another pair is used during Interrupt mode (CI, ZI), anda third pairis used
in the Non Maskable Interrupt mode (CNMI, ZNMI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI instruction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context
switching and thus retain their status.
The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also participates in the rotate left instruction.
The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.
Switching between the three sets of flags is performed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumulator, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subroutine. The stack will remain in its “deepest” position
if more than 6 nested calls orinterrupts are executed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET orRETI is executed.
In this case the next instruction will be executed.
Figure 7. ST6 CPU Programming Mode
l
SHORT
DIRECT
ADDRESSING
MODE
VREGISTER
W REGISTER
PROGRAMCOUNTER
SIX LEVELS
STACKREGISTER
CZNORMAL FLAGS
INTERRUPTFLAGS
NMI FLAGS
INDEX
REGISTER
VA000 4 23
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUM ULATO R
Y REG. POINTER
X REG. POINTER
CZ
CZ
13
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ST62T08C/T09C ST62T10C/T20C/E20C
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor
(R
NET
). Inaddition, a Low Frequency Auxiliary Oscillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automatically limits the internal clock frequency (f
INT
)asa
function ofVDD, inorder toguaranteecorrect operation. These functions are illustrated in Figure 9,
Figure 10, Figure 11 and Figure 12.
Figure 8 illustrates various possible oscillator configurations using anexternalcrystalor ceramic resonator, an external clock input, anexternal resistor
(R
NET
), or the lowest cost solution using only the
LFAO. CL1anCL2shouldhave acapacitanceinthe
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU clock frequency (f
INT
) is divided
by 12to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.
A machine cycle is the smallest unitof time needed
to executeanyoperation (forinstance,to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillatorconfigurationmay be specified byselectingtheappropriate option.WhentheCRYSTAL/
RESONATORoptionisselected,itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signalprovidedontheOSCinpin.WhentheRCNETWORK option is selected, the system clock isgenerated by an external resistor.
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatically started.
Figure 8. Oscillator Configurations
INTEGRATED CLOCK
CRYSTAL/RESONATOR option
OSG ENABLED option
OSC
in
OSC
out
C
L1n
C
L2
ST6xxx
CRYSTAL/RESONATORCLOCK
CRYSTAL/RESONATOR option
OSC
in
OSC
out
ST6xxx
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
NC
OSC
in
OSC
out
ST6xxx
NC
OSC
in
OSC
out
R
NET
ST6xxx
RC NETWORK
RC NETWORK option
NC
14
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ST62T08C/T09C ST62T10C/T20C/E20C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
the software instruction at f
LFAO
clock frequency.
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without anyexternal components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing
edge fromthemain oscillator,whatever thereason
(main oscillatordefective, no clock circuitry provided, main oscillator switched off...).
User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f
LFAO
frequency.TheA/D converter accuracy isdecreased, since the internal frequency isbelow 1MHz.
At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.
ADCR
Address: 0D1h — Read/Write
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register
. These bits are not used.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affordsdrastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide afixed frequency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct operation even ifthe power supply should drop.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result inan effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maximum internal clock frequency, f
INT
, is limited to
f
OSG
, which is supply voltage dependent. This re-
lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of
the main oscillator (see Figure 10).
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock frequency of the device is kept within the range the
particular device can stand (depending on VDD),
and below f
OSG
: the maximum authorised frequen-
cy with OSG enabled.
Note. The OSG should be usedwherever possible
as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency
to f
OSG
.
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and isnot accurate.
For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
70
ADCR7ADCR6ADCR5ADCR4ADCR3OSC
OFF
ADCR1ADCR
0
15
16/70
ST62T08C/T09C ST62T10C/T20C/E20C
CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle
Figure 10. OSG Emergency Oscillator Principle
(1)
VR001932
(3)
(2)
(4)
(1)
(2)
(3)
(4)
Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin
Noise from OSCin
Resulting Internal Frequency
Main
VR001933
Internal
Emergency
Oscillator
Frequency
Oscillator
16
17/70
ST62T08C/T09C ST62T10C/T20C/E20C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
Figure 12. Maximum Operating Frequency (f
MAX
) versus Supply Voltage (VDD)
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guaranteed at a frequency of at least f
OSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystalfrequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f
OSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at f
OSG.
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
:13
:12
:1
TIMER 1
Watchdog
POR
f
INT
Main Oscillator off
1
2.5 3.6 4 4.5 5 5.5 6
8
7
6
5
4
3
2
Maximum FREQUENCY (MHz)
SUPPLY VOLTAGE (V
DD
)
FUNCTIONALITY IS NOT
3
4
3
2
1
f
OSG
f
OSG
Min
GUARANTEED
IN THIS AREA
VR01807
17
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ST62T08C/T09C ST62T10C/T20C/E20C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDDhas
completed its risingphase andthat the oscillatoris
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization sequence is executed following expiry of the internal
delay period.
If RESET pinactivation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, theMCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon aninternal delay is initiated, inorder to
allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence
is executed immediately following the internal delay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from
0V.
As a consequence,the POR does not allow to supervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
INT LATCH CLEARED
NMI MASK SET
RESET
( IF PRESENT )
SELECT
NMI MODE FLAGS
IS RESETSTILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTION
LOAD PC
VA000427
18
19/70
ST62T08C/T09C ST62T10C/T20C/E20C
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst other things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start’s running and
sinking current on the supply.
As long as the supply voltage is below the reference value, there is a internal and static RESET
command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a powerup, power-down sequence.
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET
pin is tiedto low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
3.2.5 Application Notes
No external resistor is required between VDDand
the Reset pin, thanks to the built-inpull-up device.
Direct external connection of the pin RESET to
VDDmust be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired
structure).
RESET
RESET
VR02106A
time
V
Up
V
dn
V
DD
19
20/70
ST62T08C/T09C ST62T10C/T20C/E20C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (located in programROM starting at address 0FFEh). A
jump tothe beginning of theuser programmust be
coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The initialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If nopending interrupt
is presentat the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately followingtheRETIinstruction.If,however, a pending interrupt is present, it will be serviced.
Figure 15. Reset and Interrupt Processing
Figure 16. Reset Block Diagram
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2CYCLES
INITIALIZATION
ROUTINE
VA00181
V
DD
RESET
R
PU
R
ESD
1)
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
f
OSC
RESET
ON RESET
LVD RESET
VR02107A
AND. Wired
1) Resistive ESD protection. Value not guaranteed.
20
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ST62T08C/T09C ST62T10C/T20C/E20C
RESETS (Cont’d)
Table 5. Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register
Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
0DCh
0C0h to 0C1h
0C4h to 0C5h
0CCh to 0CDh
0C8h
0D4h
00h
f
INT=fOSC
; OSG disabled
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
TIMER disabled
X, Y, V, W, Register
Accumulator
Data RAM
Data ROM Window Register
A/D Result Register
080H TO 083H
0FFh
084h to 0BFh
0C9h
0D0h
Undefined As written if programmed
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Standby (When available)
21
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