SGS Thomson Microelectronics ST62T55BM6, ST62T55BM3, ST62T55BB6, ST62T55BB3, ST62T65BM6 Datasheet

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April 1998 1/74
R
ST62T55B
ST62T65B/E65B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
3.0 to 6.0V Supply Operating Range
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory: User selectable size
Data RAM: 128 bytes
Data EEPROM: 128 bytes(noneon ST62T55B)
User Programmable Options
21 I/O pins, fully programmable as:
– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input
8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
8-bit A/D Converter with 13 analog inputs
8-bit Synchronous Peripheral Interface (SPI)
On-chip Clock oscillatorcan be driven byQuartz Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port)
DEVICE SUMMARY
(See end of Datasheet for Ordering Information)
PDIP28
PSO28
CDIP28W
DEVICE
OTP
(Bytes)
EPROM
(Bytes)
EEPROM
ST62T55B 3884 - ­ST62T65B 3884 - 128 ST62E65B 3884 128
1
Rev. 2.4
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Table of Contents
74
2
ST62T55B / ST62T65B/E65B . . . . . . . . . . . . . . . . . . . . . . . ....1
1 GENERAL DESCRIPTION . . . . . . . ...............................................5
1.1 INTRODUCTION .........................................................5
1.2 PIN DESCRIPTIONS . . . . . . . . . . ............................................6
1.3 MEMORYMAP ..........................................................7
1.3.1 Introduction . . . . . . . . ................................................7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . ...........................8
1.3.3 Data Space . . . . . . . . ................................................9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . .......................................9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . .....................10
1.3.6 Data RAM/EEPROM Bank Register (DRBR)..............................11
1.3.7 EEPROM Description ...............................................12
1.4 PROGRAMMING MODES .................................................14
1.4.1 Option Byte . . . . . . . . ...............................................14
1.4.2 Program Memory . . . . ...............................................14
1.4.3 EEPROM Data Memory . . . . . . . . . . . . ..................................14
1.4.4 EPROMErasing....................................................15
2 CENTRAL PROCESSING UNIT .................................................16
2.1 INTRODUCTION ........................................................16
2.2 CPU REGISTERS . . . . . . . . ...............................................16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . ..............18
3.1 CLOCKSYSTEM........................................................18
3.1.1 Main Oscillator . . . . . . . . . . ...........................................18
3.2 RESETS...............................................................20
3.2.1 RESET Input ......................................................20
3.2.2 Power-on Reset . . . . . . . . . . . . . . . .....................................20
3.2.3 Watchdog Reset . . . . ...............................................21
3.2.4 Application Notes . . . . ...............................................21
3.2.5 MCU Initialization Sequence ..........................................21
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . .....................................23
3.3.1 Digital Watchdog Register (DWDR) . . . ..................................25
3.3.2 Application Notes . . . . ...............................................25
3.4 INTERRUPTS . . . . ......................................................27
3.4.1 Interrupt request . . . . . . . . . . . . . . . .....................................27
3.4.2 Interrupt Procedure . . . ..............................................28
3.4.3 Interrupt Option Register (IOR) . . . . ....................................29
3.4.4 Interrupt Sources . . . . ...............................................29
3.5 POWER SAVING MODES .................................................31
3.5.1 WAIT Mode . . . . . . . . ...............................................31
3.5.2 STOPMode.......................................................31
3.5.3 Exit from WAIT and STOP Modes . . . ...................................32
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Table of Contents
3
4 ON-CHIP PERIPHERALS . . . ...................................................33
4.1 I/OPORTS.............................................................33
4.1.1 Operating Modes . . . . ...............................................34
4.1.2 Safe I/O State Switching Sequence . . . ..................................35
4.2 TIMER ................................................................38
4.2.1 Timer Operating Modes . . . . . . . . . . . . ..................................39
4.2.2 Timer Interrupt . . .. . . . . . . ...........................................39
4.2.3 Application Notes . . . . ...............................................40
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................40
4.3 AUTO-RELOAD TIMER . . . . ...............................................41
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ................41
4.3.2 Timer Operating Modes . . . . . . . . . . . . ..................................41
4.3.3 AR Timer Registers . . . ..............................................45
4.4 A/D CONVERTER (ADC) . . . ..............................................47
4.4.1 Application Notes . . . . ...............................................47
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . ........................49
4.5.1 SPI Registers . . . ...................................................50
4.6 SPITIMINGDIAGRAMS..................................................52
5SOFTWARE ................................................................54
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . .....................................54
5.2 ADDRESSING MODES . . . . ...............................................54
5.3 INSTRUCTION SET. . . ...................................................55
6 ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . ..................................60
6.1 ABSOLUTE MAXIMUM RATINGS. ..........................................60
6.2 RECOMMENDED OPERATING CONDITIONS. . . ..............................61
6.3 DC ELECTRICAL CHARACTERISTICS ......................................62
6.4 AC ELECTRICAL CHARACTERISTICS ......................................63
6.5 A/D CONVERTER CHARACTERISTICS. . . ...................................63
6.6 TIMER CHARACTERISTICS . . . ............................................64
6.7 SPI CHARACTERISTICS . . . ..............................................64
6.8 ARTIMER ELECTRICAL CHARACTERISTICS. . . ..............................64
7 GENERAL INFORMATION . . . . . . . . . . ...........................................65
7.1 PACKAGE MECHANICAL DATA. . . . ........................................65
7.2 .ORDERING INFORMATION. . . ............................................66
ST62P55B / ST62P65B . . .............................67
1 GENERAL DESCRIPTION . . . . . . . ..............................................68
1.1 INTRODUCTION ........................................................68
1.2 ORDERING INFORMATION ...............................................68
1.2.1 Transfer of Customer Code . ..........................................68
1.2.2 Listing Generation and Verification . . . . . . . . . . ...........................68
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Table of Contents
74
4
ST6255B / ST6265B . . . . . . ...........................71
1 GENERAL DESCRIPTION . . . . . . . ..............................................72
1.1 INTRODUCTION ........................................................72
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . ........................72
1.3 ORDERING INFORMATION ...............................................74
1.3.1 Transfer of Customer Code . ..........................................74
1.3.2 Listing Generation and Verification . . . . . . . . . . ...........................74
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ST62T55B ST62T65B/E65B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T55B, ST62T65B and ST62E65B devic­es are low cost members of the ST62xx 8-bit HC­MOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block ap­proach: a common core is surrounded by a number of on-chip peripherals.
The ST62E65B is the erasable EPROM version of the ST62T65B device, which may be used to em­ulate the ST62T55B and ST62T65B device, as well as the respective ST6255B and ST6265B ROM devices.
OTP and EPROM devices are functionally identi­cal. The ROM based versions offer the same func­tionality selecting as ROM options the options de-
fined in the programmable option byte of theOTP/ EPROM versions.
OTP devices offer all the advantages of user pro­grammability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.
These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit program­mable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability (except ST62T55B), a serial port communication interface, an 8-bit A/D Converter with 13 analog inputs and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.
Figure 1.Block Diagram
j
TEST
NMI INTERRUPT
PROGRAM
PC
STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6
POWER SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
PORT A
PORT B
TIMER
DIGITAL
8 BIT CORE
TEST/V
PP
8-BIT
A/D CONVERTER
PA0..PA7 / Ain
PB0..PB5 / 20 mA Sink
V
DDVSS
OSCin OSCout RESET
WATCHDOG
MEMORY
PB6 / ARTimin / 20 mA Sink
PORT C
PC2 / Sin / Ain PC3 / Sout / Ain
SPI (SERIAL
PERIPHERAL
INTERFACE)
AUTORELOAD
TIMER
PC4 / Sck / Ain
PB7 / ARTimout / 20 mA Sink
128 Bytes
3884 bytes OTP
3884 bytes EPROM
(ST62T55B, T65B)
(ST62E65B)
DATA EEPROM
128 Bytes
PC0 / Ain PC1 / Tim1 / Ain
(ST62T65B/E65B)
5
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ST62T55B ST62T65B/E65B
1.2 PIN DESCRIPTIONS VDDand VSS. Power is supplied to the MCU via
these two pins. VDDis the power connection and VSSis the ground connection.
OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit.A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.
RESET. The active-low RESET pin is used to re­start the microcontroller.
TEST/VPP.
The TEST must be held at VSSfor nor­mal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/ OTP programming Mode is entered.
NMI.
The NMI pin provides the capability for asyn­chronous interruption, by applying an external non maskable interrupt to the MCU.The NMI input is falling edge sensitive.It is provided with an on-chip pullup resistor and Schmitt trigger characteristics.
PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured under soft­ware control as inputs with or without internal pull­up resistors, interrupt generating inputs with pull­up resistors, open-drain or push-pull outputs, ana­log inputs for the A/D converter.
PB0-PB5. These 6 lines are organized as one I/O port (B). Each line may be configured under soft­ware control as inputs with or without internal pull­up resistors, interrupt generating inputs with pull­up resistors, open-drain or push-pull outputs. PB0-PB5 can also sink 20mA for direct LED driving.
PB6/ARTIMin, PB7/ARTIMout
. These pins are ei­ther Port B I/O bits or the Input and Output pins of the AR TIMER. To be used as timer input function
PB6 has to be programmed as input with or with­out pull-up. A dedicated bit in the AR TIMER Mode Control Register sets PB7 as timer output function. PB6-PB7 can also sink 20mA for direct LED driv­ing.
PC0-PC4. These 5 lines are organized as one I/O port (C). Each line may be configured under soft­ware control as input with or without internal pull­up resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, open­drain or push-pull output. PC1 can also be used as Timer I/O bit while PC2-PC4 can also be used as respectively Data in, Data out and Clock I/O pins for the on-chip SPI to carry the synchronous serial I/O signals.
Figure 2. ST62T55B, T65B, E65B Pin
Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13
14
15
16
17
18
19
20
PB0 PB1
V
PP
/TEST
PB2 PB3
Ain/ PA0
V
DD
PB4 PB5
ARTIMin/PB6
PC0/Ain PC1/TIM1/Ain
PC2/Sin/Ain PC3/Sout/Ain PC4/Sck/Ain
PA7/Ain PA6/Ain PA5/Ain PA4/Ain
PA3/Ain
28 27 26 25 24 23 22 21
ARTIMout/PB7
V
SS
Ain/PA1 Ain/PA2
NMI RESET OSCout OSCin
6
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ST62T55B ST62T65B/E65B
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.
Briefly, Program space contains user program code in OTP and user vectors; Data space con­tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub­routine and interrupt service routine nesting.
Figure 3.Memory Addressing Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS
ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGISTER Y REGISTER V REGISTER
W REGISTER
DATA READ-ONLY
WINDOW
RAM / EEPROM BANKING AREA
000h
03Fh 040h
07Fh 080h 081h 082h 083h 084h
0C0h
0FFh
0-63
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY
MEMORY
DATA READ-ONLY
MEMORY
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be executed, the data required for immediate ad­dressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register).
1.3.2.1 Program Memory Protection
The Program Memory in OTP or EPROM devices can be protected against external readout of mem­ory by selecting the READOUT PROTECTION op­tion in the option byte.
In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.
Note: Once the Readout Protection is activated, it is no longer possible, even for SGS-THOMSON, to gain access to the OTP contents. Returned parts with a protection set can therefore notbe ac­cepted.
Figure 4.ST62T55B/T65B/E65B Program
Memory Map
0000h
RESERVED
*
USER
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES
0F9Fh 0FA0h
0FEFh
0FF0h 0FF7h
0FF8h 0FFBh 0FFCh 0FFDh 0FFEh
0FFFh
RESERVED
*
RESERVED
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
0080h
007Fh
8
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary for processing the user program. This space com­prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/ EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently con­tains the program code to be executed, as well as the constants and look-up tables required by the application.
The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM/EEPROM
In ST62T55B, ST62T65B and ST62E65B devices, the data space includes 60 bytes of RAM, the ac­cumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port regis­ters, the peripheral data and control registers, the interrupt option register and the Data ROM Win­dow register (DRW register).
Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located be­tween addresses 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as thecurrent program counter contents.
Table 1.Additional RAM/EEPROM Banks
Table 2. ST62T55B, ST62T65B and ST62E65B Data Memory Space
Device RAM EEPROM
ST62T55BB 1 x 64 bytes ­ST62T65B/E65B 1 x 64 bytes 2 x 64 bytes
RAM and EEPROM
000h 03Fh
DATA ROM WINDOW AREA
040h
07Fh X REGISTER 080h Y REGISTER 081h V REGISTER 082h
W REGISTER 083h
DATA RAM 60 BYTES
084h
0BFh PORT A DATA REGISTER 0C0h PORT B DATA REGISTER 0C1h PORT C DATA REGISTER 0C2h
RESERVED 0C3h PORT A DIRECTION REGISTER 0C4h PORT B DIRECTION REGISTER 0C5h
PORT C DIRECTION REGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h* DATA ROM WINDOW REGISTER 0C9h*
RESERVED
0CAh
0CBh PORT A OPTION REGISTER 0CCh PORT B OPTION REGISTER 0CDh PORT C OPTION REGISTER 0CEh
RESERVED 0CFh
A/D DATA REGISTER 0D0h
A/D CONTROL REGISTER 0D1h
TIMER PRESCALERREGISTER 0D2h
TIMER COUNTERREGISTER 0D3h
TIMER STATUS CONTROL REGISTER 0D4h
AR TIMER MODE CONTROL REGISTER 0D5h AR TIMER STATUS/CONTROL REGISTER1 0D6h AR TIMER STATUS/CONTROL REGISTER2 0D7h
WATCHDOG REGISTER 0D8h
AR TIMER RELOAD/CAPTURE REGISTER 0D9h
AR TIMER COMPARE REGISTER 0DAh
AR TIMER LOAD REGISTER 0DBh
OSCILLATOR CONTROL REGISTER 0DCh*
MISCELLANEOUS 0DDh
RESERVED
0DEh 0DFh
SPI DATA REGISTER 0E0h
SPI DIVIDER REGISTER 0E1h
SPI MODEREGISTER 0E2h
RESERVED
0E3h 0E7h
DATA RAM/EEPROMREGISTER 0E8h*
RESERVED 0E9h
EEPROM CONTROL REGISTER 0EAh
RESERVED
0EBh 0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d)
1.3.5 Data Window Register (DWR)
The Dataread-only memory window islocated from address 0040h to address 007Fh in Data space. It allows direct reading of64 consecutive byteslocat­ed anywhere in program memory, between ad­dress 0000h and 0FFFh (top memory address de­pends on the specific device). All the program memory can therefore be used to store either in­structions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the pro­grammemory by writing theappropriate code in the Data Window Register (DWR).
The DWR can be addressed like any RAM location in the Data Space, it is however a write-only regis­ter and therefore cannot be accessed using single­bit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significantbits), as illustrat­ed in5 below. For instance, when addressing loca­tion 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written topri­or to the first access to the Data read-only memory window area.
Data Window Register (DWR)
Address: 0C9h Write Only
Bits 6, 7 = Not used. Bit 5-0 = DWR5-DWR0:
Data read-only memory
Window Register Bits.
These are the Data read­only memory Window bits that correspond to the upper bits of the data read-only memory space.
Caution:
This register is undefined on reset. Nei­ther read nor single bit instructions may be used to address this register.
Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while exe­cuting an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writ­ing to theDWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written firstso that, if an in­terrupt occurs between the two instructions, the DWR is not affected.
Figure 5.Data read-only memory Window Memory Addressing
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DATA ROM
WINDOWREGISTER
CONTENTS
DATA SPACEADDRESS
40h-7Fh
IN INSTRUCTION
PROGRAM SPACE ADDRESS
765432 0
543210
543210
READ
1
67891011
01
VR01573C
12
1
0
DATA SPACEADDRESS
:
:
59h
000
0
1
00
1
11
Example:
(DWR)
DWR=28h
1100000001
ROM
ADDRESS:A19h
11
13
01
10
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d)
1.3.6 Data RAM/EEPROM Bank Register (DRBR)
Address: E8h Write only
Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2. Bit 3-2 - Reserved. These bits are not used. Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1. Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0. The selection ofthe bank ismade by programming
the Data RAM Bank Switch register (DRBR regis­ter) located at address E8h of the Data Space ac­cording to Table 1. No more than one bank should be set at a time.
The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space. The number of banks has to be load­ed in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address).
This register is not cleared during the MCU initiali­zation, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa­tion. The DRBR register is not modified when an interrupt or a subroutine occurs.
Notes : Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in­terrupt service routine, as the service routine can­not save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other­wise two or more pages are enabled in parallel, producing errors.
Table 3.Data RAM Bank Register Set-up
70
---
DRBR
4
--
DRBR1DRBR
0
DRBR ST62T55B ST62T65B/E65B
00 None None 01 Not Available EEPROM Page 0 02 Not Available EEPROM Page 1 08 Not Available Not Available
10h RAM Page 2 RAM Page 2
other Reserved Reserved
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d)
1.3.7 EEPROM Description
EEPROM memory is located in 64-byte pages in data space. This memory may beused by the user program for non-volatile data storage.
Data space from 00h to3Fh ispaged as described in Table 4. EEPROM locations are accessed di­rectly by addressing these paged sections of data space.
The EEPROM does not require dedicated instruc­tions forread orwriteaccess.Once selected viathe Data RAM Bank Register, the active EEPROM page is controlled bythe EEPROM Control Regis­ter (EECTL), which is described below.
BitE20FF ofthe EECTLregister mustbe reset prior to any write or read access to the EEPROM. If no bank has beenselected, orif E2OFF is set, any ac­cess is meaningless.
Programming must be enabled by setting the E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP­ROM location is read just like any other data loca­tion, also in terms of access time.
Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with conse­quent speed and power consumption advantages, the latter being particularly important in battery powered circuits).
General Notes: Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer mem­ory between data RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”) EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set.
Care is required when dealing with theEECTL reg­ister, as some bits are write only. For this reason, the EECTL contents must not be altered while ex­ecuting an interrupt service routine.
If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt oc­curs between the two instructions, the EECTL will not be affected.
Table 4.. Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace addresses. Banks 0 and 1.
Byte 01234567 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
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ST62T55B ST62T65B/E65B
MEMORY MAP(Cont’d) Additional Notes on Parallel Mode:
If the user wishes to perform parallel program­ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad­dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting E2PAR2 without programming the EEPROM. Af­ter the ROW address is latched, the MCU can only “see” the selected EEPROM row and any attempt to write or read other rows will produce errors.
The EEPROM should not be read while E2PAR2 is set.
As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM regis­ters corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified si­multaneously; the remaining bytes in the row will be unaffected.
Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel pro­gramming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and theE2PAR1 bit will be un­affected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low.The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set.
EEPROM Control Register (EECTL)
Address: EAh — Read/Write Reset status: 00h
Bit 7 =D7:
Unused.
Bit6 =E2OFF:
Stand-by Enable Bit.
WRITE ONLY. Ifthisbitis settheEEPROMisdisabled (any access willbe meaningless) and the power consumption of the EEPROM is reduced to its lowest value.
Bit 5-4 =D5-D4:
Reserved.
MUST be kept reset.
Bit 3 =
E2PAR1
:
Parallel Start Bit.
WRITE ONLY. OnceinParallel Mode,as soonasthe usersoftware sets the E2PAR1 bit, parallel writing of the 8 adja­cent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the un­defined bytes being unaffected by the parallel pro­gramming cycle;this is explained ingreater detailin the Additional Notes on Parallel Mode overleaf.
Bit 2 = E2PAR2:
Parallel Mode En. Bit.
WRITE ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultane­ously. These 8 adjacent bytes are considered asa row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are thechanging bits, as illustrated in 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged.
Bit 1 = E2BUSY:
EEPROM Busy Bit.
READ ON­LY. This bit is automatically set by the EEPROM control logic when the EEPROM is in program­ming mode. The user program should test itbefore any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed.
Bit 0 = E2ENA:
EEPROM Enable Bit.
WRITE ON­LY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEP­ROM register. Any attempt to write to the EEP­ROM when E2ENA is low is meaningless and will not trigger a write cycle.
70
D7
E2O
FF
D5 D4
E2PAR1E2PAR2E2BUSYE2E
NA
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1.4 PROGRAMMING MODES
1.4.1 Option Byte
The Option Byte allows configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated.
It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the pro­grammer.
The option byte is located in a non-user map. No address has to be specified.
EPROM Code Option Byte
PROTECT. This bit allows the protection of the
software contents against piracy. When the bit PROTECT is set high, readout of the OTP con­tents is prevented by hardware. No programming equipment is able to gain access to the user pro­gram. When this bit is low, the user program can be read.
EXTCNTL
. This bit selects the External STOP Mode capability. When EXTCNTL is high, pin NMI controls if the STOP mode can be accessed when the watchdog is active. In addition, PB0 is forced as open drain output. When EXTCNTL is low, the STOP instruction is processed as a WAIT as soon as the watchdog is active.
PB2-3 PULL
. When set this bit removes pull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.
PB0-1 PULL
. When set this bit removes pull-up at reset on PB0-PB1 pins. When cleared PB0-PB1 pins have an internal pull-up resistor at reset.
WDACT
.This bit controls the watchdog activation. When it is high, hardware activation is selected. The software activation is selected when WDACT is low.
DELAY. This bit enables the selection of the delay internally generated after pin RESET is released. When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of32768 cycles when DELAY is high.
OSCIL. When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency. When it is high, the oscil­lator must be controlled by an RC network, with only the resistor having to be externally provided.
D0. Reserved. Must be cleared to zero. The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or automatically (stand-alone mode)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPPpin. The programming flow of the ST62T65B/E65B is de­scribed in the User Manual of the EPROM Pro­gramming Board.
The MCUs can be programmed with the ST62E6xB EPROM programming tools available from SGS-THOMSON.
Table 5. ST6255B, ST62T65B/E65B
Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from SGS-THOMSON (ST62E6X-EPB or ST626X-KIT).
1.4.3 EEPROM Data Memory
EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEP­ROM data memory can be performed either through the application software, or throughan ex­ternal programmer. Any SGS-THOMSON tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem­ory.
70
PRO­TECT
EXTC-
NTL
PB2-3
PULL
PB0-1
PULL
WDACT DELAY OSCIL -
Device Address Description
0000h-007Fh 0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
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PROGRAMMING MODES(Cont’d)
1.4.4 EPROM Erasing
The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is ex­posed to light witha wave lengths shorter than ap­proximately 4000Å. It should be noted that sun­lights and some types of fluorescent lamps have wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test­ing the application in such an environment.
The recommended erasure procedure of the MCUs EPROM is the exposure to short wave ul­traviolet light which have a wave-length 2537A. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15W­sec/cm2. The erasure time with this dosage is ap­proximately 15 to 20 minutes using an ultraviolet lamp with 12000µW/cm2power rating. The ST62E65B should be placed within 2.5cm (1Inch) of the lamp tubes during erasure.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPUCoreofST6 devicesisindependent ofthe I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Pe­ripherals via internal address, data, and control buses. In-core communication is arranged as shown in6; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.
2.2 CPU REGISTERS
TheST6Family CPUcore featuressixregistersand three pairs of flags available to the programmer. These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic cal­culations, logical operations, and data manipula­tions. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.
Indirect Registers (X, Y).These two indirect reg­isters are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be ad­dressed in the dataspace as RAM locations at ad­dresses 80h (X) and 81h (Y). They can also be ac­cessed with the direct, short direct, or bit direct ad­dressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other reg­ister of the data space.
Short Direct Registers (V, W).These two regis­ters are used to save a byte in short direct ad­dressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the di­rect and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct regis­ters as any other register of the data space.
Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an oper­and, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.
Figure 6.ST6 Core Block Diagram
PROGRAM
RESET
OPCODE
FLAG
VALUES
2
CONTROLLER
FLAGS
ALU
A-DATA
B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTS TO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin
OSCout
ADDRESS
DECODER
256
12
Program Counter
and
6 LAYER STACK
0,01 TO 8MHz
VR01811
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CPU REGISTERS (Cont’d)
However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.
The PC value is incremented after reading the ad­dress of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=Interrupt vector
- Reset PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used dur­ing Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZN­MI).
The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI in­struction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main rou­tine). The flags are not cleared during context switching and thus retain their status.
The Carry flag is set when a carry or a borrow oc­curs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also partici­pates in the rotate left instruction.
The Zeroflag is set if the result of the last arithme­tic or logical operation was equal to zero; other­wise it is cleared.
Switching between the three sets of flags is per­formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is
automatically selected after the reset of the MCU, the ST6 core uses at first the NMIflags.
Stack. The ST6 CPU includes a true LIFO hard­ware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or inter­rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumula­tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subrou­tine. The stack will remain in its “deepest” position if more than 6nested callsor interrupts are execut­ed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.
Figure 7.ST6 CPU Programming Mode
l
SHORT
DIRECT
ADDRESSING
MODE
V REGISTER
WREGISTER
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
CZNORMAL FLAGS
INTERRUPTFLAGS
NMI FLAGS
INDEX
REGISTER
VA000423
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUMULATOR
YREG.POINTER
XREG.POINTER
CZ
CZ
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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita­ble ceramic resonator, or with an external resistor (R
NET
).
8 illustrates various possible oscillator configura­tionsusing anexternal crystalorceramicresonator, an external clock input, anexternal resistor (R
NET
). CL1an CL2should have a capacitance in the range 12to22pFforanoscillator frequency in the4-8 MHz range.
Aprogrammable dividerisprovidedinordertoadjust the internalclock of the MCUto thebest power con­sumption and performance trade-off.
The internal MCU clock frequency (f
INT
) drives di­rectly the AR TIMER while it is divided by 12 to drive the TIMER, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in9.
With an 8MHz oscillator frequency, the fastest ma­chine cycle is therefore 1.625µs.
A machine cycleis the smallest unit oftime needed toexecuteany operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration maybe specifiedby se­lectingtheappropriate option.WhentheCRYSTAL/ RESONATORoptionisselected,itmustbeusedwith a quartz crystal, aceramic resonator or an external signalprovidedontheOSCinpin.WhentheRCNET­WORK option is selected, the system clock is gen­erated by an external resistor.
Figure 8.Oscillator Configurations
OSC
in
OSC
out
C
L1n
C
L2
ST6xxx
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
OSC
in
OSC
out
ST6xxx
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
NC
OSC
in
OSC
out
R
NET
ST6xxx
RC NETWORK
RC NETWORK option
NC
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CLOCK SYSTEM(Cont’d) Oscillator Control Registers
Address: DCh Write only
Bit 7-4. These bits are notused. Bit 3. Reserved. Cleared at Reset. THIS BIT
MUST BE SET TO 1 BY USER PROGRAM to achieve lowest power consumption.
Bit 2. Reserved. Must be kept low. RS1-RS0. These bits select the division ratio of
the Oscillator Divider in orderto generate the inter­nal frequency. The following selctions are availa­ble:
Note: Care is required when handling the OSCR register as some bits are write only. For this rea­son, it is not allowed to change the OSCR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to OSCR it must write also to the image register. The image register must be written first, so if an inter­rupt occurs between the two instructions the OSCR is not affected.
Figure 9.Clock Circuit Block Diagram
70
----
OSCR3OSCR
2
RS1 RS0
RS1 RS0 Division Ratio
0 0 1 1
0 1 0 1
1 2 4 4
MAIN
OSCILLATOR
Core
:13
:12
:1
Timer
Watchdog
POR
f
INT
ADC
AR Timer
SPI
OSCILLATOR
DIVIDER
RS0, RS1
OSCin
OSCout
f
OSC
f
OSC
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3.2 RESETS
The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDDhas completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.
If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are con­figured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization se­quence is executed following expiry of the internal delay period.
If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of theRESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.
3.2.2 Power-on Reset
The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this se­quence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises toa sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence isexecuted immediate­ly following the internal delay.
The internal delay isgenerated by anon-chip coun­ter.The internal reset line is released 2048 internal clock cycles after release of the external reset.
Notes:
To ensure correct start-up, the user should take care that the reset signal is not released before the VDDlevel is sufficient to allow MCU operation at the chosen frequency (see Recommended Oper­ating Conditions).
A proper reset signal for a slow rising VDDsupply can generally be provided by an external RC net­work connected to theRESET pin.
Figure 10.. Reset and Interrupt Processing
INT LATCH CLEARED
NMI MASK SET
RESET
( IF PRESENT )
SELECT
NMI MODE FLAGS
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTION
LOAD PC
VA000427
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ST62T55B ST62T65B/E65B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst oth­er things, resets the watchdog counter.
The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.
3.2.4 Application Notes
No external resistor is required between VDDand the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it triggers MCU initialization on detecting the rising edge of VDD. The typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which VDDrises.
The POR circuit is
NOT
designed to supervise
static, or slowly rising or falling VDD.
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is loaded with the address of the ResetVector (locat­ed in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the In­terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The in­itialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, how­ever, a pending interrupt is present, it will be serv­iced.
Figure 11.. Reset and Interrupt Processing
Figure 12.. Reset Block Diagram
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
V
DD
RESET
300k
2.8k
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6 INTERNAL RESET
f
OSC
RESET
ON RESET
VA0200B
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RESETS (Cont’d) Table 6.Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control
AR TIMER Mode Control Register AR TIMER Status/Control 1 Register AR TIMER Status/Control 2 Register AR TIMER Compare Register AR TIMER Load Register
Miscellaneous Register SPI Registers
0DCh 0EAh 0C0h to 0C2h 0C4h to 0C6h 0CCh to 0CEh 0C8h 0D4h
0D5h 0D6h 0D7h 0DAh 0DBh
0DDh 0E0h to 0E2h
00h 00h 00h 00h 00h 00h 00h
00h 02h 00h 00h 00h
00h 00h
f
INT=fOSC
; user must set bit3 to 1 EEPROM disabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled
AR TIMER stopped
SPI Output not connected to PC3 SPI disabled
X, Y, V, W, Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A/D Result Register AR TIMER Load Register AR TIMER Reload/Capture Register
080H TO 083H 0FFh 084h to 0BFh 0E8h 0C9h 00h to 03Fh 0D0h 0DBh 0D9h
Undefined
As written if programmed
TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A/D Control Register
0D3h 0D2h 0D8h 0D1h
FFh 7Fh
FEh
40h
Max count loaded
A/D in Standby
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ST62T55B ST62T65B/E65B
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usual­ly caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be re­loaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In or­der to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind.
Watchdog behaviour is governed by two options, known as “WATCHDOG ACTIVATION” (i.e. HARDWARE or SOFTWARE) and “EXTERNAL STOP MODE CONTROL” (seeTable 7).
In the SOFTWARE option, the Watchdog is disa­bled until bit C ofthe DWDR register has been set.
When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is per­manently enabled. Since theoscillatorwill run con­tinuously, low power mode is not available. The STOP instruction is interpreted as a WAIT instruc­tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov­erned by a secondary function associated with the NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP in­struction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU en­ters STOP mode.
When the MCU exits STOP mode (i.e. when an in­terrupt is generated), the Watchdog resumes its activity.
Table 7.Recommended Option Choices
Functions Required Recommended Options
Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
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