Datasheet ST25W16, ST25C16, ST24W16, ST24C16 Datasheet (SGS Thomson Microelectronics)

with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DAT A RE TENTION

SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONT ROL VERSIONS:

ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8

BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREME NTING
ENHANCE D ESD/LATCH UP

PERFORMANCES

ST24C16, ST25C16

ST24W16, ST25W16

16 Kbit Serial I2C Bus EEPROM

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

8

1

SO8 (M)

150mil Width

DESCRIPTION

This specification covers a range of 16 Kbit I

2

C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver­sion and "W" for hardware Write Control version.

The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-

T ab le 1. Signal Names

PRE Write Protect Enable
PB0, PB1 Protect Block Select
SDA Serial Data Address Input/Output
SCL Serial Clock

MODE
WC Write Control (W version)

V

CC

V

SS

Multybyte/Page Write Mode
(C version)

Supply Voltage
Ground

V

CC

2

PB0-PB1 SDA

PRE

SCL

MODE/WC*

Note:

WC signal is only available for ST24/25W16 products.

ST24x16
ST25x16

V

SS

AI00866B

February 1999 1/17

ST24/25C16, ST24/25W16

Figure 2A. DIP Pin Connections

ST24x16
ST25x16

1

PRE V

2
3

PB1

4

SS

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature –40 to 125

8
7
6
5

AI00867B

CC

MODE/WCPB0
SCL
SDAV

(1)

Figure 2B. SO8 Pin Connections

ST24x16
ST25x16

PRE V

1
2

PB1

SS

3
4

8
7
6
5

AI00500B

CC

MODE/WCPB0
SCL
SDAV

C

°

T

STG

T

LEAD

V

IO

V

CC

V

ESD

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refe r also to t he STM icro ele ctr oni cs SURE Pro gr am and
other relevant quality documents .

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) carry a built-in 4 bit, unique device identification
ance of one million erase/write cycles with a data

retention of 40 years. The ST25x16 operates wit h
a power supply value as low as 2.5V. Both Plastic
Dual-in-Line and Plastic Small Outline packages
are available.

The memories are compatible with the I
ard, two wire serial interface which uses a bi-direc­tional data bus and serial clock. The memories

Storage Temperature –65 to 150
Lead Temperature, Soldering (SO8)

Input or Output Voltages –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

(PSDIP8)

(3)

code (1010) corresponding to the I
tion. The memories behave as slave devices in the

2

C protocol with all memory operations synchro-

I

40 sec
10 sec

(2)

215
260

4000 V

500 V

2

C bus defini-

nized by the serial clock . Read and write operations
are initiated by a START condition generated by the
bus master. The START condition is followed by a

2

C stand-

stream of 4 bits (identification code 1010), 3 block
select bits, plus one read/write bit and terminated
by an acknowledge bit. When writing data to the

C

°

C

°

2/17

ST24/25C16, ST24/25W16

T ab le 3. Device Select Code

Device Code Memory MSB Addresses RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 A10 A9 A8 R

Note:

The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit MODE pin Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

Random Address Read

Sequential Read ’1’ X 1 to 2048 As CURRENT or RANDOM Mode
Byte Write ’0’ X 1 START, Device Select, R
Multibyte Write ’0’ V
Page Write ’0’ V

Note:

X = V

or VIL.

IH

memory it responds to the 8 bits received by as­serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow­ledges the receipt of the data bytes in the sam e
way. Data transfers are terminated with a STOP
condition.

Data in the 4 upper blocks of t he memory may be
write protected. The protected area is programma­ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven

’0’
’1’ reSTART, Device Select, R

X1

IH

IL

8 START, Device Select, RW = ’0 ’

16 START, Device Select, RW = ’0’

Power On Reset: V

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any c ommand.
In the same way, when V
operating voltage to below the POR threshold
value, all operations are disabled and the dev ice
will not respond to any command. A stable V
must be applied before applying any logic signal.

START, Device Select, R

lock out write pr otec t. In

CC

CC

W = ’1’
W = ’0’, Address,

W = ’1’

W = ’0’

drops down from the

High.

W

CC

CC

3/17

ST24/25C16, ST24/25W16

SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input signal is used

to synchronise all data in and out of the memory . A
resistor can be connected from the SCL line to V

CC

to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA signal is bi-directional

and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 3).

CC

Protected Block Select (PB0, PB1). PB0 and PB1
input signals select the block in the upper part of
the memory where write protection starts. These
inputs have a CMOS compatible input level.

Protect Enable (PRE). The PRE input signal, in
addition to the status of the Block Address Pointer
bit (b2, location 7FFh as in Figure 7), sets the PRE

Mode (MODE). The MODE input is available on pin
7 (see also
cally. It must be at V
mode, V
Write mode. When unconnected, the MODE input
is internally read as V

Write Control (

feature is offered only for ST24W16 and ST25W16
versions on pin 7. This feature is usefull to protect
the contents of the memory from any erroneous
erase/write cycle. The Write Control signal is used
to enable (
internal write protection. When unconnected, the
WC input is internally read as VIL. The devices with
this Write Control feature no longer supports the
Multibyte Write mode of operation, however all
other write modes are fully supported.

Refer to the AN404 Application Note for more de­tailed information about Write Control feature.

write protection active.

Figure 3. Maximum RL Value versus Bus Capacitance (C

WC feature) and may be driven dynami-

or VIH for the Byte Write

for Multibyte Write mode or VIL for Page

IH

IL

(Multibyte Write mode).

IH

WC). An hardware Write Control

WC at VIH) or disable (WC at VIL) the

) for an I2C Bus

BUS

20

V

CC

16

R

12

max (kΩ)

L

R

8

4

0

VCC = 5V

100 200 300 400

C

(pF)

BUS

MASTER

SDA

SCL

R

BUS

L

C

BUS

AI01100

L

C

4/17

ST24/25C16, ST24/25W16

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance (ST24/25W16) VIN ≤ 0.3 V
WC Input Impedance (ST24/25W16) VIN ≥ 0.7 V
Low-pass filter input time constant

(SDA and SCL)

CC

CC

520k

500 k

100 ns

T ab le 6. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

Input Leakage Current 0V ≤ VIN ≤ V

Output Leakage Current

Supply Current (ST24 series)

Supply Current (ST25 series) V

0V ≤ V

V

= 5V, fC = 100kHz

CC

(Rise/Fall time < 10ns)

= 2.5V, fC = 100kHz 1 mA

CC

≤ VCC

OUT

SDA in Hi-Z

CC

2

±

2

±

2mA

Ω
Ω

A

µ

A

µ

I

CC1

I

CC2

V

V

V

V

V

OL

V

= VSS or VCC,

IN

= 5V

V

Supply Current (Standby)
(ST24 series)

V

Supply Current (Standby)
(ST25 series)

V

IL

IH

IL

IH

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage

(PB0 - PB1, PRE, MODE,

WC)

Input High Voltage
(PB0 - PB1, PRE, MODE,

WC)

CC

V

= VSS or VCC,

IN

= 5V, fC = 100kHz

CC

V

= VSS or VCC,

IN

= 2.5V

V

CC

V

= VSS or VCC,

IN

= 2.5V, fC = 100kHz

CC

CC

–0.3 0.5 V

V

– 0.5 VCC + 1 V

CC

100

300

5

50

CC

µ

µ

µ

µ

VCC + 1 V

A

A

A

A

V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

OL

5/17

ST24/25C16, ST24/25W16

T ab le 7. AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL1

(1)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(2)

t

CLQV

t

CLQX

f

C

(3)

t

W

Notes:

1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)

the maximum programming time is doubled to 20ms.

t
t
t
t

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

R

F

R

F

Clock Rise Time 1
Clock Fall Time 300 ns
Input Rise Time 1
Input Fall Time 300 ns
Clock High to Input Transition 4.7
Clock Pulse Width High 4
Input Low to Clock Low (START) 4
Clock Low to Input Transition 0
Clock Pulse Width Low 4.7
Input Transition to Clock Transition 2 50 ns
Clock High to Input High (STOP) 4.7
Input High to Input Low (Bus Free) 4.7
Clock Low to Next Data Out Valid 0.3 3.5
Data Out Hold Time 300 ns
Clock Frequency 100 kHz
Write Time 10 ms

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

Tabl e 8. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages 0.2V
Input and Output Timing Ref.

Voltages

50ns

≤

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Figure 4. AC Testing Input Output Waveforms

0.8V

6/17

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

DEVICE OPERATION

2

C Bus Background

I
The ST24/25x16 support the I

2

C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn­chronisation. The ST24/25x16 are always slave
devices in all communications.

Start Co nditi on. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST ART condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Figure 5. AC Waveforms

ST24/25C16, ST24/25W16

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

WRITE CYCLE

tCHDX

START

CONDITION

AI00795B

7/17

ST24/25C16, ST24/25W16

Figure 6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25x16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.

Acknowledge B it ( ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, eit her master or s lave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls t he SDA
bus low to acknowledge the receipt of the 8 bits of
data.

8/17

Data Input. During data input the ST24/25x16
samples the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera­tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.

Memory Addressing. To start communication be­tween the bus master and the slave ST24/25x16,
the master must initiate a START condition. The 8
bits sent after a STA RT c ondition are made up of a
device select of 4 bits that identifie the device type
(1010), 3 Block select bits and one bit for a READ

W = 1) or WRITE (RW = 0) operation.

(R
There are three modes both for read and write.

They are summarised in Table 4 and described
hereafter. A communication between the master
and the slave is ended with a STOP condition.

Figure 7. Memory Protection

7FFh

700h

Block
Select

Protect Location
16 byte

boundary
address

b7 b4 b2

0

PB1 PB0

1

Protect Flag
Enable = 0
Disable = 1

XX

Block 7

ST24/25C16, ST24/25W16

PB1 PB0

1

1

600h

500h

400h

Write Operations

The Multibyte Write mode (only available on the
ST24/25C16 versions) is selected when the MODE
pin is at V
pin is at V

and the Page Write mode when MODE

IH

. The MODE pin may be driven dynami-

IL

cally with CMOS input levels.
Following a START condition the master sends a

device select code with the R

W bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac­cess to any of the 256 bytes of one memory block.
After receipt of the byte address the device again
responds with an acknowledge.

For the ST24/25W16 vers ions, any write command

WC = ’1’ (during a period of time from the

with
ST ART condition untill the end of the Byte Address)
will not modify data and will NOT be acknowledged
on data bytes, as in Figure 10.

Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode

Block 6

Block 5

Block 4

1

0

0

AI00870B

0

1

0

is independant of the state of the MODE pin whic h
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either V
or VIL, to minimize the stand-by current.

Multibyte Write (ST24/25C16 only). For the Mul­tibyte Write mode, the MODE pin must be at V

IH

The Multibyte Write mode can be started from any
address in the memory . The master sends from one
up to 8 bytes of data, which are each acknowledged
by the memory. The transfer is terminated by the
master generating a STOP condition. The duration
of the write cycle is t

= 10ms maximum except

W

when bytes are accessed on 2 contiguous rows
(one row is 16 bytes), the programming time is then
doubled to a maximum of 20ms. W riting more than
8 bytes in the Multibyte Write mode may modify
data bytes in an adjacent row (one row is 16 by tes
long). However, the Multibyte Write can properly
write up to 16 consecutive bytes only if the first
address of these 16 bytes is the first address of the
row, the 15 following bytes being written in the 15
following bytes of this same row.

IH

.

9/17

ST24/25C16, ST24/25W16

Page Write. For the Page Write mode, the MODE

pin must be at V

. The Page Write mode allows up

IL

to 16 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the same Block A ddress bits
(b3, b2, b1 of Device Select code in Table 3) and
the same 4 MSBs in the B yte Address. The master
sends one up to 16 bytes of data, which are each
acknowledged by the memory. After each byte is
transfered, the internal byte address counter (4
Least Significant Bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad­dress counter ’roll-over’ which could res ult in data
being overwritten. Note that for any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.

Figure 8. Write Cycle Polling using ACK

WRITE Cycle

in Progress

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the memory discon­nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the Write time (t

) is given in the

W

AC Characteristics table, this timing value may be
reduced by an ACK polling sequence is sued by the
master.

The sequence is:
– Initial condition: a Write is in progress (see Fig-

ure 8).

– Step 1: the Master issues a ST A R T condition

followed by a Device Select byte (1st byte of
the new instruction).

– Step 2: if the memory is internally writing, no

ACK will be returned. The Master goes back
to Step1. If the memory has terminated the in­ternal writing, it will issue an ACK indicating
that the memory is ready to receive the sec­ond part of the instruction (the first byte of this
instruction was already sent during Step 1).

First byte of instruction
with RW = 0 already
decoded by ST24xxx

ReSTART

STOP

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

YES

Next

Operation is

Addressing the

Memory

WRITE Operation

YESNO

Proceed

Send

Byte Address

Proceed
Random Address
READ Operation

10/17

AI01099B

ST24/25C16, ST24/25W16

Write Protection. Data in the upper four blocks of

256 bytes of the memory may be write protected.
The memory is write protected between a boundary
address and the top of memory (address
7FFh).The boundary address is user defined by
writing it in the Block Address Pointer (location
7FFh).

The Block Address Pointer is an 8 bit EEPROM
register located at the address 7FFh. It is com­posed by 4 MSBs Address Pointer, which defines
the bottom boundary address, and 4 LSBs which
must be programmed at ’0’. This Address Pointer
can therefore address a boundary by page of 16
bytes.

The block in which the Block Address Pointer de­fines the boundary of the write pr otected memory
is defined by the logic level applied on the PB1 and
PB0 input pins:

– PB1 =’0’and PB0 =’0’ select block 4
– PB1 =’0’and PB0 =’1’ select block 5
– PB1 =’1’and PB0 =’0’ select block 6
– PB1 =’1’and PB0 =’1’ select block 7
The following sequence should be used to set the

Write Protection:
– write the data to be protected into the top of

the memory , up to, but not including, location
7FFh;

– select the block by hardwiring the signals PB0

& PB1;

– set the protection by writing the correct bottom

boundary address in the Address Pointer (4
MSBs of location 7FFh) with bit b2 (Protect
Flag) set to ’0’.

Note that for a correct fonctionality of the memory,
all the 4 LSBs of the Block Address Pointer must
also be programmed at ’0’. The area will be pro­tected when the PRE input is taken High.

Remark:

The Write Protection is active if and only
if the PRE input pin is driven High and the bit 2 of
location 7FFh is set to ’0’. In all the other cases, the
memory Block will not be protected. While the PRE
input pin is read at ’0’ by the memory, the location
7FFh can be used as a normal EEPROM byte.

Caution:

Special attention must be used when
using the protect mode together with the Multibyte
Write mode (MODE input pin High). If the Multibyte
Write starts at the location right below the first byte
of the Write Protected area, then the instruction will
write over the first 7 bytes of the Write Protected
area. The area protected is therefore smaller than
the content defined in the location 7FFh, by 7 bytes.
This does not apply to the Page Write mode as t he
address counter ’roll-over’ and thus cannot go
above the 16 bytes lower boundary of the protected
area.

Figure 9. Write Modes Sequence (ST24/25C16)

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

MULTIBYTE
AND
PAGE WRITE

DEV SEL BYTE ADDR

START

ACK ACK

DATA IN N

ACK ACK ACK

R/W

ACK ACK ACK

DATA IN 1 DATA IN 2

R/W

STOP

STOP

AI00793

11/17

ST24/25C16, ST24/25W16

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16)

WC

ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

R/W

START

WC

ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

STOP

DATA IN 2

AI01161B

Read Operation

Read operations are independent of the state of the
MODE signal. On delivery, the memory content is
set at all "1’s" (or FFh).

Current Address Read. The memory has an in­ternal byte address counter. Each time a byte is
read, this counter is incremented. For the Current
Address Read mode, following a ST ART c ondition,
the master sends a memory address with the R

W
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out­put, but terminates the tr ansfer with a STOP con­dition.

12/17

Random Address Read. A dummy write is per­formed to load the address into the address counter
(see Figure 1 1). This is followed by another ST AR T
condition from the master and the byte address
repeated with the R

W bit set to ’1’. The memory
acknowledges this and outputs the byte ad­dressed. The master does NOT acknowledge the
byte output, but terminates the transfer with a
STOP condition.

Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se­quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-

Figure 11. Read Modes Sequence

ST24/25C16, ST24/25W16

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK

DEV SEL * BYTE ADDR

NO ACK

STOP

ACK ACK

DEV SEL * DATA OUT

R/W

START

DEV SEL * DATA OUT 1

NO ACK

STOP

DATA OUT N

STOP

ACK ACK

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat­ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.

START

Acknowledge in Read Mode. In all read modes
the ST24/25x16 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x16 terminate the
data transfer and switches to a standby state.

R/W

AI00794C

13/17

ST24/25C16, ST24/25W16

ORDERING INFORMATION SCHEME

Example: ST24C16 M 1 TR

Operating Voltage

24 4.5V to 5.5V
25 2.5V to 5.5V

Note:

1. Temperature range on special request only.

Range

C Standard

W Hardware

Write Control

Package

B PSDIP8

0.25mm Frame

M SO8

150mil Width

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

(1)

3

–40 to 125 °C

Option

TR Tape & Reel

Packing

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

14/17

ST24/25C16, ST24/25W16

PSDIP8 - 8 pin Plastic S ki nny DIP, 0.25mm lea d f ram e

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB – 10.00 – 0.394

L 3.00 3.80 0.118 0.150

N8 8

mm inches

Drawing is not to scale.

A2

A1AL

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

15/17

ST24/25C16, ST24/25W16

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –
H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

mm inches

0

°

8

°

0

°

8

°

Drawing is not to scale.

16/17

B

SO-a

h x 45˚

A

C

e

CP

D

N

E

H

1

LA1 α

ST24/25C16, ST24/25W16

Information furnished is believ ed to be accura te a nd rel i abl e. However, STMicroelec tronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelect roni cs

© 1999 STMicroelectronics - All Rights Reserved

All other names are the property of their respective owners

2

2

I

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Purchase of I

C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

C Components by STMicroelectronics, conveys a license under the Philips

2

C Standard Specifications as defined by Philips.

the I

STMicroelectronics GROUP OF COMPANIES

http://www.st.com

17/17