SGS Thomson Microelectronics ST18AU1-DS Datasheet

February 98 42 1726 00

This ispreliminary information on aproduct indevelopment orundergoing evaluation. Detailsare subject to change without notice.

ST18-AU1

SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER

PRELIMINARY DATA

FEATURES

■ Single chip multi-function audio decoder able to

decompress DOLBY AC-3, MPEG-1 and
MPEG-2 audio streams.

■ Maximum 5.1 channel DOLBY AC-3 decoding

to 2 channel mixed down output with DOLBY
surround compatible or karaoke capable option.

■ Variable bit rate MPEG-1 layer II audio

decoding, and MPEG-2 multi-channel audio
decoding for karaoke capable application.

■ Input data rates

■ up to 448 Kbits/s for AC-3 decoder

■ up to 912 Kbits/s for MPEG-1 or MPEG-2

audio decoder

■ Supports up to 8 channel DVDlinear PCMinput

at max rate of 6.144 Mbits/s down-mixing and/
or sub-sampling to 2 to 6 channels.

■ Accepts MPEG-1 or DVD/MPEG-2 PES input

packets.

■ Programmable D950 core

■ System time clock provides A/V

synchronization and PTS packet extraction.

■ Automatic error concealment on CRC or

synchronization error.

■ 6 channel PCM audio output at 16/18/20/24 bit.

Sampling rate of 32/44.1/48/96 kHz.

■ Two on-chip PLLs providing full circuit operation

with only one external 27 MHz clock.

■ I

2

C interface for host control

■ Multi-format i

2

S serial data input port and

decoded audio PCM output port.

■ IEC-958 (S/PDIF) formatter and transmitter for

DOLBY AC-3, MPEG audiobit stream, oraudio
PCM.

■ Dedicated hardware for emulation and test,

IEEE 1149.1 (JTAG).

■ 3.3V power supply, I/O’s 5V tolerant, 0.35µM

HCMOS6 technology.

■ 160 pin PQFP package

APPLICATIONS

■ Digital video disc (DVD) player

■ Digital TV (DBS/DVB) receiver

■ PC multimedia

■ Consumer digital audio

Interrupt

controller

Clocks and

timers

I2C Host
interface

2

Input serial

interface

IEC-958

(S/PDIF)

output

16K Program

memory

3

Output serial

interface

D950

DSP

core

24K Data

memory

DMA

controller

Emulation

unit and TAP

Bus switch

unit

2/87

Table of Contents

4

1 INTRODUCTION......................................................5

2 PINDESCRIPTIONS................................................... 7

3 FUNCTIONALOVERVIEW .............................................12

4 HOSTINTERFACE ...................................................16

4.1 HOSTINTERFACEREGISTERS ...................................16

4.2 LISTOFHOSTCOMMANDS ......................................19

5 INPUTSERIALINTERFACE............................................25

5.1 INPUT SERIAL INTERFACE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 INPUT FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................27

5.2.1 Input FIFO registers . . . . . . . . . . . . . . . . . . . .....................27

6 INPUTANDOUTPUTBUFFERS ........................................ 29

6.1 INPUTBUFFER.................................................29

6.2 OUTPUTBUFFER ...............................................29

6.2.1 Input and output buffer registers . . . . ..........................29

7 OUTPUTSERIALINTERFACE-PCMOUTPUT ............................31

7.1 OUTPUTSERIALINTERFACEREGISTERS ..........................31

8 INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . ........................34

8.1 INTERRUPT CONTROLLER REGISTERS . . . . . . . . ....................35

9 DMACONTROLLER..................................................40

9.1 DMAOPERATION ...............................................40

9.2 DMAREGISTERS ...............................................41

9.2.1 Address registers . . . . . . . . . . . . . . . . . . ........................41

9.2.2 Counting registers . . ....................................... 41

9.2.3 Control registers . .......................................... 42

10 IEC-958 TRANSMITTER . . . . . . . . ....................................... 44

10.1 IEC-958 TRANSMITTER REGISTERS . . . . . . . . . . . . . . . . . . . . . ..........44

11 MEMORY ..........................................................46

11.1 INTERNALMEMORYRESOURCE..................................46

11.2 I-MEMORY BUS EXTENSION - DIRECT AND THROUGH BSU . . . . . . . . . . . 47

11.3 X-MEMORY BUS EXTENSION - DIRECT AND THROUGH BSU ...........47

11.4 Y-MEMORY BUS EXTENSION THROUGH BSU . . . . . . . . . . .............47

12 BUSSWITCHUNIT...................................................48

12.1 BSUCONTROLREGISTERS ...................................... 48

13 CLOCKS AND TIMERS UNIT . . . . . . . . . . .................................51

13.1 OPERATION ................................................... 51

1

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Table of Contents

13.1.1 Audio clock prescaler . . . ....................................51

13.2 CLOCKS AND TIMERS REGISTERS . . . .............................52

14 JTAGIEEE1149.1TESTACCESSPORT.................................55

15 EMULATIONUNIT ...................................................56

16 D950CORE .........................................................58

16.1 D950COREREGISTERS..........................................60

17 YSPACEMEMORYMAPPING .........................................61

17.1 MEMORYMAP .................................................61

17.2 CLOCKS AND TIMERS REGISTERS . . . .............................62

17.3 IEC-958 TRANSMITTER (S/PDIF OUTPUT) REGISTERS . . . .............63

17.4 PCMREGISTERS ............................................... 63

17.5 INPUT/OUTPUT BUFFER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

17.6 SERIALINPUT1REGISTERS .....................................64

17.7 SERIALINPUT0REGISTERS .....................................64

17.8 HOSTINTERFACEREGISTERS ...................................64

17.9 BUSSWITCHUNITREGISTERS ...................................64

17.10PLLREGISTERS ................................................ 65

17.11DMACONTROLLERREGISTERS ..................................65

17.12 INTERRUPT CONTROLLER REGISTERS ............................66

17.13D950CORECONTROLREGISTERS................................66

17.14 DATA AND PROGRAM MEMORY MAPPING . . . . . . . . . . . . . . . . ..........67

18 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .............68

18.1 DCABSOLUTEMAXIMUMRATINGS................................68

18.2 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

18.3 ACCHARACTERISTICS .......................................... 69

18.3.1 Clocks electrical characteristics . . .............................72

18.3.2 E-bus (I direct extension) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

18.3.3 E-bus (X direct extension) . . . . . . . . . . . . . . . ....................74

18.3.4 E-bus (I BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 75

18.3.5 E-bus (X BSU) . . ..........................................76

18.3.6 E-bus (Y BSU) . . ..........................................77

18.3.7 D950 control . . . . . . . . . . . . . .................................78

18.3.8 I2C Host interface . . . . . ....................................79

18.3.9 PCM and SPDIF .......................................... 80

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Table of Contents

4

18.3.10I2S Data Input 0 . ..........................................81

18.3.11I2S Data Input 1 . ..........................................82

19 ST18-AU1 PACKAGE SPECIFICATIONS . . . . . . . . . . .......................83

19.1 ST18-AU1 PACKAGE PINOUT . ....................................83

19.2 160PINPQFPPACKAGEDIMENSIONS .............................84

20 DEVICEID..........................................................86

21 ORDERING INFORMATION . . . . . . . . . . . . . . . . . ...........................86

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ST18-AU1

1 INTRODUCTION

The ST18-AU1 is a single-chip multi-function audio processor for Dolby AC-3, MPEG-1/
MPEG-2 Layer-I/II audio encoded bitstreams, and DVD Linear PCM. It is capable of decoding
up to 5.1 channels of input Dolby AC-3 or MPEG-2 multi-channel encoded audio, and down
mixing to 2 channels of PCM output audio. Maximum input data rates for Dolby AC-3 bitstream
and MPEG-2 audio bitstream are 448 Kbits/s and 912 Kbits/s respectively. It also supports up
to 8 channel linear PCM input with by-pass, down-sampling, and down-mixing function. The
linear PCM multi-channel input modes available are:

• 48 kHz/16-bit up to 8 ch @ max 6.144 Mbps

• 48 kHz/20-bit up to 6ch @ max 5.760 Mbps

• 48 kHz/24-bit up to 5ch @ max 5.760 Mbps

• 96 kHz/16-bit up to 4ch @ max 6.144 Mbps

• 96 kHz/20-bit up to 3ch @ max 5.760 Mbps

• 96 kHz/24-bit up to 2ch @ max 4.608 Mbps

• 44.1 kHz/16-bit 2ch (CD-DA).

The input bitstream is taken from the multi-format serial input, and decoded according to the
selected MPEG-1, MPEG-2 (in the case of Karaoke capable mode), AC-3 decoder or Linear
PCM processor. A Packet Demux de-multiplexes the input if it is MPEG-1 or DVD/MPEG-2
PES packetized. For an input bitstream with more than 2 encoded audio channels, the
decoded channels are mixed down to 2 channels with the Dolby Surround compatible or
karaoke capable option, and outputted through a multi-format serial output port. The input AC­3, MPEG bitstream, or decoded PCM can be outputted through an IEC-958 (S/PDIF)
Formatter/Transmitter. The AC-3 or MPEG S/PDIF output bitstream is delayed and
synchronized with the output decoded PCM.

The Karaoke Capable mode defined in Dolby AC-3 or DVD to allow the multi-channel audio
stream to convey channels designed as L, R (2-ch stereo music), M (guide melody), and V1,
V2 (one or two vocal/supplementary tracks) are supported. This Karaoke capable decoder
allows the user to choose to have the decoder reproduce any of the guide melody and vocal/
supplementary channels. Centre and surround mix levels either controlled by the user or within
the bitstream are used to down mix the M channel and the V1, V2 channels respectively.

The selectable Linear PCM Processor functions are:

• down-mixing to 2 channels,

• down-sampling for 96kHz to 48kHz,

• noise shaped quantization for 24-bits or 20-bits to 16-bits.

Depending on the application, the decoded PCM audio output is selectable to be 16, 18, 20 or
24 bits, and the sampling rates of the PCM output are 32 kHz, 44.1 kHz, 48 kHz or 96 kHz.

External A/V synchronization can be assisted by the System Time Clock (STC) within the
Timer and the PTS extracted from the packetized input. A serial I

2

C interface to host

2

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ST18-AU1

microcontroller is provided to allow ST18-AU1 operation control, bitstream information and
internal status access.

A typical DVD back-end system configuration is shown in Figure 1.1.

Figure 1.1 Typical DVD back-end system configuration

Video bitstream

Control

DRAM

MPEG-2 video

decoder

27 MHz osc

Video

encoder

ST18-AU1

audio

processor

Audio DAC

System layer

controller

Audio bitstream

Control

I2C

I2S

Compressed
system input
bitstreams

Video
output

L/Lt

R/Rt

IEC-958
(S/PDIF)
AC-3/MPEG

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ST18-AU1

2 PIN DESCRIPTIONS

The following tables detail the ST18-AU1 pin set. There is one table for each group of pins.
The tables detail the pin name, type and a short description of the pin function.

Signal names have a bar above if they are active low, otherwise they are active high.

Table 2.1 Direct I bus extension (35 pins)

Pin name Type Description

IDE0-15 I/O Instruction data extension bus.
IAE0-15 O Instruction address extension bus.
IRDE O I-extension bus read strobe.Active low.
IWRE O I-extension bus write strobe. Active low.
IBSE O I-extension bus strobe. Active low. Asserted at the beginning of I-bus read/

write cycle.

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ST18-AU1

Table 2.2 Direct X bus extension / Bus extension through bus switch unit (39 pins)

Table 2.3 General purpose parallel port (8 pins)

Pin name Type Description

ED0-15 I/O Bus switch unit (BSU) X/Y/I data extension bus.
EA0-15 O BSU X/Y/I address extension bus.
EIRD O BSU I-extension bus read strobe EIRD output.
EIWR O BSU I-extension bus writestrobe EIWR output.
XBSE O X_extension bus data strobe (BSU not used).
EYRD O BSU Y-extension bus read strobe EYRD output.
EYWR O BSU Y-extension bus write strobe EYWR output.
XRDE_EXRD O Multiplexed output.

In direct X-bus extension mode (BSU not used):
X-extension bus read strobe (XRDE). Active low when reading from exter­nal X-memory.
In X extension through BSU mode:
BSU X-extension bus read strobe (EXRD). Active low when reading from
external memory (when bit I/Mof XER register is ‘1’: Intel mode).
BSU extensionbus data strobe (EDS). Activelow when reading fromorwrit­ing to external memory (when bit I/M of XER register is ‘0’ Motorola mode).

XWRE_EXWR O Multiplexed output.

In direct X-bus extension mode (BSU not used):
X-extension bus write strobe (XWRE). Active low when writing to external
X-memory.
In X extension through BSU mode:
BSU X-extension bus write strobe (EXWR). Active low when writing to ex­ternal memory (when bit I/M of XER register is ‘1’: Intel mode).
Extension bus read /write signal (ERD_WR). Low during write cycle, other­wise high (when bit I/M of XER register is ‘0’: Motorola mode).

Pin name Type Description

P0-7 I/O Parallel port I/O. Each pin can be programmed as input or output.

On reset, all pins are inputs.

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ST18-AU1

Table 2.4 Clocks (13 pins)

Table 2.5 I

2

C Host interface (3 pins)

Pin name Type Description

EXTAL0 I Oscillator0 input. DSP PLL.
XTAL0 O Oscillator0 output. Nominal oscillator frequency is 27 MHz.
EXTAL1 I Oscillator1 input. Audio PLL
XTAL1 O Oscillator1 output. Nominal oscillator frequency is 27 MHz.
CLK0 I Direct clock input for D950 core.
CLK0_MODE I Clock0 mode select input.

When low, select output of DSP PLL for DSP Clock In

When high, select CLK0 (bypass DSP PLL) for DSP Clock In
CLK1 I Direct audio clock input.
CLK1_MODE I Clock1 mode select input.

When low, select output of audio PLL for audio clock

When high, select CLK1 (bypass audio PLL) for DSP Clock In
PLL_MODE I PLL mode select input

When low, select oscillator 1 for audio PLL

When high, select oscillator 0 for audio PLL
CLKOUT O Output clock (at input clock/2 frequency).
INCYCLE O Instruction cycle.

Asserted high for 1 CLKOUT cycle at the beginning of instruction cycle.
SCLK I/O External audio clock/audio clock prescaler output
MCLK_MODE I SCLK mode select input

When low,SCLK = output (internal audio master clock from clock prescaler)

When high, SCLK = input (external audio master clock)

Pin name Type Description

HDA I/O I2C Data input/output (open drain output).
HCL /O I2C Clock input/output (open drain output).
HSAS I Slave address select

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ST18-AU1

Table 2.6 Data input 0 (4 pins)

Table 2.7 Data input 1 (3 pins)

Table 2.8 PCM output (5 pins)

Table 2.9 IEC-958 transmitter (SPDIF) output (1 pin)

Table 2.10 Interrupt controller interface (1 pin)

Pin name Type Description

DIN0 I Serial data input
CLKDIN0 I/O Data input clock

Input in slave mode, output in master mode.
WSDIN0 I/O Data input word select

Input in slave mode, output in master mode.
DREQ0 O Request for data input. Active low.

Pin name Type Description

DIN1 I Serial data input
CLKDIN1 I Data input clock

Input in slave mode, output in master mode.
WSDIN1 O Data input word select

Input in slave mode, output in master mode.

Pin name Type Description

PCM_OUT0 O PCM data output 0
PCM_OUT1 O PCM data output 1
PCM_OUT2 O PCM data output 2
SCLKPCM O PCM output clock (common)
WSPCM O PCM output word select (common)

Pin name Type Description

SPDIFOUT O S/PDIF signal

Pin name Type Description

IRQ I Interrupt request. Active low.

Maskable, programmable as falling edge or low level triggered (default is

level triggered).

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ST18-AU1

Table 2.11 D950-Core control (3 pins)

Table 2.12 Emulation unit (4 pins)

Table 2.13 JTAG IEEE 1149.1 test access port(5 pins)

Pin name Type Description

RESET I Reset input. Active low.

Initializes the 950-Core to the Reset state.
LP I Low power input. Active low.
MODE_RESET I Mode selection for Reset.

When low, forces reset address to 0x0000.

When high, forces reset address to 0xFC00.

Pin name Type Description

ERQ I Emulator halt request. Active low.

Halts program execution and enters emulation mode.
IDLE O Output flag asserted high whenthe processor is halted due to an emulation

halt request or a valid breakpoint condition.Asserted low when the proces-

sor is not Halted or during execution of an instruction under control of the

emulator.
HALTACK O Halt acknowledge. Active high.

Asserted high when the processor is halted from an Emulator Halt request

or when a valid Breakpoint condition is met.
SNAP O Snapshot. Active high.

Asserted high when executing an instruction if Snapshot mode is enabled.

Pin name Type Description

TDI I Test data input.
TCK I Test clock.
TMS I Test mode select.
TDO O Test data output.
TRST I Test logic reset (also used for Emulator module). Active low.

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ST18-AU1

3 FUNCTIONAL OVERVIEW

A functional block diagram of the ST18-AU1 is shown in Figure 3.1. The modules that
comprise the ST18-AU1 are outlined below and more detailed information is given in the
following chapters of this datasheet. The interconnection of these blocks and all external
interfaces are shown in the block diagram in Figure 3.2.

Figure 3.1 Functional block diagram

Timer

Host

interface

Serial

Packet
demux

interface

Linear PCM

MPEG2

decoder

Dolby AC-3

decoder

processor

Down mix

(surround)

(or Karaoke

modes)

Serial

S/PDIF

formatter

output

System

manager

Delay

Clock
inputs

Commands
status

Data
input

2 to 6 channel
PCM output

S/PDIF
output
(AC-3/MPEG
or 2 ch PCM)

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ST18-AU1

Figure 3.2 ST18-AU1 block diagram

Host interface

The I

2

C serial bus interface operated in slave mode enables connection to an external host
processor. It receives operating commands, and returns host requested bitstream information
and internal status.

Interrupt

controller

Clocks and

timers

Host

interface

2

TAP

16K Program

memory

16K X-data

8K Y-data

memory

IEC-958

DMA

controller

D950

DSP
core

ST18-AU1

P0-7

RESET

VCC

GND

Clocks

HCL

HDA

HSAS

(I2C host interface)

DIN

WSDIN

CLKDIN

DREQ

SPDIFOUT
(AC-3/MPEG or PCM)

IEEE 1149.1
JTAG interface

PCM_OUT

SCLKPCM

WSPCM

I-bus

X-bus

Y-bus

IT

9

Bus switch

unit

Direct X / bus

Input serial

interfaces

memory

IRQ

(S/PDIF)

output

3

Output serial

interfaces

switch
(39 pins)

(13 pins)

MODE_RESET

LP

Direct I bus
(35 pins)

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ST18-AU1

Input serial interface

The ST18-AU1 has two input serial interfaces. The interfaces are multi-format serial interfaces
for inputting audio bitstreams. Supported formats include delayed (I

2

S)/non-delayed, left/right
justified, 16/18/20/24-bit word, polarity options in L/R clock and input clock, and master/slave
mode. They provide the serial to parallel conversion and transfer the input data to the input
buffer for further processing.

Output serial interface

The ST18-AU1 has three output serial interfaces. The output serial interfaces organize the
PCM audio output into the required I

2

S serial format and generate allthe DAC control signals.

IEC-958 transmitter

The IEC-958 transmitter accepts either the AC-3/MPEG bitstream or the decoded audio output
PCM data, and formats the input in accordance with the IEC-958 (S/PDIF) specification for
output.

Interrupt controller (ITC)

The interrupt controller (ITC) manages the interrupts from the clocks and timers unit, the host
interface, and the external interrupt for the DSP core. The interrupt can be activated and
programmed as edge or level triggered.

DMA controller (DMAC)

The DMA controller (DMAC) controls data transfer between data input/output and internal data
buffers.

D950 DSP Core

The D950-Core is a general purpose programmable 16-bit fixed point Digital Signal Processor
Core. The main blocks of the D950-Core include an arithmetic data calculation unit, aprogram
control unit and an address calculation unit, able to manage up to 64k (program) and 128k
(data) x 16-bitmemory spaces.

The DSP core processes all host commands, performs input bitstream parsing,
decompression, sample down-mixing and/or subsampling, as well as input and output control.

Memory

There is 8 Kword Y-data memory on Y space, 16 Kword X-data memory on X space and 16
Kword instruction memory on I space.

Memory can be extended off-chip in one of three ways:

• Direct I-bus extension.

• Direct X-bus extension.

• I, X and Y -bus extension through the bus switch unit.

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ST18-AU1

Bus switch unit

The bus switch unit (BSU) is a bi-directional switcher. It switches the 3 internal buses (I, X and
Y) to the external (E) bus.

Clocks and timers unit

The clocks and timers unit provides all the necessary clocks and timer controls for DSP
processing, and all input/output operations. In addition, a 90 kHz System Time Clock (STC) is
provided to assist audio/video synchronization in systems which include a video decoder.

Emulation unit and JTAG IEEE 1149.1 test access port

The emulation unit (EMU) performs functions dedicated to emulation and test through the
external IEEE 1149.1 JTAG interface.

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ST18-AU1

4 HOST INTERFACE

The host interface is a fast I2C serial bus interface operated in slave mode. It provides
connection to an external host processor. It receives operating commands, and returns host
requested bitstream information and internal status.

4.1 Host interface registers

HSER: Host serial shift register

This 16-bit shift register is used for serial data input and output. Data is shifted MSB first. It is
not visible from the D950.

HDR: Host data register

This register is used for transfers between the HSER register and the D950.

Figure 4.1 Host interface data exchange, receive mode

msb654321lsb

HCL

HDA

ack

byte 0

msb654321lsb

byte 1 .....

YD

HDR

(16-bit words)

HDA

byte 0 byte 1

msb lsb

16-bit

16-bit

msb lsb

YD

8-bit

(msb)

8-bit

(lsb)

‘0’

byte 0

8-bit

(msb) (lsb)

HDR

(8-bit words)

HDA

HSER HSER

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ST18-AU1

Figure 4.2 Host interface data exchange, send mode

HCR: Host control register

All bits are cleared on reset.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - BER­RIEN

ACK­FIEN

STOPI-EN- HTIEN - - - - - ACK-

OFF

WS HEN

Bit Function

HEN Host interface enable

0 host interface disabled
1 host interface enabled

WS Word size

0 8-bit word
1 16-bit word

ACKOFF Acknowledge generation disable

0 acknowledge enabled
1 acknowledge disabled

msb654321lsb

HCL

HDA ack

byte 0

msb654321lsb

byte 1 .....

YD

HDR

(16-bit words)

HDA

byte 0 byte 1

msb lsb

16-bit

16-bit

msb lsb

YD

8-bit

(msb)

byte 0

8-bit

(msb) (lsb)

HDR

(8-bit words)

HDA

HSER HSER

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ST18-AU1

HSR: Host status register

All bits are reset when the register is read. The register can only be read by the D950.

HTIEN Transfer interrupt enable

0 transfer interrupt disabled
1 transfer interrupt enabled

STOPIEN Stop interrupt enable

0 stop interrupt disabled
1 stop interrupt enabled

ACKFIEN Acknowledge fail interrupt

0 acknowledge fail interrupt disabled
1 acknowledge fail interrupt enabled

BERRIEN Bus error interrupt

0 bus error interrupt disabled
1 bus error interrupt enabled

- RESERVED, read as 0.

15141312 11 10 9 8 765432 1 0

- - - BERR ACK-

FAIL

STOP HDRRRQHDRWRQ------DAT-

ADIR

BUSY

Bit Function

BUSY Set whenValid slave address detected, until Stopevent or Restart event with invalid slave

address.

DATADIR Data direction (valid when Busy bit is set).

0 receive data from host
1’ send data tohost

HDRWRQ HDR write request. Set when data is required by the host. Data needs to be written into

the HDR register, this is reset whenthe HSR register is read.

HDRRRQ Host read request. Set when data has been sent by the host. Data needs to be read from

the HDR register, this is reset whenthe HSR register is read.
STOP Stop. Set when a stop condition is detected.
ACKFAIL Acknowledge fail. Set when the host does not generate an acknowledge after one data

byte has been sent.
BERR Bus error.Set when a misplaced start or stop condition is detected during transmission.

- RESERVED, read as 0.

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ST18-AU1

HSAR: Host slave address register

(Default value for slave address on reset: HSAS (7...2) = 101000).

4.2 List of host commands

A list of host commands is given below.

15 14 13 12 11 10 9 8 76543210

HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 --------

Bit Function

HSA0 Data direction (read only, written from HSER when Slave address is send by the host.
HSA1 Slave address bit 1 (read only, value of pin HSAS)
HSA2 Slave address bit 2
HSA3 Slave address bit 3
HSA4 Slave address bit 4
HSA5 Slave address bit 5
HSA6 Slave address bit 6
HSA7 Slave address bit 7

- RESERVED, read as 0.

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ST18-AU1

Table 4.1 Write commands

Mnemonic Opcode

Size
(bits)

Command description and Parameter values

HostInputMode 00 8 Input mode (type of bitstream).

AC3 (default) 00
MPEG -1 01
MPEG-2 02
MPEG-2 with extension 03
PCM by pass 04
Linear PCM 05

HostInputStrmFormat 01 8 Input Stream Format

ES (Default) 00
DVD/PES 01

HostOpmode 02 8 Operating Mode

Idle (no decoding) (default) 00
Start (starts selected decoder) 01
Stop and flush (stops decoder and flush buffers) 02
Reset 03
SelfTest 04

HostMute 03 8 Mute

Off (default) 00
On 01

HostAudiStrmIdSel 04 8 Audio stream ID select

ID = 0(default) to 7 (e.g. language selection)00 - 07

HostOutputChanConf 05 8 Output channel configuration.

2/0 Lt/Rt, Dolby surround compatible X0
1/0 C X1
2/0 L/R (default) X2
3/0 LCR X3
2/1 LRl X4
3/1 LCRl X5
2/2 LRlr X6
3/2 LCRlr X7
Karaoke capable no vocal 0X
Karaoke capable vocal 1 1X
Karaoke capable vocal 2 2X
Karaoke capable vocal 1& 2 (default Karaoke) 3X

where X = do not care

HostDualMonoReproMode 06 8 Dual mono reproduction mode

Stereo (default) 00
Left mono 01
Right mono 02
Mixed mono 03

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ST18-AU1

HostDynRngeCompMode 07 8 Dynamic Range Compression Mode

Line-out Mode 00
Custom Mode, Analog Dialnorm 01
Custom Mode, Digital Dialnorm (default) 02
RF Demod Mode 03

HostDynRngeCutScaleFac 08 16 Dynamic Range Compression Cut Scale Factor

0 to 0x7FFF (at ‘0’ the compression is minimum, at
0x7fff the compression is maximum).
(default: 0x 7fff)

HostDynRngeBstScaleFac 09 16 Dynamic Range Compression Boost Scale Factor

0 to 7FFF (at ‘0’ the boost is minimum, at 0x7fff the
boost is maximum).
(default: 0x7fff)

HostPcmScaleFac 0A 16 PCM Scale Factor

0 to 7FFF (default)

HostOutLfeOn 0B 8 Output LFE Present

Off (default) 00
On 01

HostSpdifOutStrmFormat 0C 8 SPDIF OutputStream Format

(the SPDIF output can send either the PCM decoded
output, or the input encoded elementary stream)
AC3/MPEG (default) 00
PCM 01

HostSpdifOutputLatency 0D 16 SPDIF Output Latency

Delay between the decoder and the bitstream sent via
the SPDIF output. The delay is expressed in multiples
of 1/Fs, where Fs is the samplefrequency. The delay is
signed.
0xffff to 0x7ffff (default: 0)

HostSpdifSmpteFrmRat­Cod

0E 16 SPDIF SMPTEFrame Rate Code

not indicated 00
24/1001 01
24 02
25 03
30/1001 (default) 04
30 05
50 06
60/1001 07
60 08

Table 4.1 Write commands

Mnemonic Opcode

Size
(bits)

Command description and Parameter values

22/87

ST18-AU1

HostLpcmMixAlpha0-7
HostLpcmMixBeta0-7

0F-16
17-1E

16 Linear PCM Downmixing Coefficients

In LPCM mode: Alphai isthe coefficient to downmix the
channel i into the Left channel. Betai isthe downmixing
coefficient for channel i into the Right channel.
In Ac-3 Karaoke mode: the Alpha0 to Alpha5 are used
to downmix respectively the Left, Melody, Right,
Vocal1, Vocal2 channels.Beta0 to Beta5is respective­ly used todownmix into the Right channel.
Alpha0 to Alpha7, Beta0 to Beta7.

HostErrorConcealMod 1F 8 Error Concealment Mode

Mute (default) 00
Disabled 01
Skip 02

HostLowPower 20 8 Low Power Stand-by Mode

Off (default) 00
On 01

HostSerialInputCtrl 21 Serial Input Control

Defines the input format.
default: I2S slave

HostSerialInoutDiv 22 Serial Input Clock Division

In master mode define the clock rate of the input.)

HostSerialOutputCtrl 23 Serial Output Control

Defines the output format.
default: I2s master

HostSerialOutputDiv 24 16 Serial Output Clock Division

In master mode define the clock rate of the output.
default: set for 44.1 Hz

HostAudioClockSel 25 Audio Clock Selection

All clocks derived from the 27MHz (default) 11

HostSamplFreq 26 16 Audio Sample Frequency (Hz)

3200 10
44100 (default) 00
48000 01

HostPcmNbBits 27 16 Number of bits per sample

16 (default) 16
18 18
20 20

WriteStc 80 32 System Time Clock

Table 4.1 Write commands

Mnemonic Opcode

Size
(bits)

Command description and Parameter values

23/87

ST18-AU1

Table 4.2 Read commands

Mnemonic Opcode

Size
(bits)

Command description and parameter value

HostVersion 40 16 Version number
HostI2cStatus 41 8 I2cStatus

No error 00
Error 01

HostInputStatus 42 8 InputStatus

No error 00
Overflow 01
Underflow 02

HostOutputStatus 43 8 OutputStatus

No error 00
Underflow 01
Overflow 02
Error decoder 04

HostSPDIFStatus 44 8 SPDIF Status

No error 00
Error 01

HostOpMode 45 8 OutputMode

(Refer to output channel configuration)

HostAudDecodErrorStatus 46 16 Audio Decoder Error Status

No error 0
Sync word 1
Sample frequency 2
Frame size 3
Number of channels 4
Decoder errors 5…f
Crc 10

HostInputSamplFreq 47 8 Input Sampling Frequency

Sampling frequency specified by the bitstream.
For AC-3 fscod is returned.

HostInputDatRate 48 8 Input Data Rate

Data rate specified by the bitstream.
For AC-3 frmsizecod is returned.

HostInputMultiChanMode 49 8 InputMultiChannelMode

For AC-3 acmod is returned.

HostKaraokCapBitstrm 4A 8 Karaoke Bitstream

Non Karaoke 00
Karaoke 01

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ST18-AU1

HostLfePresent 4B 8 Lfe Present

Lfe not present 00
Lfe present 01

HodtCopyProtect 4C 8 Copy Protected

Not protected 00
Protected 01

HostOpModeOut 4D 8 Operating Mode

Idle 00
Synchronising 01
Decoding 02

HostInputBitstrmStatus 4E 8 Input Bitstream Status

Idle 00
Searching for PES sync word 01

Searching for audio frame syncword 04
STC 81 32 System Time Clock
PTS 82 32 Presentation Time Stamp

Table 4.2 Read commands

Mnemonic Opcode

Size
(bits)

Command description and parameter value

25/87

ST18-AU1

5 INPUT SERIAL INTERFACE

The ST18-AU1 has two input serial interfaces (DIN0 and DIN1). The interfaces are multi­format serial interfaces for inputting audio bitstreams. Supported formats include delayed
(I

2

S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and
input clock, and master/slave mode. They provide the serial to parallel conversion and transfer
the input data to the input buffer for further processing.

Data input interface 0 (DIN0) operates with an input FIFO which regulates the input data flow
transferred to the input buffer. Data input interface 1 (DIN1) operates in a similar way to DIN0
but it does not have an associated input FIFO.

5.1 Input serial interface registers

Each input serial interface has the following set of registers.

DIN0-1CR: Data in control register

On reset, all bits are cleared.

1514131211109876543210

--------Mas­ter

Justi-

fied

De-

layed

WS_polCLK_

pol

WS DIN-

EN

Bit Function

DINEN Input interface enable

0 input interface disabled
1’ input interface enabled

WS Input word size

Bit1 Bit 0 Input word size
0 0 16 bit
0 1 18 bit
1 0 20 bit
1 1 24 bit

CLK_pol Clock polarity

0 data and WS change on Clk falling edge
1 data and WS change on Clk rising edge

WS_pol Word size polarity

0 Left data word = WS low, Right data word = WS high
1 Left data word = WS high, Right data word = WS low

Delayed Delay inserted before first bit of data following transition of WS.

0 first bit of data occurs on transition of WS
1 first bit of data occurs with 1 Clk cycle delay relative to transition of

WS (I2S compatible).

26/87

ST18-AU1

DIN0-1DIV: Data in division register

On reset, DIN0DIV value is set to 0.

DIN1DR: Data in output register

This 16-bit register contains the serial interface input data and is read by the D950.

Justified If number of Clk cycles between WS transitions is >n(= word size)

0 start justified:nbits read, starting from first bit:

just after WS transition if Delayed =’0’
with 1 clk cycle delay after WS transition if Delayed=’1’

1 end justified, end bit beein last bit received:

just before WS transition if Delayed =’0’
just after WS transition if Delayed =’1’

Master Master or slave operation

0 slave
1 master

NOTE: this bit must be defined before the input interface enable (DINEN) bit is set.

- RESERVED, read as 0.

1514131211109876543210

-------- DINDIV

Bit Function

DINDIV MCLK_DIN divide factor

00000000’ 1
00000001 2

..... ......

11111111 ’510 ‘

f

CLKDIN

=

fMCLK_DIN

/2(DIN0DIV) if DIN0DIV /= ‘00000

RESERVED, read as 0.

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ST18-AU1

5.2 Input FIFO

Associated with input serial interface 0 (DIN0) is a 32 byte input FIFO. It is used for temporary
storage of incoming data during processing of packet headers or AC3/MPEG decoding. The
input FIFO provides the following:

• transfer ofdata to the input buffer on a word basis

• packet header processing when operating on PES

• detection of FIFO overflow and FIFO filled to a predefined level

5.2.1 Input FIFO registers

FIFOCR: Input FIFO control register

On reset, all bits are cleared. The FIFO is cleared and the formatter is set to the ‘empty’ state.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - CLR_Form- DIN0_IEN- DREQ_
SEL

FIFO_level DMA_

mod

DREQ

_EN

-

Bit Function

DREQ_EN DREQ enable

0 DREQ= 0
1 DREQ set according to FIFO threshold/full level

DMA_mod DMA mode

0 DMA request always enabled
1 DMA request enabled only when PDC not equal to 0 (PES

processing)

FIFO_level FIFO threshold level (MSB=7, LSB=3). Set FIFO filling level for IRQ/DREQ manage-

ment.

DREQ_SEL DREQ signal settings (if DREQ_EN = 1)

0 DREQ is asserted high when FIFO threshold is reached
1 DREQ is asserted high when FIFO is full (if DREQ_EN=1)

DIN0_IEN DIN0 interrupt enable

0 interrupt disabled
1’ interrupt enabled (when FIFO_THS = 1)

CLR_Form Set formatter empty (active only at write time of FIFOCR)

- RESERVED, read as 0.