SGS Thomson Microelectronics ST16CF54 Datasheet

®

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DATA BRIEFING

This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact
your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: [phone]

ST16CF54 Level B

Smar tcard MCU

With 4 KBytes EEPROM

&

512 Bits Modular Arithmetic Processor

■

8 BIT ARCHITECTURE CPU

■

16 KBytes of USER ROM SECTOR
COMBINATIVE

■

8 KBytes of SYSTEM ROM

■

512 Bytes of RAM

■

4 KBytes of EEPROM, SECTOR
COMBINATIVE

■

512 BITS MODULAR ARITHMETIC
PROCESSOR

– Fast modular multiplication and squaring us-

ing Montgomery method

– Driven by STMicroelectronics cryptographic

library

■

EFFICIENT CRYPTOGRAPHIC LIBRARY
– Embedded software for driving the MAP

through a set of advanced functions

– Supports modu lar and no n modular ari thme-

tic

– Operand length can be any size up to 1 024

bits
– Highly reliable CMOS EEPROM technology
– 10 year data retention
– 100,000 Erase/Write cycle endurance
– Protected One Time Programmable block (32

or 64 Bytes)
– Separate Write and Erase cycle fo r fast “1”

programming
– 1 to 32 Bytes block either Erase or Write in

single cycle programming

■

SERIAL ACCESS, ISO 7816-3 COMPATIBLE

■

SINGLE 5V ±10% SUPPLY VOLTAGE

■

STANDBY MODE FOR POWER SAVING

■

UP TO 5 MHz I N TERNAL OP E RATING
FREQUENCY

■

VERY HIGH SECURITY FEATURES
INCLUDING EEPROM FLASH ERASE

■

CONTACT ASSIGNMENT COMPATIBLE ISO
7816-2

■

ESD PROTECTION GREA TE R THA N 5000V

■

2 OPE RATING CO NFIGURA T IONS
–ISSUER
– USER

■

SOFTWARE SUPPORT
– Cryptographic Library
– Manager

■

FAST CRYPTOGRAPHIC FUNCTIONS
PROCESSING

Note * 5MHz clock CPU

** CRT : Chines e Re m ai n der Theor em

Function Speed *

512 bits signature with CRT ** 125 ms
512 bits signature without CRT 375 ms
768 bits signature with CRT 350 ms
768 bits authentication (e=$10001) 190 ms
1024 bits signature with CRT 770 ms
1024 bits authentication (e=$10001) 265 ms

2

2

2

2

Micromodule (D4)

Wafer

1

BD.CF54-B/9809V2

ST16CF54 Level B

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DESCRIPTION

The ST16CF54 Level B, a member of the ST16
device family, is a serial access microcontroller
especially designed for high volume and cost
competitive Smartcard applications, where high
performance Public Key Algorithms will be imple­mented, to cut down initialization and communica­tion costs and to increase secu ri ty.

Its internal Modular Arithmetic Processor is de­signed to speed up c ryptographic calcul ations re­quired in Public Key Algorithms. It processes
hardware modular multiplication and squaring on
various size 32/256/288/384/416/512 bits oper­and. By using of software (cryptographic firmware
library) this calculation can be extended for any
size of operand from 3 to 1024 bits. The
ST16CF54 Level B is ba sed on an ST 8 bit CP U
core including on-chip memories: 512 Bytes of
RAM, 16 KBytes of USER ROM and 4 KBytes of
EEPROM.

Both ROM and EEPROM memorie s can be con­figured into two sectors. Access rules from any
memory section (sector) to another are setup by
the User defined Memory Access Control Matrix.

In addition, to reinforce the security of this product,
an hardware mechanism called SRAC (SYSTEM
ROM Access Control) has been implemented. It
protects against unauthorized access to both
SYSTEM ROM an d MAP .

Reliabilit y data re lated to t he ST16CF 54 Leve l B
product, manufactured using ST’s advanced
CMOS EEPROM tec hnology, confirm data reten­tion of up to 10 years and endurance up to
100,000 Erase/Write cycles.

As all o ther ST16 f am ily m emb ers, it is fully com ­patible with the ISO standards for Smartcard ap­plications.

Software development and firmware (ROM code,
options) generation are completed b y the ST16­19HDS development system.

The ST16CF54 Level B can be delivered either as
unsawn or sawn wafers, 180 or 275 micron thick­ness as well as in micromodule package.

Fi

g

ure 1 Block Diagram

SCP 096a/DS

MEMORY ACCESS CONTROL MATRIX

8 BIT

CPU

512

BYTES

SERIAL I/0's
INTERFACE

DATA

REGISTER

INTERNAL BUS

RAM

SECT. ASECT.

B

SECTOR

A

SECTOR

B

8K BYTES

SYSTEM

ROM
CRYPTO
LIBRARY

V GENERATION

EEPROM 4K BYTES

SECTORS COMBINATIVE

I/O2 I/O1

CONTROL
REGISTER

SECURITY

LOGIC

WITH

NUMBER

GENERATOR

32/256/288/384/416/

RST

GND

VCC.

CLK

16K BYTES
USER ROM

SRAC

512 BIT MAP

PP