SGS Thomson Microelectronics ST10F167-DS Datasheet
1/61July 1999
■ HIGH PERFORMANCE CPU
– 16-BIT CPU WITH 4-STAGE PIPELINE.
– 16-BIT CPU WITH 4 STAGEPIPELINE
– 100NS INSTRUCTION CYCLE TIME AT 20MHz
CPU CLOCK
– 500NS MULTIPLICATION (16*16 BIT)
–1µS DIVISION(32/16 BIT)
– ENHANCED BOOLEAN BIT MANIPULATION
FACILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLECONTEXTSWITCHINGSUPPORT
■ MEMORY ORGANIZATION
– 2K BYTE ON-CHIP INTERNAL RAM
– 2K BYTE ON-CHIP EXTENSION RAM
– 128K BYTE ON-CHIP FLASH MEMORY
–FLASHWITH4 INDEPENDENTLYERASABLEBANKS
■ FAST AND FLEXIBLE BUS
– PROGRAMMABLEEXTERNALBUSCHARACTER-
ISTICSFOR DIFFERENTADDRESS RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS.
– MULTIPLEXED OR DE-MULTIPLEXED EXTER-
NAL ADDRESS/DATA BUSES
– FIVEPROGRAMMABLECHIP-SELECTSIGNALS.
– HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-
TRATION SUPPORT
■ FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
■ ON-CHIP CAN 2.0B INTERFACE
■ ON-CHIP BOOTSTRAP LOADER
■ INTERRUPT
– 8-CHANNEL PEC FOR SINGLE CYCLE, INTER-
RUPT DRIVEN DATA TRANSFER
– 16-PRIORITY-LEVELINTERRUPTSYSTEM WITH
56 SOURCES, SAMPLE-RATE DOWN TO 50ns
■ TIMERS
– TWOMULTI-FUNCTIONALGENERAL-PURPOSE
TIMER UNITS WITH 5 TIMERS
– TWO 16-BIT CAPTURE/COMPARE UNITS
■ A/D CONVERTER
– 16-CHANNEL 10-BIT 9.7µS CONVERSION TIME
■ CLOCK GENERATION
– ON-CHIP PLL.
– DIRECT CLOCK INPUT
■ UP TO 111GENERAL PURPOSE I/O LINES
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
■ IDLE AND POWER DOWN MODES
– IDLE CURRENT <70mA
– POWER DOWN SUPPLY CURRENT <100µA.
■ 4-CHANNEL PWM UNIT
■ SERIAL CHANNELS
– SYNCHRONOUS/ASYNCH SERIAL CHANNEL.
– HIGH SPEED SYNCHRONOUS CHANNEL
■ ELECTRICAL CHARACTERISTICS
– POWER - 5V ± 10%
■ DEVELOPMENT SUPPORT
– C-COMPILERS,MACRO-ASSEMBLERPACKAGES,
EMULATORS, EVALUATION BOARDS, HLL-DEBUGGERS,SIMULATORS, LOGICANALYZERDISASSEMBLERS, PROGRAMMINGBOARDS
■ PACKAGE OPTION
– 144-PIN PQFP PACKAGE
PQFP144 (28 x 28 mm)
(Plastic Quad Flat Pack)
P.0
P.1P.4
P.6
P.5
P.3
P.2
GPT2/GPT1
ASC usart
BRG
CPU-Core
Internal
RAM
Wdog
Interrupt Controller
PEC
CAN
P.7 P.8
EBC
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
OSC.
XRAM
FLASH
128Kbyte
ST10F167
16-BIT MCU WITH 128KBYTE FLASH MEMORY
This is advance information on a new product now in development or undergoing evaluation. Details are subject tochange without notice.
ST10F167
2/61
TABLE OF CONTENTS Page
I INTRODUCTION......................................................................................................... 4
II PIN DATA.................................................................................................................... 5
III FUNCTIONAL DESCRIPTION.................................................................................... 10
IV MEMORY ORGANIZATION........................................................................................ 11
V FLASH MEMORY ................................................................................... .................... 12
V.1 FLASH PROGRAMMING AND ERASING .................................................................. 12
V.2 FLASH CONTROL REGISTER (FCR)........................................................................ 12
V.2.1 Flash memory security ................................................................................................ 14
VI EXTERNAL BUS CONTROLLER............................................................................... 16
VII CENTRAL PROCESSING UNIT (CPU)...................................................................... 17
VIII INTERRUPT SYSTEM ................................................................................................ 18
IX CAPTURE/COMPARE (CAPCOM) UNITS................................................................ . 21
X GENERAL PURPOSE TIMER (GPT) UNIT................................................................ 22
X.1 GPT1 ........................................................................................................................... 22
X.2 GPT2 ........................................................................................................................... 22
XI PWM MODULE ................ ........................................................................................... 25
XII PARALLEL PORTS.................................................................................................... 26
XIII A/D CONVERTER...................................... ................................................................. 26
XIV SERIAL CHANNELS .............................................................................. .................... 27
XIV.1 ASCO .......................................................................................................................... 27
XIV.2 HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC)...................................... 27
XV CAN MODULE............................................................................................................ 28
XVI WATCHDOG TIMER................................................................................................... 28
XVII INSTRUCTION SET.................................................................................................... 29
XVIII BOOTSTRAP LOADER............................. ................................................................. 30
XIX SPECIAL FUNCTION REGISTERS............................................................................ 31
XX ELECTRICAL CHARACTERISTICS ......................................................................... . 37
XX.1 ABSOLUTE MAXIMUM RATINGS.............................................................................. 37
XX.2 PARAMETER INTERPRETATION.............................................................................. 37
XX.3 DC CHARACTERISTICS............................................................................................ 37
ST10F167
3/61
TABLE OF CONTENTS (continued) Page
XX.4 A/D CONVERTER CHARACTERISTICS.................................................................... 39
XX.5 AC CHARACTERISTICS............................................................................................. 40
XX.5.1 Test waveforms ........................................................................................................... 40
XX.5.2 Definition of internal timing .......................................................................................... 41
XX.5.3 Direct Drive................................................................................................................. . 41
XX.5.4 Phase locked loop...................................... ................................................................. 41
XX.5.5 External clock drive XTAL1 ........................................................................................ . 42
XX.5.6 Memory cycle variables............................................................................................... 43
XX.5.7 Multiplexed Bus ............................................................. .............................................. 43
XX.5.8 Demultiplexed Bus....................................................................................................... 49
XX.5.9 CLKOUT and READY.............................................................................. .................... 55
XX.5.10 External Bus Arbitration............................................................................................... 57
XXI PACKAGE MECHANICAL DATA ................................ .............................................. 59
XXII ORDERING INFORMATION....................................................................................... 60
XXIII REVISION HISTORY .................................................................................................. 60
ST10F167
4/61
I - INTRODUCTION
The ST10F167 is a derivative of the STMicroelectronics 16-bit single-chip CMOS microcontrollers. It combines high CPU performance with
high peripheral functionality and enhanced I/O
capabilities. It also provideson-chip high-speed
RAM and clock generation via PLL.
Figure 1 : Logic symbol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA
READY
ALE
RD
WR/WRL
Port5
16-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
16-bit
Port 1
16-bit
Port 0
16-bit
V
DD
V
SS
ST10F167
Port 7
8-bit
Port8
8-bit
V
AREF
V
AGND
V
PP
This is advance information on a new product now in development or undergoing evaluation. Details are subject tochange without notice.
ST10F167
5/61
II - PIN DATA
Figure 2 : Pin out
ST10F167
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.6/CC22IO
P8.7/CC23IO
V
DD
V
SS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P8.5/CC21IO
V
PP
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.1/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
V
SS
V
DD
P4.7/A23
P4.6/A22/CAN_TXD
P4.5/A21/CAN_RXD
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
V
SS
V
DD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
V
AREF
V
AGND
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
V
SS
V
DD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
V
SS
V
DD
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
V
SS
V
DD
VSSNMI
VDDRSTOUT
RSTIN
VSSXTAL1
XTAL2
V
DD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSSVDDP1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
VSSV
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
ST10F167
6/61
Table 1 : Pin list
Symbol Pin Type Function
P6.0 –P6.7 1 - 8 I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output viadirection bits. For a pin configured as input, the output
driver is put into high-impedance state. Port 6 outputs can be configured
as push/pull or open drain drivers. The following Port 6 pins also serve for
alternate functions:
1
...
5
6
7
8
O
...
O
I
O
O
P6.0 CS0 Chip Select 0 Output
... ... ...
P6.4 CS4 Chip Select 4 Output
P6.5 HOLD External Master Hold Request Input
P6.6 HLDA Hold Acknowledge Output
P6.7 BREQ Bus Request Output
P8.0 –P8.7 9 - 16 I/O Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output viadirection bits. For a pin configured as input, the output
driver is put into high-impedance state. Port 8 outputs can be configured
as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
9
...
16
I/O
...
I/O
P8.0 CC16IO CAPCOM2: CC16 Capture In/Compare Out
... ... ...
P8.7 CC23IO CAPCOM2: CC23 Capture In/Compare Out
P7.0 –P7.7 19 -26 I/O Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output viadirection bits. For a pin configured as input, the output
driver is put into high-impedance state. Port 7 outputs can be configured
as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
19
...
22
23
...
26
O
...
O
I/O
...
I/O
P7.0 POUT0 PWM Channel 0 Output
... ... ...
P7.3 POUT3 PWM Channel 3 Output
P7.4 CC28IO CAPCOM2: CC28 Capture In/Compare Out
... ... ...
P7.7 CC31IO CAPCOM2: CC31 Capture In/Compare Out
P5.0 –P5.15 27-36
39-44
I
I
Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The
pins of Port 5 also serve as the (up to 16) analog input channels for the A/
D converter, where P5.x equals ANx (Analog input channel x), or they
serve as timer inputs:
39
40
41
42
43
44
I
I
I
I
I
I
P5.10 T6EUD GPT2 Timer T6Ext.Up/Down Control Input
P5.11 T5EUD GPT2 Timer T5Ext.Up/Down Control Input
P5.12 T6IN GPT2 Timer T6 Count Input
P5.13 T5IN GPT2 Timer T5 Count Input
P5.14 T4EUD GPT1 Timer T4Ext.Up/Down Control Input
P5.15 T2EUD GPT1 Timer T2Ext.Up/Down Control Input
II - PIN DATA (continued)
ST10F167
7/61
P2.0 –P2.15 47-54
57-64
I/O Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for
input or output viadirection bits. For a pin configured as input, the output
driver is put into high-impedance state. Port 2 outputs can be configured
as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
47
...
54
57
...
64
I/O
...
I/O
I/O
I
...
I/O
I
I
P2.0 CC0IO CAPCOM: CC0 Capture In/Compare Out
... ... ...
P2.7 CC7IO CAPCOM: CC7 Capture In/Compare Out
P2.8 CC8IO CAPCOM: CC8 Capture In/Compare Out
EX0IN Fast External Interrupt 0 Input
... ... ...
P2.15 CC15IO CAPCOM: CC15 Capture In/Compare Out
EX7IN Fast External Interrupt 7 Input
T7IN CAPCOM2 Timer T7 Count Input
P3.0- P3.13,
P3.15
65-70,
73-0,
81
I/O
I/O
I/O
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port 3 outputs
can be configured as push/pull or open drain drivers. The input threshold
of Port 3 is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
65
66
67
68
69
70
73
74
75
76
77
78
79
80
81
I
O
I
O
I
I
I
I
I/O
I/O
I/O
O
O
I/O
O
P3.0 T0IN CAPCOM Timer T0 Count Input
P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 T3EUD GPT1 Timer T3 External Up/Down Control Input
P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture
P3.8 MRST SSC Master-Receive/Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Receive O/I
P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE Ext. Memory High Byte Enable Signal,
WRH Ext. Memory High Byte Write Strobe
P3.13 SCLK SSC Master Clock Output/Slave Clock Input
P3.15 CLKOUT System Clock Output (=CPU Clock)
P4.0 –P4.7 85-92 I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for
input or output viadirection bits. For a pin configured as input, the output
driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines :
85
90
91
92
O
O
I
O
O
O
P4.0 A16 Least Significant Segment Address Line
P4.5 A21 Segment Address Line
CAN_RxD CAN Receive Data Input
P4.6 A22 Segment Address Line, CAN_TxD
CAN Transmit Data Output
P4.7 A23 Most Significant Segment Address Line
RD 95 O External Memory Read Strobe. RD is activated for every external instruc-
tion or data read access.
Table 1 : Pin list (continued)
Symbol Pin Type Function
II - PIN DATA (continued)
ST10F167
8/61
WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated for every
external data write access. In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for every data write access on
an 8-bit bus. See WRCFG in register SYSCON for mode selection.
READY/READY 97 I Ready Input. The active level is programmable. When the Ready function
is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until
the pin returns to the selected active level.
ALE 98 O Address Latch Enable Output. Can be used for latching the address into
external memory or an address latch in the multiplexed busmodes.
EA 99 I External Access Enable pin. A low level at this pin during and after Reset
forces the ST10F167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory.
PORT0:
P0L.0-P0L.7,
P0H.0-P0H.7
100-107,
108,
111-117
I/O Port 0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is
bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In
case of an external bus configuration, Port 0 serves as the address (A)
and address/data (AD) bus in multiplexed bus modes and as the data (D)
bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width : 8-bit 16-bit
P0L.0 – P0L.7 : D0 – D7 D0 - D7
P0H.0 – P0H.7 : I/O D8 - D15
Multiplexed bus modes:
Data Path Width : 8-bit 16-bit
P0L.0 – P0L.7 : AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 : A8 - A15 AD8 - AD15
PORT1:
P1L.0-P1L.7,
P1H.0-P1H.7
118-125,
128-135
I/O Port 1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is
bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 1
is used as the 16-bit address bus (A) in demultiplexed bus modes and
also after switching from a demultiplexed bus mode to a multiplexed bus
mode.
The following PORT1 pins also serve for alternate functions:
132
133
134
135
I
I
I
I
P1H.4 CC24IO CAPCOM2: CC24 Capture Input
P1H.5 CC25IO CAPCOM2: CC25 Capture Input
P1H.6 CC26IO CAPCOM2: CC26 Capture Input
P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 138 I Input to the oscillator amplifier and input to the internal clock generator
XTAL2 137 O Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while leaving
XTAL2 unconnected. Minimum and maximum high/low and rise/fall times
specified in the AC Characteristics must be observed.
RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F167.
An internal pullup resistor permits power-on reset using only a capacitor
connected toV
SS
.
In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
Table 1 : Pin list (continued)
Symbol Pin Type Function
II - PIN DATA (continued)
ST10F167
9/61
RSTOUT 141 O Internal Reset Indication Output. This pin is set to a low level when the
part is executing either a hardware-, a software- or a watchdog-timer
reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes
the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in
SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F167 to go into
power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
V
AREF
37 - Reference voltage for the A/D converter.
V
AGND
38 - Reference ground for the A/D converter.
V
PP
/RPD 84 - Flash programming voltage (ST10F167 ONLY).
This pin accepts the programming voltage for ST10F167 derivatives with
on-chip Flash memory.
It is used also as the timing pin for the return from powerdown circuit and
power-up asynchronous reset.
V
DD
17, 46,
56, 72,
82, 93,
109, 126,
136, 144
- Digital Supply Voltage:
= + 5 V during normal operation and idle mode.
> + 2.5 V during power down mode
V
SS
18, 45,
55, 71,
83, 94,
110, 127,
139, 143
- Digital Ground.
Table 1 : Pin list (continued)
Symbol Pin Type Function
II - PIN DATA (continued)
ST10F167
10/61
III - FUNCTIONAL DESCRIPTION
The architecture of the ST10F167 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem.
The following block diagram gives an overview of
the different on-chip components and the high
bandwidth internal bus structure of the ST10F167.
Figure 3 : Block diagram
Port 0
Port 1Port 4
Port 6
Port 5
Port 3
Port 2
GPT1
GPT2
ASC usart
BRG
Internal
FLASH
Memory
CPU-Core
Internal
RAM
Watchdog
Interrupt Controller
32
16
PEC
16
16
CAN
Port 7
Port 8
External Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
OSC.
XRAM
16
Controller
16
8
16
16
16
8
15 8 8
16
ST10F167
11/61
IV - MEMORY ORGANIZATION
The memory space of the ST10F167 is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are organized within the same linear address space of
16M Byte. The entire memory space can be
accessed Bytewise or Wordwise. Particular portions of the on-chip memory have additionally
been made directly bit addressable.
The ST10F167 provides 128K Byte of on-chip
flash memory.
2K Byte of on-chip Internal RAM stores user
defined variables for the system stack, general
purpose register banks and even for code. A register bank can consist of up to 16 Wordwide (R0 to
R15) and/or Bytewide (RL0, RH0, …, RL7, RH7)
so-called General Purpose Registers (GPRs).
1024 Byte (2 * 512 Byte) of the address space are
reserved for the Special Function Register areas
(SFR space and ESFR space). SFRs are Wordwide registers which are used for controlling and
monitoring functions of the differenton-chip units.
Unused SFR addresses are reserved for other/
future members of the ST10 family.
2K Byte of on-chip Extension RAM (XRAM) are
provided to store user data, user stacks or code.
The XRAM is accessed like external memory and
cannot be used for the system stack or register
banks, and is not bit-addressable. The XRAM
allows 16-bit accesses with maximum speed.
In order to meet the needs of designs where more
memory is requiredthan is provided on chip, up to
16M Byte of external RAM and/or ROM can be
connected to the microcontroller.
ST10F167
12/61
V - FLASH MEMORY
The ST10F167 provides 128K Byte of on-chip,
electrically erasable and re-programmable Flash
EPROM. The flash memory is organized in 32 bit
wide blocks. Double Word instructions can be
fetched in one machine cycle. The flash memory
can be used for both code and data storage. It is
organised into four banks of sizes 8K, 24K, 48K
and 48KByte. Each of these banks can be erased
independently. This prevents unnecessary re-programming of the whole flash memory when only
partial re-programming is required.
The first 32K Byte of the FLASH memory are
located in segment 0 (0h to 007FFFh) during reset,
and include the reset and interrupt vectors. The
rest of theFLASH memory is mapped in segments
1 and 2 (018000h to 02FFFFh). For flexibility, the
first 32K Byte of the FLASH memory may be
remapped to segment 1 (010000h to 017FFFh)
during initialization. This allows the interrupt vectors to be programmed from the external memory,
while retaining the common routines and constants
that are programmed into the FLASH memory.
V.1- Flash programming and erasing
The FLASH memory is programmed using the
PRESTO F Program Write algorithm. Erasure of
the FLASH memory is performed in the program
mode using the PRESTO F Erase algorithm.
Timing of the Write/Erase cycles is automatically
generated by a programmable timer and completion is indicated by a flag. A second flag indicates
that the VPPvoltage was correct for the whole pro-
gramming cycle. This guarantees that a good
write/erase operation has been carried out.
V.2 - Flash Control Register (FCR)
In the standard operationmode, the FLASH memory can be accessed in the sameway as the normal mask-programmable on-chip ROM. All
appropriate direct and indirect addressing modes
can be used forreading theFLASH memory.
All programming or erase operations are controlled via a 16-bit register, the FCR. The FCR is
not an SFR or GPR. To prevent inadvertent writing
to the FLASH memory, the FCR is locked and
inactive during the standard operation mode. The
FLASH memory writing mode must be entered
before a valid access to the FCR is provided. This
is done via a special key code instruction
sequence.
The FCR is virtually mapped into the active
address space of the Flash memory. It can only be
accessed with direct 16-bit (mem) addressing
modes. Since the FCR is neither byte, nor
bit-addressable, only word operand instructions
can be used for FCR accesses. By default, the
FCR can be accessed with any even address from
000000h to 07FFFEh and 018000h to 02FFFEh.
If thefirst 32K byte Block of the FLASH memory is
mapped to segment 1, the corresponding even
FCR addresses are 010000h to 017FFEh. Note
that DPP referencing and DPP contents must be
considered for FCR accesses. If an FCR access is
attempted via an odd address, an illegal operand
access hardware trap will occur.
FCR Flash Control Register: Reset Condition:
0000h (Read).
Table 2 : Flash memory bank addresses
Bank Addresses (Segment 0)
Size
(Byte)
0
1
2
3
000000h to 07FFFh
and 018000h to 01BFFFh
01C000h to 027FFFh
028000h to 02DFFFh
02E000h to 02FFFFh
48K
48K
24K
8K
Table 3 : Flash Parameters
Parameter Units Min Typical Max
Word
Programming
Time
µsec 12.8 12.8 1250
Bank Erasing
Time
sec 0.5 30
Endurance cycles 1000
Flash V
PP
volts 11.4 12.6
ST10F167
13/61
V - FLASH MEMORY (continued)
Table 4 : Flash control register bit definition
Bit number & name Description
b15 = FWMSET
Flash Writing Mode Set.
This bit is set to ”1” automatically once the Flash writing mode is entered. To exit from the
Flash writing mode, FWMSET must be set to ”0”. Since only word values can be written to
FCR, care must be taken that FWMSET is not cleared inadvertently. Therefore, for any
command written to FCR (except for the return to the Flash standard mode), FWMSET
must be set to ”1”. Reset condition of FWMSET is ”0”.
b14-b10 These bits are reserved for future development, they must be written to ”0”.
b9-b8 = BE0,1
Bank erase select.
Select the Flash memory bank to be erased. The physical addresses of bank 0 depends on
the which Flash memory map has been chosen. In Flash operating modes, other than the
erasing mode, these bits are not significant. At reset BE1,0 are set to ”00”.
b7 = WDWW
Word/double word write.
Determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit
(WDWW = ”1”). In Flash operation modes, other than the programming mode, this bit is not
significant. At reset, WDWWis set to “0”.
b6-b5 = CKCTL0,1
Flash Timer Clock Con-
trol.
Control the width (TPRG) of the programming or erase pulses applied to the Flash memory
cells during the operation. TPRG varies in an inverse ratio to the clock frequency. To avoid
putting the Flash memory under critical stress conditions, the width of one single program-
ming or erase pulse and the programming or erase time, must not exceed defined values.
Thus the maximum number of programming or erase attempts, depends on the system
clock frequency. RESET state: 00.
b4 = VPPRIV
VPPRevelation bit.
Read-only bit reflects the state of the VPPvoltage in the Flash writing mode. If VPPRIV is
set to ”0”, this indicates that V
PP
is below the threshold necessary for reliable programming.
The normal reaction to this indication is to check the V
PP
power supply and to then repeat
the intended operation. If the V
PP
voltage is above a sufficient margin, VPPRIV will be set to
”1”. The reset state of the VPPRIV bit depends on the state of the external V
PP
voltage at
the V
PP
pin.
b3 = FCVPP
Flash V
PP
control bit.
Read-only bit indicates that the V
PP
voltage fell below the valid threshold value during a
Flash programming or erase operation. If FCVPP is set to ”1” after such an operation has
finished, it can mean that the operation was not successful. The V
PP
power supply should
be checked and the operation repeated. If FCVPP is set to ”0”, no critical discontinuity in
V
PP
occurred. At reset FCVPP is set to ”0”.
b2 = FBUSY
Flash busy bit.
Read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY
is set to ”1” by hardware, as soon as the programming or erase command is given. At reset
FBUSY is set to ”0”. Note that this bit position is also occupied by the write-only bit RPROT.
b2 = RPROT
Protection enable bit.
This bit set at ’1’, and ed with the OTP protection bit, disables any access to the Flash, by
instructions fetched from the external memory space, or from the internal RAM. This
write-only bit, is only significant if the general Flash memory protection is enabled. If the
protection is enabled, the setting of RPROT determines whether the Flash protection is
active (RPROT=”1”) or inactive (RPROT=”0”). RPROT is the only FCR bit which can be
modified even in the Flash standard operation mode, but only by an instruction executed
from the Flash memory itself. At reset, RPROT is set to ”1”. Note that this bit position is also
occupied by the read-only bit FBUSY.
b1 = FEE
Flash erase/program
selection.
Selects the Flash write operation to be performed: erase (FEE=”1”) or programming
(FEE=”0”). Together with bits FWE and FWMSET,bit FEE determined the operation mode
of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash
operation mode to be selected but does not launch the execution of the selected operation.
If bit FWE was set to ”0”, the setting of FEE is insignificant. At reset, FEE is set to ”0”.
b0 = FWE
Flash write/read enable.
This bit determines whether FLASH write operations are enabled (FWE=1) or disabled
(FWE=0). By definition, a FLASH write operation can be either programming or erasure.
Together with bits FEE and FWMSET,bit FWE determines the operation mode of the Flash
memory. Note that setting bits FWE and FEE causes the corresponding Flash operation
mode to be selected but does not launch the execution of the selected operation. If bit FWE
was set to ”1”, any read access on a Flash memory location means a particular pro-
gram-verify or erase-verify read operation. Flash write operations are disabled at reset.
ST10F167
14/61
V.2.1- Flash memory security
Security and reliability have been enhanced by
built-in features: a key code sequence is used to
enter the Write/Erase mode preventing false write
cycles, a programmable option (set by the programming board) prevents access to the FLASH
memory from the internal RAM or from External
Memory. If the security option is set, the FLASH
memory can only be accessed from a program
within the FLASH memory area.
This protection can only be disabled by instructions executed from the FLASH memory.
Figure 4 : PRESTO F write algorithm
=0
PCOUNT=PNmax?
PCOUNT=PCOUNT+1
VR02057A
V - FLASH MEMORY (continued)
ST10F167
15/61
Figure 5 : PRESTO F erase algorithm
=0
PCOUNT=ENmax?
PCOUNT=PCOUNT+1
VR02057B
V - FLASH MEMORY (continued)
ST10F167
16/61
VI - EXTERNAL BUS CONTROLLER
All of the external memory accesses are performed by the on-chip External Bus Controller
(EBC). It can be programmed either to single chip
mode when no external memory is required, or to
one of four different external memory access
modes:
– 16-/18-/20-/24-bit Addresses, 16-bit Data,
Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data,
Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data,
Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data,
Demultiplexed
In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both
addresses and data use PORT0 for input/output.
Important timing characteristics of the external
bus interface (Memory Cycle Time, Memory
Tri-State Time, Length of ALE and Read/Write
Delay) have been made programmable. This
gives the choice of a wide range of external of
memories and external peripherals. In addition,
different address ranges may be accessed with
different bus characteristics. Up to 5 external CS
signals (4 windows plus default) can be generated
in orderto save external glue logic. Access to very
slow memories is supported via a particular
‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.
For applications which require less than 16M Byte
of external memory space, this address space
can be restricted to 1M Byte, 256K Byte or to
64K Byte. In this case Port 4 outputs four, two or
no address lines. If an address space of 16M Byte
is used, it outputs all8 address lines.
ST10F167
17/61
VII - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU). Dedicated
SFRs have been added for a separate multiply
and divide unit, a bit-mask generator and a barrel
shifter.
Most of the ST10F167’s instructions can be executed in one instruction cycle which requires
100ns at 20MHz CPU clock. For example, shift
and rotate instructions are always processed in
one machine cycle independent of the number of
bits to be shifted. All multiple-cycle instructions
have been optimized for speed: branches in 2
cycles, a 16 X 16 bit multiplicationin 5 cycles and
a 32-/16 bit division in 10 cycles. The ‘Jump
Cache’ pipeline optimization, reduces the execution time of repeatedly performed jumps in a loop,
from 2 cycles to 1 cycle.
The CPU includes an actual register context. This
consists of up to 16 Wordwide GPRs which are
physically allocated within the on-chip RAM area.
A Context Pointer (CP) register determines the
base address of the active register bank to be
accessed by the CPU at a time. The number of
register banks is only restricted by the available
internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 2048 Byte is provided as a
storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and
STKUN, are implicitly compared against the stack
pointer value upon each stack access for the
detection of a stack overflow or underflow.
Figure 6 : CPU Block Diagram
32
Internal
RAM
2K Byte
General
Purpose
Registers
R0
R15
MDH
MLD
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
CP
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs
Code Seg. Ptr.
CPU
256K Byte
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
ST10F167
18/61
VIII - INTERRUPT SYSTEM
With an interrupt response time from 250ns to
600ns (in the case of internal program execution),
the ST10F167 reacts quickly to the occurrence of
non-deterministic events
The architecture of the ST10F167 supports
several mechanisms for fast and flexible response
to service requests that can be generated from
various sources internal or external to the
microcontroller. Any of these interrupt requests
can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event
Controller (PEC).
In a standard interrupt service, programexecution
is suspended and a branch to the interrupt vector
table is performed. For a PEC service, just one
cycle is ‘stolen’ from the current CPU activity. A
PEC service is a single byte or word data transfer
between any two memory locations with an additional increment of either the PEC source or the
destination pointer. An individual PEC transfer
counter is decremented for each PEC service,
except for the continuous transfer mode. When
this counter reaches zero, a standard interrupt is
performed to the corresponding source related
vector location. PEC services are suited to, for
example, the transmission or reception of blocks
of data. The ST10F167 has 8 PEC channels,
each of which offers fast interrupt-driven data
transfer capabilities.
A separate control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield, exists for each of the
possible interrupt sources. Via its related register,
each source can be programmedto oneof sixteen
interrupt priority levels. Once having been
accepted by the CPU, an interrupt service can
only be interrupted by a higher prioritized service
request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs, feature
programmable edge detection (rising edge, falling
edge or both edges).
Software interruptsare supportedby means of the
‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Table 5 shows all the available ST10F167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers.
Table 5 : List of interrupt sources
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
ST10F167
19/61
Note Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes where no X-Peripherals are
connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
CAN Interface XP0IR XP0IE XP0INT 00’0100h 40h
X-Peripheral Node XP1IR XP1IE XP1INT 00’0104h 41h
X-Peripheral Node XP2IR XP2IE XP2INT 00’0108h 42h
PLL Unlock XP3IR XP3IE XP3INT 00’010Ch 43h
Table 5 : List of interrupt sources
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
VIII - INTERRUPT SYSTEM (continued)
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