SGS Thomson Microelectronics ST10F163-DS Datasheet
1/58April 1999
■ HIGH PERFORMANCE CPU
– HIGH PERFORMANCE 16-BIT CPU WITH
4-STAGE PIPELINE
– 80nsINSTRUCTION CYCLE TIME@ 25MHzCPU
CLOCK
– 400ns MULTIPLICATION (16 × 16 BITS)
– 800ns DIVISION (32 / 16 BIT)
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORTHLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
■ MEMORY ORGANIZATION
– UP TO 16 MBYTES LINEAR ADDRESS SPACE
FOR CODE AND DATA (1MBYTE WITH SSP
USED)
– 1 KBYTES ON-CHIP RAM
– 128KBYTES ON-CHIP FLASH MEMORY
– 4 INDEPENDENTLY ERASABLE BANKS OF
FLASH
■ FAST AND FLEXIBLE BUS
– PROGRAMMABLE EBC
– 8-BIT OR16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS/DATA BUSES
– FIVEPROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-
TRATION SUPPORT
■ ON-CHIP BOOTSTRAP LOADER
■ FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
■ INTERRUPT
– 8-CHANNEL INTERRUPT-DRIVEN SINGLE-CY-
CLE DATA TRANSFER FACILITIES VIA PERIPH-
ERAL EVENT CONTROLLER (PEC)
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM
WITH 20 SOURCES, SAMPLE-RATE DOWN TO
40ns
■ TIMERS
– TWOGENERAL PURPOSE TIMERUNITS WITH5
TIMERS
■ CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT
■ UP TO 77 GENERAL PURPOSE I/O LINES
■ IDLE AND POWER DOWN MODES
■ SERIAL CHANNELS
– SYNCHRONOUS/ASYNCHRONOUS
– HIGH-SPEEDSYNCHRONOUSSERIALPORTSSP
■ DEVELOPMENT SUPPORT
– C-COMPILERS, MACRO-ASSEMBLER PACKAG-
ES, EMULATORS, EVALUATION BOARDS,
HLL-DEBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEMBLERS, PROGRAMMING
BOARDS
■ PACKAGE
– 100-PIN THIN QUAD FLATPACK (TQFP)
PQFP100 (14 x 14 mm)
(Plastic Quad Flat Pack)
P.0
P.1
P.4
P.6
P.5
P.3 P.2
SSP
BRG
GPT1&2
ASC
BRG
FLASH
CPU
RAM
Watchdog
InterruptController
PEC
PLL
EBC
ST10F163
16-BIT MCU WITH 128KBYTE FLASH MEMORY
This is advance information on a new product now in development or undergoing evaluation. Details are subject tochange without notice.
ST10F163
2/58
I INTRODUCTION ........................................................................................................ 4
II PIN DATA ............................................................................................................. 5
III FUNCTIONAL DESCRIPTION ................................................................................... 9
IV MEMORY ORGANIZATION ....................................................................................... 10
V FLASH MEMORY ...................................................................................................... 10
V.1 PROGRAMMING/ERASING WITH ST EMBEDDED ALGORITHMKERNEL ............ 11
V.1.1 Return values ............................................................................................................. 13
V.1.2 Programming examples .............................................................................................. 13
V.2 FLASH MEMORY CONFIGURATION......................................................................... 14
V.3 FLASH PROTECTION ............................... ................................................................. 14
VI EXTERNAL BUS CONTROLLER .............................................................................. 15
VI.1 PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................. 15
VII CENTRAL PROCESSING UNIT (CPU) ..................................................................... 17
VIII INTERRUPT SYSTEM ............................................................................................... 18
IX GENERAL PURPOSE TIMER (GPT) UNIT ........................................... .................... 20
IX.1 GPT1 ........................................................................................................................... 20
IX.2 GPT2 ........................................................................................................................... 20
X PARALLEL PORTS ............................................................................... .................... 23
XI SERIAL CHANNELS ................................................................................................. 23
XII WATCHDOG TIMER .................................................................................................. 25
XIII OSCILLATOR WATCHDOG (OWD) ......................................................................... 25
XIV INSTRUCTION SET SUMMARY ................................. .............................................. 26
XV SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 28
XVI ELECTRICAL CHARACTERISTICS ......................................................................... 31
XVI.1 ABSOLUTE MAXIMUM RATINGS.............................................................................. 31
XVI.2 PARAMETER INTERPRETATION.............................................................................. 31
XVI.3 DC CHARACTERISTICS ............................................................................................ 31
XVI.4 AC CHARACTERISTICS............................................................................................. 33
XVI.4.1 Test waveforms .......................................................................................................... 33
XVI.4.2 Definition of internal timing ......................................................................................... 34
XVI.4.3 Clock generation modes ............................................................................................. 34
XVI.4.4 Prescaler operation .................................................................................................... 35
XVI.4.5 Direct drive ................................................................................................................. 35
XVI.4.6 Oscillator Watchdog (OWD) ................................................................... .................... 35
TABLE OF CONTENTS Page
ST10F163
3/58
XVI.4.7 Phase locked loop ...................................................................................................... 35
XVI.4.8 Memory cycle variables .............................................................................................. 36
XVI.4.9 External clock drive XTAL1 .......................................... .............................................. 37
XVI.4.10 Multiplexed bus ...................................................................................... ....................38
XVI.4.11 Demultiplexed bus ...................................................................................................... 44
XVI.4.12 CLKOUT and READY ................................................................................................ 50
XVI.4.13 External bus arbitration ........................................................................... .................... 52
XVI.4.14 Synchronous serial port timing ................................................................................... 54
XVII PACKAGE MECHANICAL DATA ........................................................................... 56
XVIII ORDERING INFORMATION ...................................................................................... 56
XIX REVISION HISTORY ................................ ................................................................. 57
ST10F163
4/58
I - INTRODUCTION
The ST10F163 is a Flash derivative of the
STMicroelectronics ST10 family of 16-bit microcontrollers. It combines high CPU performance
(up to 12.5 million instructions per second) with
high peripheral functionality and enhanced
IO-capabilities. 128KBytes of an electrically erasable and re-programmable Flash EPROM is provided on-chip.
Figure 1 : Logic symbol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA
READY
ALE
RD
WR/WRL
Port 5
6-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
8-bit
Port 1
16-bit
Port 0
16-bit
V
DD
V
SS
ST10F163
ST10F163
5/58
II - PIN DATA
Figure 2 : TQFP pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 2728 2930 3132 3334 35 36 37 3839 40 4142 4344 4546 47484950
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10099 9897 969594939291 90898887 8685848382818079787776
P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
V
SS
XTAL1
XTAL2
V
DD
P3.0
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8
P3.9
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
V
SS
V
DD
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
P5.12/T6IN
P5.11/T5EUD
P5.10/T6EUD
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
VDDV
SS
P1H.7/A15
P4.3/A19
V
SS
V
DD
P4.4/A20/SSPCE1
P4.5/A21/SSPCE0
P4.6/A22/SSPDAT
P4.7/A23/SSPCLK
RD
WR/WRL
READY
ALE
EA
V
DD
VSSV
PP
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
V
DD
V
SS
ST10F163
ST10F163
6/58
Table 1 : Pin definitions and functions
Symbol
Pin
Number(
TQFP)
Input (I)
Output
(O)
Function
P5.10 – P5.15 98-100
1- 3
I
I
6-bit input-only port with Schmitt-Trigger characteristics.
Port 5 pins alsoserve as timer inputs:
98 I P5.10 T6EUD GPT2 TimerT6 Ext.Up/Down Ctrl.Input
99 I P5.11 T5EUD GPT2 TimerT5 Ext.Up/Down Ctrl.Input
100 I P5.12 T6IN GPT2 Timer T6 Count Input
1 I P5.13 T5IN GPT2 TimerT5 Count Input
2 I P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
3 I P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input
XTAL1 5 I XTAL1:Input to the oscillator amplifier and input to the internal clock generator
XTAL2 6 O XTAL2:Output of the oscillator amplifier circuit.
Toclock the device from an external source, drive XTAL1, while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in
the AC Characteristics must be observed.
P3.0 – P3.13,
P3.15
8- 21
22
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input
or output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state. Port 3 outputs can be configured as push/pull or
open drain drivers. The following Port 3 pins have alternate functions:
9 O P3.1 T6OUT GPT2 TimerT6 ToggleLatch Output
10 I P3.2 CAPIN GPT2 Register CAPREL Capture Input
11 IO P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
12 I P3.4 T3EUD GPT1 TimerT3 Ext.Up/Down Ctrl.Input
13 I P3.5 T4IN GPT1 TimerT4 Input for Count/Gate/Reload/Capture
14 I P3.6 T3IN GPT1 TimerT3 Count/Gate Input
15 I P3.7 T2IN GPT1 TimerT2 Input for Count/Gate/Reload/Capture
18 O P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.)
19 I/O P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.)
20 O P3.12 BHE Ext. Memory High Byte Enable Signal,
O WRH Ext. Memory High ByteWrite Strobe
22 O P3.15 CLKOUT System Clock Output (=CPU Clock)
ST10F163
7/58
P4.0 – P4.7 23-26
29-32
I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direc-
tion bits. For a pin configured as input, the output driver is put into high-impedance state. For external bus configuration, Port 4 can be used to output the
segment address lines:
23 O P4.0 A16 Least Significant Segment Addr.Line
... ... ... ... ...
26 O P4.3 A19 Segment Address Line
29 O P4.4 A20 Segment Address Line
O SSPCE1 SSP Chip Enable Line 1
30 O P4.5 A21 Segment Address Line
O SSPCE0 SSP Chip Enable Line 0
31 O P4.6 A22 Segment Address Line
I/O SSPDAT SSP Data Input/Output Line
32 O P4.7 A23 Most Significant Segment Addr. Line
O SSPCLK SSP Clock Output Line
RD 33 O External Memory Read Strobe. RD is activated for every external instruction or
data read access.
WR/WRL 34 O External Memory Write Strobe. In WR-mode this pin is activated for every
external data write access. In WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
READY 35 I Ready Input. When the READY function is enabled, a high level at this pin dur-
ing an external memory access will force the insertion of memory cycle time
waitstates until the pin returns to a low level.
ALE 36 O Address Latch Enable Output. Can be used for latching the address into exter-
nal memory or an address latch in the multiplexed bus modes.
EA 37 I External Access Enable pin. A low level at this pin during and after Reset forces
the device to begin instruction execution out of external memory. A high level
forces execution out of theinternal flash EPROM.
PORT0:
P0L.0-P0L.7
P0H.0-P0H.7
41-48
51-58
I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input
or output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and
address/data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Table 1 : Pin definitions and functions(continued)
Symbol
Pin
Number(
TQFP)
Input (I)
Output
(O)
Function
Demultiplexed bus modes
Data Path Width:
8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15
ST10F163
8/58
PORT1:
P1L.0-P1L.7
P1H.0-P1H.7
59-66
67, 68
71-76
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input
or output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state. PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus
mode to a multiplexed bus mode.
RSTIN 79 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a
specified duration while the oscillator is running resets the device. An internal
pullup resistor permits power-on reset using only a capacitor connected to
V
SS
.
RSTOUT 80 O Internal Reset Indication Output. This pin is set to a low level when the part is
executing either a hardware-, a software- or a watchdog timer reset. RSTOUT
remains low until the EINIT (end of initialization) instruction is executed.
NMI 81 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the
CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10R65 to go
into power down mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P6.0-P6.7 82-89 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direc-
tion bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can beconfigured as push/pull oropen drain drivers.
The following Port 6 pins have alternate functions:
82 O P6.0 CS0 Chip Select 0 Output
... ... ... ... ...
86 O P6.4 CS4 Chip Select 4 Output
87 I P6.5 HOLD External Master Hold Request Input
(Master mode: O, Slave mode: I)
88 I/O P6.6 HLDA Hold Acknowledge Output
89 O P6.7 BREQ Bus Request Output
P2.8 –P2.15 90 - 97 I/O Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state. Port 2 outputs can be configured as push/pull or
open drain drivers.
The following Port 2 pins also serve for alternate functions:
90 I P2.8 EX0IN Fast External Interrupt 0 Input
... ... ... ... ...
97 I P2.15 EX7IN Fast External Interrupt 7 Input
V
PP
40 - Flash programming voltage. This pin accepts the programming voltage for the
on-chip flash EPROM. In the ST10F163, bit 4of SYSCON register serves as an
enable/disable control for the OWD.
V
DD
7, 28,38,
49, 69,
78
- Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
> 2.5 Vduring power down mode
V
SS
4, 27,39,
50, 70,
77
- Digital Ground.
Table 1 : Pin definitions and functions(continued)
Symbol
Pin
Number(
TQFP)
Input (I)
Output
(O)
Function
ST10F163
9/58
III - FUNCTIONAL DESCRIPTION
The architecture of the ST10F163 combines the
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The fol-
lowing block diagram gives anoverview of the different on-chip components and of the advanced,
high bandwidth internal busstructure.
Figure 3 : Block diagram
OSC.
Port 0
Port 1Port 4
Port 6
Port 5
Port 3
Port 2
Ext.
Bus
Controller
SSP
BRG
GPT1
T2
T3
T4
GPT2
T5
T6
ASC
(usart)
BRG
Internal
FLASH
Memory
CPU-Core
Internal
RAM
Watchdog
Interrupt Controller
16
16
8
8
8
156
32
16
PEC
16
16
16
16
PLL
ST10F163
10/58
IV - MEMORY ORGANIZATION
The memory spaceof the ST10F163is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are organized within the same linear address space which
includes 16 MBytes. The entire memory space
can be accessed bytewise or wordwise. Particular
portions of the on-chip memory have additionally
been made directly bit addressable.
1 KByte of on-chip RAM is provided as a storage
for user defined variables, for the system stack,
general purposeregister banks and even forcode.
A register bank can consist of up to 16 wordwide
(R0 to R15) and/or bytewide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
1024 bytes (2 * 512 bytes) of the address space
are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are
wordwide registers which are used for controlling
and monitoring functions of the different on-chip
units. Unused SFR addresses are reserved for
other/future members of the ST10 family.
In order to meet the needs of system designs
where more memory is required than is provided
on chip, up to 16 MBytes of external RAM and/or
ROM can be connected to themicrocontroller.
V - FLASH MEMORY
The ST10F163 provides 128KBytes of on-chip,
electrically erasable and re-programmable Flash
EPROM. The flash memory is organized in 32 bit
wide blocks. This allows double word instructions
to be fetched in one machine cycle. The flash
memory can be used for both code and data storage. The flash memory is organized into four
banks of sizes 8K, 24K, 48K and 48Kbytes (table
2). Each of these banks can be erased indepen-
dently. This prevents unnecessary erasing of the
whole flash memory whenonly a partial erasing is
required (see Table 2).
Typicaltiming characteristics give 80µs forword or
double word programming and 800 ms for block
erasing, at 25mhz systemclock. the flashmemory
has a typicalendurance of 1000 erasing/programming cycles. the flash memory can be programmed, eitherin a programming board, or inthe
target system. the code to program or erase the
flash memory is executed from an external memory or from theon-chip ram, but not fromthe flash
memory itself. as a flexible and cost-saving alternative, the on-chip bootstrap loader may be used
to load and start the programmingcode.
the following considerations must be taken into
account forprogramming orerasing ‘on-line’in the
target system:
– While operationsare in progress, theflash mem-
ory can not be accessed as usual, no branch
can be made to the flash memory and no data
reads can be taken from the flash memory.
– If the two first blocks (8KB + 24KB) of the flash
memory are mapped to segment 0, no interrupt
or hardware trap must occur during programming or erasing, as this would require a ‘forbidden’ branch to the flashmemory.
A flash memory protection option, whenactivated,
prevents view access to the contents of the ROM
and the on-chip RAM, code operation from within
the flash memory continuesas normal. During the
initialization phase, thefirst two blocks of the flash
memory (8KB + 24KB) can be mapped to segment 0 (addresses 00000h to 07FFFh), or to segment 1 (addresses 10000h to 17FFFh). This
makes itpossible touse external memory for additional system flexibility.
Table 2 : FLASH memory bank organisation
Bank Addresses (Segment 0) Addresses (Segment 1) Size (bytes)
0
1
2
3
000000h to 001FFFh
002000h to 007FFFh
018000h to 023FFFh
024000h to 02FFFFh
010000h to 011FFFh
012000h to 017FFFh
018000h to 023FFFh
024000h to 02FFFFh
8K
24K
48K
48K
ST10F163
11/58
V.1- Programming/erasing with ST Embedded
Algorithm Kernel
In order to secure flash programming and erasing
operations, and also to simplify the software
development for programming and erasing the
Flash, the ST10F163 Flash is programmed or
erased by executing a specific sequence of
instructions (called ‘Unlock Sequence’) with command and parameters loaded into GPRs. The
Unlock Sequence’ invokes embedded kernel routines that checks the validity of the parameters
provided by the user, and decodes the command
(programming or erasing) and executesit.
When performing a programming command, the
Embedded Algorithm Kernel automatically times
the program pulse widths (taking in account the
CPU periodprovided as a parameter by the user)
and verifies proper cell programming.
When performing an erasing command, the
Embedded Algorithm Kernel automatically
pre-programs the bank to be erased if it is not
already programmed. During erase, the Embedded Algorithm Kernel automatically times the
erase pulse widths (taking in account the CPU
period provided as a parameter by the user) and
verifies proper cell erasing.
To start a program/erase operation, the user’s
application must performan ‘Unlock Sequence’ to
trigger the flash ST Embedded Algorithms Kernel
(STEAK). Before using STEAK, proper parameters must be assigned through the R0-R4 registers. TheR0 registeris the command register. The
other registers handle the address and data to be
programmed or sector to be erased. Table 3
defines the command sequence. A definition of
the codes used inTable3 is given in Table 4.
Note The read status for registers R1 to R3 is not used except for the return values, refer to “Return values” on page 13
Table 3 : Command -parameters definition
COMMAND R0 R1 R2 R3 R4
Single word programming 55Ash AddOff W nu 2TCL
Double Word programming DD4sh AddOff DWL DWH 2TCL
Block programming AA5sh BegAddOff EndAddOff SourceAddr 2TCL
Sector Erasing EEEEh 5555h Bnk Bnk 2TCL
Read Status 7777h nu nu nu 2TCL
Table 4 : Code definition
Abbreviation Definition
s Segment of the target flash memory cell
AddOff Segment Offset of thetarget flash memory cell which must be even an value (word-aligned address).
W Data (word) to be written in flash.
DWL,DWH Data (double word, DHL = low word, DWH = high word to be written in Flash,
BegAddOff Segment Offset ofthe FIRST target flash memory word to be written in a multiple programming com-
mand. This value must be even (word-aligned address)
EndAddOff Segment Offset of the LAST Target Flash Memory word to be written in a Multiple programming
command.
Must be even value (word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <=
D < 16384 (ie. up to one page (16 KBytes) can be written in the flash with one multi-word programming command).
SourceAdd Start address for the source data (block) to be programmed. This address uses implicitly the data
paging mechanism of the CPU. SourceAdd value must respect the rules:
- SourceAdd + (EndAddOff - BegAddOff) <16384.
- Page 0 and 1 canNOT be used forsource data if SYSCON bitROMS1 = ‘1’
Note: source data can be located in flash (Inpages 0, 1, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = ‘0’, or in
pages 4, 5, 6, 7, 8, 9,10 or 11if bit ROMS1 = ‘1’.
Bnk Number of the Bank to be erased. Note that for security, R2 and R3 must hold the same value.
2TCL CPU clock period in nseconds (e.g. R4 = 40d means CPU frequency is 25MHz).
ST10F163
12/58
The Flash Unlock Sequence consists of two consecutive writes: the direct addressing mode and
the indirect addressing mode. The FCR must represent an even address in the active address
space of the flash memory. Rwn can be any
unused word GPR (R6 to R15), loaded with a
value that results in the same even address as for
FCR
For easier coding, the standard data paging
addressing schemeis overridden for the two MOV
instruction of the Flash Trigger Sequence (EXTS
instruction). This also locked both standard and
PEC interrupts and class A hardware traps. Must
be replace by ATOMICinstruction if standardDPP
addressing scheme must be preserved.
When the embedded programming/erasing algorithm returns to trigger point, information can be
collected through registerR0 so the user can take
specific actions. Table 5 lists all of the error codes
that can be returned in R0.
Note The Flash Embedded Presto Algorithms require at least 45 words on the Internal System Stack for proper operation. The program
verifies itself that there is enough free space on the System Stack before performing a programming or erasing operation (by
comparing SP value with STKOV+90d).
EXTS #1, #2 ; assumes flash is
mapped in seg 1
MOV FCR, R7 ; first part
MOV [R7], R7 ; second part
Table 5 : Error code definition
ERROR CODE MEANING
00h Operation was successful
01h ROMEN bit inside SYSCON is not set
02h Vpp voltage not present
03h Programming operation failed
04h Address value (R1) incorrect: not in Flash address area or odd
05h CPU period out of range (must be between 10 ns to 1000 ns)
06h Not enough free space on system stack for proper operation
07h Incorrect bank number (R2,R3) specified
08h Erase operation failed
09h Bad source address for multi-word programming command
0Ah Bad number of words to be copied in multi-word programming command: one
destination will be outof flash, or one source operand will be out of the source page
FFh Unknown or bad command
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V.1.1- Return values
After a single or double word programming command, R0 contains error code, R1 remains
unchanged, R2 will contain the data in Flash for
location Segment+Segment Offset (R0.[3:0] with
R1), R3 will contain the data in Flash for location
Segment+Segment Offset +2 (R0[3:0] withR1+2),
R4 to R15 remain unchanged.
After a multi-word programming command, R0
contains error code, R1 will contains the last segment offset address of the last written word in
flash (failing flash address if R0 is not equal to
zero), R2 and R3 are undefined, R4 to R15
remain unchanged.
After erasing command, only R4 to R15 remain
unchanged, R0 will contain error code, R1 to R3
are undefined.
After status read command, R0 contains error
code, R1 contains flash embedded revision, R2
and R3 contains circuit identifiers (R2 = #0787h
and R3 = #0101h for this device), R4 to R15
remain unchanged.
V.1.2- Programming examples
Programming a double word:
Note For easier coding, the standard data paging addressing scheme is overrides for the two MOV instruction of the Flash Trigger
Sequence (EXTS instruction).This also locked both standard and PEC interrupts and class A hardware traps. Must be replace by
ATOMIC instruction if standard DPP addressing scheme must be preserved.
Programming a block of data:
Address 01’9000h to 01’9FFEh (inclusive) is to be programmed. Source data (data to be copied into
flash) is located in external RAM from address 03’1000h (to 03’1FFEh, implicitly):
; code hereafter assumes that flash is mapped in segment 1
; i.e. bit ROMS1 = ‘1’ in SYSCON register
; Flash must also be enabled, i.e. bit ROMEN = ‘1’ in SYSCON.
MOV R0, #PROGDW ; DD4xh: Double word programming command
OR R0, #01h ; Selects segment 1 in flash memory
MOV R1, #00224h ; Address to be programmed is 01’0224h
MOV R2, #03456h ; Data to be programmed at 01’0224h
MOV R3, #04567h ; Data to be programmed at 01’0226h
MOV R4, #050d ; 50ns is 20 MHz CPU clock frequency
MOV R7, #08000h ; R7 used for Flash trigger sequence
#define FCR 08000h
; Flash Unlock Sequence: consists in two consecutive writes, with the direct
addressing mode and then the indirect addressing mode. FCR must represent an
even address in the active address space of the Flash memory, and Rwn can be
any unused word GPR (R6 to R15)loaded with a value resulting in the same even
address than FCR
EXTS #1, #2 ; flash can be mapped in segment 0 or 1
MOV FCR, R7 ; first part
MOV [R7], R7 ; second part
NOP ; WARNING: place 2 NOP operations after
NOP ; the Unlock sequence to avoid all possible
; pipeline conflict in STEAK programs
; code hereafter assumes that flash is mapped in segment 1
; i.e. bit ROMS1 = ‘1’ in SYSCON register
; Flash must also be enabled, i.e. bit ROMEN = ‘1’ in SYSCON.
MOV R0, #PROGMW ; AA5xh: Multi word programming command
OR R0, #01h ; Selects segment 1 in flash memory
ST10F163
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V.2- Flash memory configuration
The default memory configuration is determined
by the state of the EA pin at reset. This value is
stored in the Internal ROM enable bit: ROMEN of
the SYSCON Register.
When ROMEN=0, the internal ROM is disabled
and externalROM is used for start-up control.The
first 32KBytes of the flash memory area must be
re-mapped to segment 1, to enabletheir later use.
This is done by setting the ROMS1 bit of
SYSCON to 0. This is done by the externally supplied program, before the execution of the EINIT
instruction.
If program execution startsfrom external memory,
but access to the flash memory (re-mapped to
Bank 1) is required later, one of the following values has to be written to the SYSCON register,
before the end of initialization:
– If flash is to be mapped to segment 1:
xxx100xxxxxxxxxxb
(ROMS1=1,SGTDIS=0)
– If flash is to be mapped to segment 0:
xxx000xxxxxxxxxxb
(ROMS1=0,SGTDIS=0)
All other parts of the flash memory (addresses
18000h - 1FFFFh) remain unaffected.
The SGTDIS Segmentation Disable/Enable must
be set to 0 so that the 64KBytes of on-chip memory can be used in addition to the external boot
memory. The correct procedure for changing the
segmentation registers must be observed, to prevent unwanted trap conditions:
– Instructions that configure the internal memory
must only be executed from external memory
or from the internal RAM.
– Whenever the internalmemory is disabled,ena-
bled or re-mapped, the DPPs must be explicitly
(re)loaded to enable correct data accesses to
the internal memory and/or externalmemory.
V.3 - Flash protection
The flash protection mode, prevents the reading
of data operands in the flashmemory by anything
but a program executed from the flash memory
itself. Flash protection mode permits program
branches from, or into the flash memory, but does
not permit erasing and programming of the flash
memory.
Flash protection is controlled by the Protection
UPROM Programming Bit(UPROG). UPROG is a
’hidden’ one-time programmable bit. It is only
accessible in a special mode, entered, for example, via a flash EPROM programming board. If
UPROG is setto ‘1’,flash protection isactive after
reset. By default flash protection is disabled
(UPROG=0).
For deactivation of flash protection, where the
flash memory has to be reprogrammed with
updated program/variables, a zero value must be
written at every even address in the active
address spaceof the flash memory.This write can
only be done by an instruction executed from the
internal flash memory itself, e.g. MOV
FLASH,ZEROS.
MOV R1, #09000h ; First Flash Segment Offset Address
MOV R2, #09FFEh ; Last Flash Segment Offset Address
MOV R3, #01000h ; Source data address: use DPP2 as
; data page pointer
SCXT DPP2,#0Ch ; Source is in page 12 (0Ch): save previous
; DPP2 value and load it with source page
; number
MOV R4, #050d ; 50ns is 20 MHz CPU clock frequency
MOV R7, #08000h ; R7 used for Flash trigger sequence
#define FCR 08000h
EXTS #1, #2 ; flash can be mapped in segment 0 or 1
MOV FCR, R7 ; first part
MOV [R7], R7 ; second part
NOP ; WARNING: place 2 NOP operations after
NOP ; the Unlock sequence to avoid all possible
; pipeline conflict in STEAK programs
POP DPP2 ; restore DPP2
ST10F163
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VI - EXTERNAL BUS CONTROLLER
All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to
Single Chip Mode when no external memory is
required, or to one of four different external memory access modes:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, De-
multiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multi-
plexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multi-
plexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, De-
multiplexed
In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0 or P0L, respectively. In the multiplexed
bus modes both addresses and data use PORT0
for input/output.
Important timing characteristics of the external
bus interface (Memory Cycle Time, Memory
Tri-State Time, Length of ALE and Read Write
Delay) have been made programmable. This
gives the choice of a wide range of different types
of memories and external peripherals. In addition,
up to 4 independent address windows may be
defined (via register pairs ADDRSELx / BUSCONx).
This gives access to different resources with different bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1.
All accesses to locations not covered by these 4
address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus
default) canbe generated in order tosave external
glue logic. Access to very slow memories is supported via a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration so that external resources can be shared
with other bus masters. The bus arbitration is
enabled by setting bit HLDEN in register
SYSCON. After setting HLDEN once, pins
P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In Master Mode
(default after reset) the HLDA pin is an output.
By setting bit DP6.7 to’1’ the Slave Mode is
selected where pin HLDA is switched to input.
This allows to directly connect the slave controller
to another master controller withoutglue logic.
For applications which require less than 16
MBytes of external memory space, this address
space can be restricted to 1 MByte, 256 KByte or
to 64 KByte. In this case Port 4 outputs four, two
or no address lines at all. If an address space of
16 MBytes is used,it outputs all 8 address lines.
Note When the on-chip SSP Module is to be used the segment
address output on Port 4 must be limited to 4 bits (i.e.
A19...A16) in order to enable the alternate function of the
SSP interface pins.
VI.1 - Programmable chip select timing control
The position of the CSx lines can be changed by
setting theCSCFG bit inthe SYSCON register. By
default the CSx lines change half a CPU clock
cycle after the rising edge of ALE (20ns @ f
CPU
=
25 MHz). With the CSCFG bit set (section
Figure VII -
), the CSx lines change with the rising
edge of ALE. In this case, the CSx lines and
address lines change at the same time.
ST10F163
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Figure 4 : Chip selectdelay
Delay
Normal CSx
RD
Address (P1)
ALE
Segment (P4)
NormalDemulti plexed
Bus Cycle
ALE Lengthen Demultiplexed
BusCycle
Unlatched CSx
WR
Data Data
Data
BUS(P0)
BUS(P0)
Read/Write
Delay
Read/Write
Data
ST10F163
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VII - CENTRAL PROCESSING UNIT (CPU)
The main core of the CPU consists of a 4-stage
instruction pipeline, a 16-bit arithmetic and logic
unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and
divide unit, a bit-mask generator and a barrel
shifter.
Based on these hardware provisions, most of the
ST10F163’s instructions can be executed in one
machine cycle. This requires 80ns at 25MHz CPU
clock. For example, shift and rotate instructions
are always processed in one machine cycle independent of the number of bits to be shifted. All
multiple-cycle instructions have been optimized
for speed: branches in 2 cycles,a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. The ‘Jump Cache’ pipeline optimization, reduces the execution time of repeatedly performed jumps in aloop, from 2 cycles to 1 cycle.
The CPU includes an actual register context.This
consists of up to 16 wordwide GPRs physically
allocated in the on-chip RAM area. A Context
Pointer (CP) register determines the base
address ofthe activeregister bank to be accessed
by the CPU. The number of register banks is only
restricted by the available internal RAM space.
For easy parameter passing, one register bank
may overlap others.
A system stack ofup to 1024 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and
STKUN, are implicitly compared against the stack
pointer value upon each stack access for the
detection of a stack overflow or underflow.
The basic instruction length is either 2 or 4 bytes.
Possible operand typesare bits, bytes andwords.
A variety of direct, indirect or immediate addressing modes exist.
Figure 5 : CPU block diagram
16
16
32
ROM
Internal
RAM
1KByte
R15
R0
General
Purpose
Registers
R0
R15
MDH
MLD
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Context Ptr
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs Code Seg. Ptr.
CPU
128KBytes
FLASH
ST10F163
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VIII - INTERRUPT SYSTEM
With an interrupt response time from 200 ns to
480ns (in the case of internal program execution),
the ST10F163 reacts quickly to the occurrence of
non-deterministic events.
The architecture of the ST10F163 supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be
programmed to being serviced by the Interrupt
Controller or by the Peripheral Event Controller
(PEC). In a standard interrupt service, program
execution is suspended and a branch to the interrupt vector table is performed. For a PEC service,
just one cycle is ‘stolen’ from the current CPU
activity. A PEC service is a single byte or word
data transfer between any two memory locations
with an additional increment of either the PEC
source or the destination pointer. An individual
PEC transfer counter is decremented for each
PEC service, except for the continuous transfer
mode. When this counter reaches zero, a standard interrupt is performed to the corresponding
source related vector location. PEC services are
suited to, for example, the transmission or reception of blocks of data. The ST10F163 has 8 PEC
channels, each of which offers fast interrupt-driven data transfer capabilities.
A separate control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield, exists for each of the
possible interrupt sources. Via its related register,
each source can be programmed to one ofsixteen
interrupt priority levels. Once having been
accepted by the CPU, an interrupt service can
only be interrupted by a higher prioritized service
request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs, feature
programmable edge detection (rising edge, falling
edge or both edges).
Software interruptsare supportedby means of the
‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Table 6 shows all of the possible ST10F163 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers:
Table 6 : List of possible interrupt sources, flags,vector and trap numbers
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
External Interrupt 0 CC8IR CC8IE CC8INT 00’0060h 18h
External Interrupt 1 CC9IR CC9IE CC9INT 00’0064h 19h
External Interrupt 2 CC10IR CC10IE CC10INT 00’0068h 1Ah
External Interrupt 3 CC11IR CC11IE CC11INT 00’006Ch 1Bh
External Interrupt 4 CC12IR CC12IE CC12INT 00’0070h 1Ch
External Interrupt 5 CC13IR CC13IE CC13INT 00’0074h 1Dh
External Interrupt 6 CC14IR CC14IE CC14INT 00’0078h 1Eh
External Interrupt 7 CC15IR CC15IE CC15INT 00’007Ch 1Fh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
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