SGS Thomson Microelectronics SERC816 Datasheet

SERCOS INTERFACE CONTROLLER

■ Single-chip controller for SERCOS interface

■ Real time communication for in dustrial control

systems

■ 8/16-bit bus interface, Intel and Motorola control

signals

■ Dual port RAM with 2048 word *16-bit

■ Data communications via optical fiber rings, RS

485 rings and RS 485 busses

■ Maximum transmission rate of 16 Mbaud with

internal clock recovery

■ Internal repeater for ring connections

■ Full duplex operation

■ Modulation of power of optical transmitter diode

■ Automatic transmission of synchronous and

data telegrams in the communication cycle

■ Flexible RAM configuration, communication

data stored in RAM (s ingle or doubl e buffer) or transfer via DMA

■ Synchronization by external signal

SERCON816

PQFP100

ORDERING NUMBERS: SERC816

SERC816/TR

■ Timing control signals

■ Automatic service channel transmission

■ Watchdog to monitor software and external

synchronization signals

■ Compatible mode to SERCON410B SERCOS

interface controller

■ 100-pin plastic flat-pack casing

Figure 1. SERCON816 Block Diagram

WRN D[15:0] A[15:0] BUSYN

ADMUX

BUSMO DE[ 1 : 0 ]

BUSWIDTH

BYTEDIR

SBAUD

SBAUD 1 6

TM0/1

ALE L

RDN

ALE H

bus interface

telegram-

processing

serial interface

RxC

TxC

RxD

TxD[6:1]

MCSN0/1

PC SN 0

BHEN

PCS1

DMA

timingcontrol

optical transmitter/

receiver or

RS-485 bus drive

inter-

rup t

clock

reset

watch-

dog

INT 0/1

SCLK SCLKO 2 / 4 MCLK RSTN

DMAR EQR/T DMAACKNR/

WDOGN

CYC_CLK CON_CLK DIV_CLK

L_ERRN REC A C TN IDLE

January 2003

1/23

SERCON816

TABLE OF CONTENTS

1 GENERAL DESCRIPTION.................................................................................................................3

2 Pin Description................................................................................................................................... 5

3 Electrical (DC and AC) Characteristics..............................................................................................7

3.1 Absolute Maximum Ratings .....................................................................................................7

3.2 Recommended Operating Conditions......................................................................................8

3.3 ELECTRICAL CHARACTERISTCS ........................................................................................ 8

3.4 Power Dissipation....................................................................................................................9

3.4.1 Power Dissipation Considerations....................................................................................9

3.5 AC Electrical Characteristics..................................................................................................10

3.5.1 Clock Input MCLK...........................................................................................................10

3.5.2 Clock Input SCLK...........................................................................................................11

3.5.3 Address Latch... .............. ....... .............. .............. ............... ....... .............. .............. ....... ....11

3.5.4 Read Acce ss of Control Registers.................................................................................. 12

3.5.5 Read Access of Dual Port RAM .............................................................. ..... ....... ....... ....13

3.5.6 Write Access to Control Registers..................................................................................14

3.5.7 Write Access to DUAL Port RAM...................................................................................15

4 Control Registers and RAM Data Structures....................................................................................16

4.1 Control Register Addresses...................................................................................................16

4.2 Data Structures within the RAM.............................................................................................16

4.2.1 Telegram Headers.............................................................. ....... .. .......... ....... .. .......... ......16

4.2.2 Data Containe r s.............. ....... .............. .............. ............... ....... .............. .............. ........ ...17

4.2.3 End Marker.....................................................................................................................18

4.2.4 Service Conta ine r s......... .............. ....... .............. ............... .............. ....... .............. ...........18

5 Additional Specifications, Tools and Suppo rt...................................................................................21

5.1 Additional Spec ifications ........................................................................................................21

5.2 Hardware and Software Components.................................................................. ....... ....... ....21

5.3 Tools........................................... ........................................................... ................... .............21

6 Package Mechanical Data:

SERCON816 100 Pin Plastic Quad Flat Pack Package (PQFP100) ........................................... ....22

2/23

SERCON816

1 GENERAL DESCRIPTION

The SERCOS interface controller SERCON816 is an integrated circuit for SERCOS interface communication systems. The SERCOS interface is a digital interface for communication between systems which have to exchange information cyclically at short, fixed intervals (62,5 s to 65 ms). It is appropriate for the synchronous operation of distributed control or test equipment (e.g. connection between drives and numeric control).

A SERCOS interface communication system consists of one master and several slaves. These units are connect ed by a fiber optical ring. This ring starts and ends at the maste r. T he slaves regenerate and repeat their received data or send their own telegrams. By this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves. The optical fiber assures a reliabl e hi gh-speed dat a t ransmissio n wi t h excellent noi s e i m m unity.

The SERC O S i nt erf ace contro l le r c ontains al l the hardware-relat ed f unctions of the SERCOS in te rface and considerably reduces the hardware costs and the computing time requirements of the microprocessor. It is the dire ct link betw een th e elect ro-op tical rece iver an d tran smit ter a nd the micr oproc essor that exec utes th e control algorithms. The SERCON816 can be used bo th for SERCOS interface masters and slaves.

The circuit contains the following functions (Fig. 1): – Interface to the microprocessor with a data bus width of 8 or 16 bits and with control lines according to

Intel or Motorola standards.

– A serial interface for making a direct c onnection with the opti cal rec eiver and tr ansmitter of the fi ber optic r ing

or with drivers to an elec tric ring or bus. Data and cl ock r egeneratio n, the repeater for ring to pologies and the serial transmitter and receiver are integrated. The signals are monitored and test signals generated. The serial interface operates up to 16 Mbaud without external circuitry.

– A dual port RAM (2048 * 16 bi t) for control and communication data. The organization of the memory is flexible. – Telegram processing for automatic transmission and monitoring of synchronous and data telegrams. Only

transmission data which is intended for the particular interface user is processed. The transmitted data is either stored in the internal RAM (single or double buffer) or transferred via direct memory access (DMA). The transmission of service channel information over several communication cycles is executed automatically.

In addition to the SERCOS interface the SERCON816 c an also be used for other real-time communications tasks. As an alternative to t he fiber optical ring also bus topologies with RS-485 signals are supported (Fig. 4). The SERCON816 is therefore suitable for a wide range of applications. Remark: The SERCON816 is based on the former SERCON410B SERCOS interface controller.

Figure 2. SERCON816 Pin Configuration

80 D12

D13

D14

D15

75 BHEN

VDD

VSS 81

D11 D10 D9

D8 85 VDD D7 D6 D5

D4 90 VSS D3 D2 D1

D0 95

ADMUX BUSMODE0 BUSMODE1 BUSWIDTH

BYTDIR 100

VDD 1

SCLK

VSS

MCLK

TEST

SCLK04 5

SCLK02

70 VSS

A10

65 VDD

SERCON816

VSS 15

TxD2

TxD3

RxC

VDD

NDTRO

RxD

OUTZ

TxC

RSTN 10

VDD

TxD1

A11

A12

A13

A14

60 VSS

TxD4 20

TxD5

TxD6

VSS

WRN

ALEH

A15

WDOGN

51 RDN

55 VDD

ALEL

50 VSS PCS1 PCSN0 MCSN1 MCSN0 45 BUSYN INT0

INT1 VSS

DMAACKTN 40 DMAACKRN DMAREQT DMAREQR VDD DIV_CLK

35 CON_CLK

CYC_CLK

VSS

L_ERRN

31 TM1

TM0 30

IDLE 25

VDD

RECACTN

SBAUD

SBAUD16

3/23

SERCON816

Figure 3. SERCON816 with Ring Connection (SERCOS interface)

µP

bus interface

SERC O N 8 1 6

master

fibre optical ring

TxDRxD

bus interface

µP

TxDRxD

bus interface

µP

slave 1 slave 2

Figure 4. SERCON816 with RS-485 bus connection

µP

bus interface

SERC ON8 1 6

IDLE

master

SERC O N 8 1 6SERCON816SERC O N 8 1 6

bus interface

µP

TxDRxD

sla ve n

4/23

IDLE IDLE IDLE

SERC ON8 1 6 SERC ON8 1 6 SERCON816

businterface businterface businterface

µP µP µP

sla ve 1 slave 2

SERCRING.CDR

slave n

SERCON816

2 PIN DESCRIPTION

Table 1. S E R CON816 I/O Port Func tion Su m m ary

Signal(s) Pin(s) IO Function

D15-0 77-80,

ALEL, ALEH 54, 53 I Address latch enable, low and high, active high: they are only used when

RDN 51 I Read: for the Intel bus interface, data is read when RDN is 0. For the Motorola

WRN 52 I Write: for the Intel bus interface, data is written to when WRN is 0. For the

BHEN 75 I Byte high enable, active low: in the 16-bit bus mode, data is transferred via

MCSN0,

MCSN1 PCSN0,

PCS1

BUSYN 45 O RAM busy, active low: becomes active if an access to an address of the dual

DMAREQR 38 O DMA request receive, active high: becomes active if data from the receive

DMAACKRN 40 I DMA acknowledge receive, active low: when DMAACKRN is 0, the receive

DMAREQT 39 O DMA request transmit, active high: becomes active when data can be written

DMAACKTN 41 I DMA acknowledge transmit, active low: when DMAACKTN is 0, the transmit

ADMUX 96 I Address data bus: when ADMUX is 0 A15-0 are the address inputs, when

BUSMODE0,

BUSMODE1

BUSWIDTH 99 I Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).

BYTEDIR 100 I Byte address sequence: when BYTEDIR is 0, A0 = 0 addresses the lower 8

INT0, INT1 44,43 O Interrupts, active low or active high. Interrupt sources and signal polarity are

SBAUD16 28 I Baud rate and SERCON410B compatible mode: SBAUD and SBAUD16

SBAUD 29 I Baud rate. Can be overwritten by the microprocessor.

82-85, 87-90,

92-95

46,47 I Memory chip select, active low: to access the internal RAM MCSN0 and

48,49 I Periphery chip select, active low (PCSN0) and active high (PCS1): to access

97,98 I Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read,

I/O

Data bus: for 8-bit-wide bus interfaces, data is wri 16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address which is stored in the address latch with ALEL and ALEH is input via D15-0.

ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to the address bus, when ALEL/ALEH = 0, they store the address. When ADMUX is 0, ALEL/ALEH have to be connected to VDD.

bus interface, data is read or written to when RDN is 0 (BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1).

Motorola bus interace, WRN selects read (WRN = 1) and write (WRN = 0) operations of the data bus.

D15-8 when BHEN is 0.

MCSN1 must be 0.

the control registers PCSN0 must equal 0 and PCS1 must equal 1.

port RAM is performed simultaneously to an access to the same memory location by the internal telegram processing.

FIFO can be read. At the beginning of the read operation of the last word of the receive FIFO, DMAREQR becomes inactive.

FIFO is read, independent of the levels on A6-1 and the chip select signals.

to the transmit FIFO. DMAREQT becomes inactive again at the beginning of the last write access to the transmit FIFO.

FIFO is written to when there is a bus write access independent of the levels on A6-1 and the chip select signals.

ADMUX is 1 A15-0 are the outputs of the address latch.

WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1).

bits of a word (low byte first), when BYTEDIR is 1, the upper 8 bits of a word are addressed (high byte first).

programmable.

selects the baud rate for the serial interface. If SBAUD16 is ‘1’ the SERCON410B compatible mode is selected.

tten to and read via D7-0, for

5/23

SERCON816

Table 1. S E R CON816 I/O Port Func tion Su m m ary (continued)

Signal(s) Pin(s) IO Function

RxD 14 I Receive data for the serial interface. RxC 12 O Receive clock for the serial interface. Output of the internally generated

RECACTN 26 O Receive active, active low. Indicates that the serial receiver is receiving a

TxD1 16 O Transmit data. The pin can be switched to a high impedance state.

TxD6-2 22,21,20,

18,17

TxC 13 O Transmit clock for the serial interface. Output for the internally generated

IDLE 25 O Transmitter active, active low. When transmitting own data IDLE is 0.