SGS Thomson Microelectronics SBPH400-3 Datasheet



IEEE1394 3-Port 400Mbps Physical Layer

■ FEATURES

■ 3 ports fully compliant with IEEE 1394-1995

cable environment specification

■

Fully implements IEEE P1394a D2.0 proposal

■ S100, S200 and S400 speeds

■ IEEE P1394a proposal PHY-LINK interface

■

IEEE P1394a proposal Suspend/Resume

■ OHCI support

■ Per port disable

■

Automatic power saving

■ Optional isolation support

■ IEEE P1394a proposal arbitration

enhancements

■

IEEE P1394a proposal register set and remote register read

■ Advanced Data-Strobe clock and data

recovery

■

Digital delay-lock loop technology - no filtering capacitors

■ Built-in self-test (BIST) of analog and digital

port logic

■

JTAG Test Access Port

■ 3.3V supply

■ 80 pin plastic TQFP package

■

APPLICATIONS

■ Host processor interface

■ Host processor adapter cards

■ Digital set-top box

■

Digital Video Recorder/ Player

■ Repeaters

SBPH400-3

P1394a Link interface

Link layer interface logic

Reset and

arbitration

Port

logic

1394 cable

interface

@400 Mbps

1394 cable

@400 Mbps

Built-in

self test

Port logic

interface

PRELIMINARY DATA

Port

logic

1394 cable

interface

@400 Mbps

16 March 1998 42 1697 05 The information in this datasheet is subject to change

Table of Contents

1Overview.............................................................. 4

2 Functional Description . . . . . . ..............................................6

2.1 Transmitter and receiver port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 6

2.2 Connect detect and bias . . . . . . . . . . . . . ...............................8

2.3 Configuration pins . . ............................................... 8

2.4 Suspend/Resume/Disable . . .........................................9

2.5 Data encoder/decoder . . ............................................9

2.6 Bus reset, arbitration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 PHY packets . . . . .. . . . . . . . . . . . . .................................. 11

2.7.1 Link device interaction . . . . . . . . . . . . . ...........................11

2.7.2 Self-ID packet . . . . ........................................... 11

2.7.3 Link_onpacket .............................................. 11

2.7.4 PHY configuration packet . . . . .................................. 12

2.7.5 Ping packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... 12

2.7.6 Remote Access and Reply . . . . . . . . . . . . . ........................13

2.7.7 Remote Command and Confirmation packets . . .. . . . . . . . . . . . . . . .... 14

2.8 Link interface . . . . . . . . . . . . . . . . . . .................................. 15

2.8.1 Overview ...................................................15

2.8.2 Types of operation . . . . . . . . . . . . . ..............................16

2.8.3 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... 16

2.8.4 Link device request (LREQ) . . .................................. 16

2.8.5 Busrequest................................................. 20

2.8.6 Register Read/Write requests . . . . ............................... 20

2.8.7 Status transfer . . . . ........................................... 21

2.8.8 Transmit ...................................................22

2.8.9 Receive . . . . ................................................24

2.8.10 SBPH400 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 25

2.9 Reset and initialization . . . . . . . . . . . . ................................. 28

2.9.1 Poweron................................................... 28

2.9.2 PHY/Link Interface start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.9.3 PHY/Link interface reset and disable . . . . . . . . . . . . . . . ..............30

2.9.4 LKON(linkon) .............................................. 32

2.10 ISO (isolation) ...................................................32

2.11 CPS (cable power status) . . ........................................32

3 Pin Description . . . . . . . . . . . . . . . . . . . . . ................................... 33

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Table of Contents

4 Electrical Specifications . . . . . .............................................35

4.1 Absolute maximum ratings . . . . . . . . . . . . .............................. 35

4.2 Operating conditions . . . . . . . . . . . . . ................................. 35

4.3 DC characteristics . . .............................................. 36

5 AC characteristics . . . . . . ................................................38

6 Package Specifications . . . . . ............................................. 40

7 Application Circuit . . . . . . . . . . ............................................ 42

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SBPH400-3

1 Overview

The SBPH400-3 provides the analog transceiver functions needed to implement a 3 port node in an IEEE 1394-1995 cable network. There are 2 differential line transceivers in each cable port. The following main functions are included in the chip:

• Detection of connection status using line condition detection circuitry.

• Node initialization and bus arbitration.

• Reception and Transmission of Data Strobe Bit Level encoded packets

• Interface to higher level protocol devices (Link layer).

• Production test through JTAG

The interface to the Link conforms to the IEEE 1394-1995 Annex J with 2 control lines and an 8 bit data bus, as modified by the P1394a proposals.

The basic chip timing may be controlled either from a 24.596 MHz crystal controlling an internal oscillator or from anexternal 24.596 MHz oscillator. The internal delay lock loop (DLL) generates the various internal clocks for the high speed serial data transmission and reception. Note that there is no need to provide filtering capacitors. The input clock is used to derive the 49.152 MHz clock for the interface to a Link layer device, which provides the data to be transmitted on the 8 bit Link data interface. The data from the Link layer device is latched internally in the chip at 49.152 MHz. The bits are serialized and encoded in the Data Strobe Bit Level Encoding format. The Data information is transmitted differentially on the TPBcable pair(s) while the Strobe information is transmitted differentially on the TPA cable pair(s). Data can be transmitted at 98.304 Mbit/s (S100 speed), 196.608 Mbit/s (S200 speed) or 393.216 Mbit/sec (S400 speed). When a packet is received by a port, the corresponding transmitters are disabled and the receivers enabled. The received encoded Data information from TPA cable pair and the encoded Strobe information from the TPBcable pair are decoded to extract the receive clock signal and the data bits. The data bits are converted into a parallel format and transmitted to the Link Layer controller and the other active cable ports after resynchronisation to the system clock.

Figure 1.1 is a block diagram of the SBPH400-3. The portion of circuit which is circled by the dash line is termed the Cable Media Interface are pure digital signals. The signals which are driven on and received from the cable are analog differential and common mode signals. The differential signals on the cable transmit data or arbitration states, while common mode signals indicate the cable connection status or transmission rate (speed).

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Cable Media Interface

. All signals between the Digital Circuit and the

SBPH400-3

Figure 1.1

D[0:7]

Ctl[0:1]

LReq

SClk

CPS

LPS

ISO

CMC

LKON

PC[0:2]

RESET#

LACT

PDISABLE

QX1

CLK24/QX0

TCK TRST# TMS TDI TDO

SBP H 400-3

LINK

Interface

I/O

Arbitration and

Control State Machine

TEST ACCESS PORT

block diagram

Data Encoder/ Decoder

Logic

JTAG

Cable Media Interface

Strb_Tx Data_Tx

Strb_Rx

Data_Rx

Speed_Tx

Strb_En

Data_En Arb_A_Rx

Arb_B_Rx Speed_Rx

Port_Status

...

Transmitter

Receiver

Port 1

(Driver/Receiver,

Arb. Comparator,

Port_Status,

Speed Monitor)

Port 2

(same as Port 1)

Port 3

(same as Port 1)

Bias

TPA1 TPA1#

TPB1 TPB1#

TPA2 TPA2#

TPB2 TPB2#

TPA3 TPA3#

TPB3 TPB3#

TPBias1 TPBias2 TPBias3

R0 R1

TESTMODE

TESTENABLE

SCI[2:0]

SCO[2:0]

BUILT-IN

SELF TEST

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SBPH400-3

2 Functional Description

2.1 Transmitter and receiver port interface

Figure 2.1 Analog port schematic

Twisted Pair A Twisted Pair B

Physical connection detection co mparat o r

Con

TpBias disable

Driver

Strb_Tx

Strb_Enable

Data_Rx

Arb_A_Rx A rbitr ation

S200 Speed_Rx

S400 Speed_ Rx

Receiver

Comparators

TpBias’

7kΩ

0.3 min

S200 Spee d_Tx

S400 Spee d_Tx

TPA

55Ω 55Ω

Ω 7kΩ 7kΩ

S200_ref

S400 _ref

TPA*

Da ta _Tx

Data_Enable

Strb_Rx

Arb_B_Rx

Bias

Arbitration

Com parator s

TpBias detection comparator

0.8V

Common mode speed signal current

55Ω 55Ω

Ω

±5%

(shared with T PA and otherports)

TPB

TPB*

250pF

The SBPH400-3 implements three cable interface transceiver ports. Each port operates independently from the other ports, under control of the device control logic. Each port provides two pairs of signals, denoted TPA, TPA#, and TPB, TPB#. Each signal is implemented using a driver and a receiver connected to a single pin (total of four pins per port). In various modes, the driver and receiver are enabled, either separately or both at the same time (for bi-directional signalling).

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SBPH400-3

A port may be disconnected, disabled, suspended or active. When active, each port operates in the following modes:

Idle mode: In this mode,each port’s driver is disabled, i.e. the port presents a high impedance on all four signals. The inputs are continuously sampled, and if a signal is detected (which will normally indicate an arbitration signal from a connected port) then this is passed to the arbitration logic.

Arbitration mode: In this mode, both pairs engage in bi-directional untimed digital signalling. Each pair transmits (under the control of the arbitration logic) either a logic 1 using differential signalling, a logic 0 using differential signalling, or high impedance Z. Simultaneously, the signal on each pair is continuously sampled, and is interpreted as a logic 1, logic 0 or high impedance Z. The sampled signal is a combination of the transmitted signal and the signal being transmitted on the corresponding pair by a connected transceiver (NB the cable implements a “twist” - TPA is connected to the far end TPB, and vice versa). The signal is interpreted using the 1394 1’s dominant rule and passed to the arbitration logic for interpretation by the arbitration state machine. If a 11 level is received then this is interpreted as a reset signal and passed to the control logic.

Speed signalling mode: Speed signalling uses common mode signalling. It is used to signal the transmission speed capabilitiesof the device (during the Self_ID phase of bus initialization) and in parallel with the transmission of Data_Prefix arbitration signal during arbitration to indicate the speed of the packet about to be transmitted. To send a speed signal, the port generates a common mode current signal on TPB and TPB# for 100 ns. This signal results in a drop ofthe current modebias voltage through apair of 55 Ohm resistors connected between the TpBias output and the TPA, TPA# pair at the receiving end. To receive a speed signal, the port determines the speed by measuring the amount of voltage drop on the TPA pair, compared to the TpBias signal it is generating. The port samples the speed signal at 20ns intervals in order to provide filtering against intermediate values or against noise. The SBPH400 requires two consecutive samples of a S200 or a S400 signal (as appropriate) in order to identify a valid speed signal. If no speed signal is identified when data transmission starts, then the data is assumed to be transmitted at S100 speed.

Data transmission mode: In this mode, which always follows arbitration mode, the port transmits the data and strobe signals received from the data encoder on the TPB pair and the TPA pair respectively. The transmission uses uni-directional differential data signalling on each pair. Note that at the end of arbitration mode, the port will be transmitting an untimed signal of 01. If the first bit to be transmitted is a zero, then this will cause a transition on “data” (i.e. TPB, so that TPA, TPB transmit 00), if the first bit to be transmitted is a 1, then this will cause a transition on “strobe” (i.e. TPA, so that TPA, TPB transmit 11). The receivers are disabled during data transmission. At the end of data transmission mode, the port reverts to idle mode.

Data reception mode: This mode always follows arbitration mode. The port presents high impedance on its output drivers (and ignores the data which is being repeated to the other ports by the data encoder/decoder). The port implements a differential receiver for each of TPA (data) and TPB (strobe) pairs, and passes the received binary signals to the data

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SBPH400-3

decoder. Advanced logic is used to ensure reception of the Data andStrobe signals at speeds of up to 400 MHz.

2.2 Connect detect and bias

A low current connect detect circuit is used to detect a physical connection. A current, applied to the TPA pair and sensed viaa localSchmitt trigger, will indicate a disconnected state unless there is a physical connection to ground via the 5K resistor connected to the TPB pair at the far end. Note that this does not require the far end to be powered. This mechanism operates only when the port is not generating TpBias.

In order to implement the cable detection, suspend/resume and speed signalling functions, a common mode bias voltage has to be provided to the TPA pair. A separate TpBias pin is provided for each port, which should be connected to the TPA pair via a pair of 55 Ohm resistors, as shown in Figure 2.1. The use of a separate pin for each port avoids problems of possible interference between the common mode signalling on each port, or possible misdetection of a disconnect.

A single external resistor should be provided between pins R0 and R1 in order to set the internal operating and the cable driver output currents. A low TCR 3KΩ ±1% resistor should be used.

2.3 Configuration pins

The SBPH400 provides six configuration pins which may be hard wired high or low, or may be directly controlled from a link layer device. Fourof thepins are used toinitialize registers which control configuration status bits in the self identification packet.

The PC[0:2] pins provide the power reset value for the power class register, which is reported in the Self_ID packet in the pwr field.

The CMC pin provides the power reset value for the C register, with is reported in the Self_ID packet in the C field to indicate if the node is a contender for the bus or isochronous resource manager.

The LACT pin is used to initialize the value of the Link_active register on power reset. If set to zero, this allows the node to appearas having an inactive link (the L field in the Self-ID packet will be zero) until application software sets the Link_active bit to 1.

The PDISABLE pin is used to initialize all ports as disabled on power reset. This satisfies the OHCI requirement, and allows software to be initialized before the device starts to participate on power-on as a new device on the bus.

The ISO pin is used onpower reset to determine the operating mode of the PHY/Link interface (DC coupled or using a DC isolation barrier).

The SBPH400 also has a number of pins which are intended for use during production test only, and are held to ground or V

as appropriate in normal operation.

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SBPH400-3

2.4 Suspend/Resume/Disable

Each port independently implements the P1394a suspend/resume proposal. At any one time, a port may be disconnected, disabled, suspended or active.

On power reset, if PDISABLE = 0 then all ports are initialized as disconnected, and then, if any ports are physically connected, the normal new connection actions taken. If PDISABLE = 1 then all ports are initialized as disabled.

When a port is not active, the TpBias output for the port is disabled, all outputs of the port are set to high impedance and any incoming arbitration signals on TPA and TPB are ignored.

A port may be disabled or re-enabled by a command (register write) from the local link, or by remote PHY command packet. While disabled, the port ignores any incoming TpBias signal but the port continues to monitor its connection status using the connect_detect mechanism. A change in connection status will cause an interrupt to the link or a LinkOn packet as appropriate and according to the controlling flags. When re-enabled and connected, the port is treated as suspended (see below).

When disconnected, a port ignores any incoming TpBias signal but continuously monitors the connection status using the connect detect circuitry. On connection, the port attempts to become active, but if an incoming TpBias is not then detected, then the port is suspended with the fault bit set.

While active, the port continuously senses the common-mode bias input voltage on the TPB pair. The presence of a bias voltage on the TPB pair indicates that the port is connected to an active port on some other device. Similarly, the absence of a bias voltage indicates the lack of such a connection or that the far end port has been powered off. On detection of loss of bias, the port is treated as suspended (see below)

A port may be suspended by a remote PHY command packet. In this case, it engages in a protocol with the remote connected port, resulting in that port too being suspended. It may be suspended on loss of incoming TpBias on an active port. A port may also be suspended as a result of its active connected port being suspended. A connected disabled port is treated as suspended when re-enabled.

While suspended, the port monitors both TpBias and its connection state using the connect_detect mechanism. If a disconnection is detected, then the port becomes disconnected. If a TpBias signal is detected, then the port resumes to its active state. A port may be instructed to resume by means of a remote command packet, in which case it generates a TpBias signal. This will indicate to the connected peer port that it too should resume.

It should be noted that any change of port state to or from the active state has the effect of a topology change, and that reconfiguration of the bus is necessary. To ensure that this occurs, the SBPH400 initiates the appropriate bus resets as defined in the P1394a proposal.

When a port becomes disconnected, disabled or suspended, it carries out the appropriate actions and then automatically enters a low power mode. Normal operation (on full power) is restored after an appropriate delay (to allow the internal clocks to stabilize) on any change in

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SBPH400-3

port state. If all ports are in a low power state, and the PHY/Link interface is disabled, then the SBPH400 implements the necessary delays to allow the SBPH400 core to enter a low power state in future versions with no functional or timing change.

2.5 Data encoder/decoder

The data encoder/decoder implements the SGS-Thomson patented “Data/Strobe” clock encoding technique, asdescribed inthe 1394 specification. Data to betransmitted isserialized and encoded into the appropriate Data and Strobe signals. These are send simultaneously to all active ports for outputting. Alloutput is clocked by the SBPH400 clock derived from thelocal crystal. Note that data to be transmitted may be received from an incoming port, or from the link interface.

Data received from a port (only at most one port can be receiving data at any one time) is resynchronized to the local clock using a small elastic buffer, as the clock frequency of the incoming data may differ (by up to 200 ppm) from the local clock. The buffer is sized to avoid underflow or overflow for the longest possible packet.The data is repeated to the ports and to the link layer as described above, using the local reference clock.

2.6 Bus reset, arbitration and control

The SBPH400 enters bus reset on power reset, if the reset signal is sensed onany connected port’s arbitration signal lines, on a request from a link layer device, on resume from suspend or on connection of detection on any port (possibly after a delay, to allow for an incoming reset), on loss of TpBias on an active parent port, on entry to suspend as a result of the peer port being suspended or disabled, or if the device stays in any state other than Idle, Tree-ID start, Transmit or Receive for longer than 300 µsec. In some circumstances, the device will arbitrate for the bus before generating a reset signal, as defined in the P1394a proposal. This results in minimum disruption to high priority traffic.

On entry to reset, the arbitration control logic enters a Tree-ID phase. Either the node will be identified an isolated node, or the node will be identified as the root, and all active ports willbe identified as child ports, or one active port will be the port to the node’s parent, and the other active ports will be identified as child ports.

The control logic will then engage in Self-ID, in which all nodes are allocated a node-ID and exchange self-ID packets (see 2.7.2). All received self-ID packets are passed to the link layer device. Speed capabilities are exchanged during the Self-ID process with all connected active nodes.

In normal operation, the control logic implements the functions of the root, should the result of the Tree-ID process be that this node becomes the root.

The control logic accepts arbitration requests from either the local link or any port. Upon receipt of an arbitration request, the request is accepted locally (if the node is the root) or repeated towards the root node via the parent port. Data Prefix (01) is transmitted on all other ports, which indicates that any arbitration request from these ports is rejected.

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SBPH400-3

If the request for transmit comes from the local link, then the arbitration control logic waits for an appropriate gap (all interfaces Idle), and then (unless the request is an immediate request) arbitrates as above.

The arbitration logic supports all the arbitration enhancements specified in IEEE P1394a:-

• arbitrated reset (a short reset which is delayed until a subaction gap arbitration)

• ack-accelerated arbitration (immediate arbitration after an ACK)

• fly-by arbitration (concatenation of packets after a packet received from a child

port)

2.7 PHY packets

2.7.1 Link device interaction

The SBPH400 will forward to the link (if the PHY/Link interface is active) every PHY packet received on the bus.

The SBPH400 will interpret every PHY packet which it receives from the local link device for transmission on the bus (in addition to responding to every PHY packet received from thebus). The SBPH400 will acton it in exactly the same way as if the packet was received from the bus.

2.7.2 Self-ID packet

The Self-ID packet has the following format:

Figure 2.2 Self-ID packet format

1 0 phy_ID 0 L gap_cnt sp c pwr p0 p1 p2 i 0

rsv

logical inverse of first quadlet

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SBPH400-3

The fields in the Self-ID packet are derived as shown in Table 2.1.

Table 2.1 Self ID packet fields

Field Derived from Comment

phy_ID self-ID process or

set_PHY_ID packet L Link enabled register Logical AND of LPS signal and the Link_active register gap_cnt Gap_Count register current value of Gap Count register sp Max_Phy_Speed 10b (S100, S200 and S400 capable) rsv (reserved) 00b c Contender register current value of C register pwr Power class register current value of Power class register p0, p1 p2 port status forport 0, 1and

2 respectively

i initiated reset set whenever the node initiated the current bus reset

physical node identifier

01 - not active (disabled, disconnected or suspended) 10 - active and connected to parent node 11 - active and connected to child node

2.7.3 Link_on packet

The SBPH400 will respond to a Link_on packet addressed to it received on the bus. The packet has the following format:

Figure 2.3 Link_on packet format

0 1 phy_ID

0000 0000 0000 0000 0000 0000

logical inverse of first quadlet

If the logical AND of the LPS pin and the Link_active bit is zero, then the SBPH400 will generate a 6.144 MHz signal on the LKON pin, until this logical value becomes 1. Otherwise the packet is forwarded to the local link. Note that all Link_on packets received on the bus are forwarded to the local link if it is active, whether or not the packets are addressed to the local node.

2.7.4 PHY configuration packet

The SBPH400 will respond to every PHY configuration packet which it receives on the bus, or from the link device for transmission on the bus. The packet has the format shown in Figure

2.4:

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Figure 2.4 PHY configuration packet format

SBPH400-3

0 0 root_ID

R 0000 0000 0000 0000T gap_cnt

logical inverse of first quadlet

The fields in the PHY configuration packet are interpreted as shown in Table 2.2.

Table 2.2 PHY configuration packet fields

Field Definition Comment

root_ID physical ID the physical node identifier of the node to become root on next reset R set root The Force_Root bit in the SBPH400 is set if R=1 and root_ID = the

node_ID of this node

T set gap count If T=1, then the value of the gap countregister inthe SBPH400 is set

to gap_cnt.

gap_cnt Gap_Count value new value of Gap Count register

Note that either or both of R and T must be set to 1.

2.7.5 Ping packet

The SBPH400 supports the useof ping timing.The pingpacket has the format shown in Figure

2.5:

Figure 2.5 Ping packet format

0 0 phy_ID

0 0000 0000 0000 0000000type (0)

logical inverse of first quadlet

When the SBPH400 receives a ping packet from the bus or from the local link addressed to the node, it responds immediately (without arbitration) with a Self_ID packet to both the bus and the local link.

2.7.6 Remote Access and Reply

The SBPH supports remote access to its internal registers. On receipt of a remote access packet addressed to the node (either from the bus or from the local link), the SBPH400 will immediatelyrespond with theappropriate remote reply packet. The remote access packet and the reply packet are also forwarded to the local link.

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