SGS Thomson Microelectronics REVISION Datasheet
1/4February 2002
1 - DESCRIPTION
This errata sheet describes the functional and electrical problems known in the revision AB of the
ST10F280-AB engineering samples.
The ST10F280-AB engineering samples marked as EAB-xxxx are not completely tested in all electrical
and functional characteristics and should be used for functional evaluation only.
Test conditions for these engineering samples are:
– TA Room Temperature (25°C)
– Vcc 5.0V ±10%
– Fosc 40MHz, PLL disabled, direct drive (f
CPU
= 40MHz)
2 - FUNCTIONAL PROBLEMS
The following malfunctions are known in this step:
2.1 - PWRDN.1 - Execution of PWRDN Instruction
When instruction PWRDN is executed while pin NMI
is at a high level (if PWRDCFG bit is clear in
SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRDCFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the
PWRDN instruction is ignored.
However, under the conditions described b elow, the PWRDN instruction is not ignored, and no fur ther
instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state.
This problem only occurs in the following situations:
a) The instructions following the PWRDN instruction are located in an external memory, and a multi-
plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used.
Or
b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral
(XRAM,CAN), and the instructions following the PWRDN instruction are located in external memor y.
In this case, the problem occurs for any bus configuration.
Note: The on-chip peripherals are still working correctly, in particular the Watchdog Timer, i f not disabled,
resets the device upon an overflow. Interrupts and PEC transfers, however, cannot be processed. In case
NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered.
No problem occurs if the NMI
pin is low (if PWRDCFG = 0) or if all P2 pins used to exit from power-down
mode are at inactive leve l (if PWRDCFG = 1): the chip normally enters powerdown mode.
Workaround:
Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory
tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM.
ST10F 280-AB
16-Bit MCU with 512K Byte FLASH and 18K Byte RAM Memories
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ERRATA SHEET
ST10F280-AB
2/4
2.2 - MAC.9 - CoCMP Instruction Inverted Operands
The ST10 Family Programming Manual describes the Co CMP instruction as: subtracts a 40-bit signed
operand from th 40-bit accumulator content (acc - op2\op1), and updates the N, Z and C flags in the MSW
register, leaving the accumulator unchanged. O n the device the reverse operation (op2\op1 - acc) has
been implemented in the Mac Unit. Therefore, the N and C flags are set according to the reverse
operation (Z flag is not affected).
Workaround:
Change interpretation of the N and C flags in the MSW register.
Example:
MOV R12, #07h
MOV R13, #06h
MOV R14, #0
CoLOAD R14, R12 ; Accumulator = 70000h
CoCMP R14, R13 ; Compares 70000h to 60000h
Here the content of MSW is 0500h, i.e. C = 1, Z = 0 and N = 1.
To test if the Accumulator was greater than or equa l t he c ompared value, the "normal" test, according t o
the description in the ST10 Programming Manual, would be:
JNB MSW.10, Greater ; If C flag cleared, then greater than or equal
With the implementation, this test does not provide the expected result.
To obtain the correct compari son, use instead:
JB MSW .10, Greater ; C flag set: 60000h < 70000h (60000h-70000h implemented)
; i.e. the accumulator is greater than or equal compared value
2.3 - MAC.10 - E Flag Ev aluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled
The Logical and the Arithmetic Right Shift instructions (CoSHR/CoASHR) are specififed not to be affected
by the saturation mode (MS bit of the MCW register): the shift operation is always made on the 40 bits of
the accumulator. The result shifted in the accumulator is never saturated. Only when the saturation mode
is enabled, the evaluation of the E Flag (in the MSW register) is erroneous.
Comment to the example:
In the example below (Table 1), t he E F lag is kep t c leared however MAE is us ed: bi t 0 of MAE has been
shifted into bit 15 of MAH. The MAE part has been used and it contents significant bits but the E Flag has
not been set.
The content of the flags is given after the execution of the instruction.
Workaround:
If the MAE flag is used, the saturation mode must be disabled before running Logical and/or Arihmetic
Right Shift instructions and re-enable just after.
Table 1 : MAC.10 Example
MS Bit is Set, Saturation Mode is Enabled Status of Flags After Instruction Execution
Code
Accumulator Value
(Hexa.)
SL E SV C Z N Remark
MOV
R5, #5555h -- ---- ---- -------
CoLOAD
R5, R5 00 5555 5555 000000Right
NOP 00
5555 5555 000000Right
MOV
MSW, #007Fh 7F 5555 5555 000000Righ t
NOP 7F
5555 5555 000000Right
CoSHR
#1 3F AAAA AAAA 00*0000*E is wrong
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